The MOSFET Transistor

Digital Systems M
Master Degree in Electronic Engineering
Curriculum Electronic technologies for
Big-Data and Internet of Things
A.A. 2018-19

Prof. Elena Gnani

 Outline
 PN Junction
 Intuitive understanding of device operation
 Analysis of I/V characteristics
 Analysis of deep-submicron effects
 Simplified models for manual analysis in digital domain
 I/V characteristics of NMOS and PMOS transistors
 MOSFET dynamic model
PN Junction
The Diode
B Al A
SiO2

Cross-section ofpn-junction in an IC process

A Al
p A

B B
One-dimensional
representation diode symbol

Mostly occurring as parasitic element in Digital ICs

Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
p n

hole drift
electron drift
Charge 
Density
+ x (b) Charge density.
Distance
-

Electrical 
Field x
(c) Electric field.

V
Potential
 (d) Electrostatic
x potential.
-W 1 W2
Diode Current
Models for Manual Analysis

ID = IS(eV D/T – 1) ID
+ +
+
VD VD VDon
–
– –

(a) Ideal diode model (b) First-order diode model

Junction Capacitance
Secondary Effects
0.1
ID (A)

–0.1
–25.0 –15.0 –5.0 0 5.0
VD (V)

Avalanche Breakdown
The MOS(FET) Transistor
 What is a Transistor?

A Switch! MOS Transistor

G
VGS  V T |VGS|

Ron
S D S B D
CMOS Cross Section
Threshold voltage: concept

+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

B
 Threshold Voltage
VTN 0 = F MS + 2f F + g 2f F
KT Nsub REMEMBER THIS:
fF = ln POWERFUL LOW-POWER
q ni KNOB

1
g= 2qe Si Nsub
Cox
VT (VBS ) = F MS + 2f F + g 2f F -VBS
= VTN 0 + g { 2f F -VBS - 2f F }
The Body Effect
0.9

0.85

0.8

0.75

0.7
VT (V)

0.65

0.6

0.55

0.5

0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
V (V)
BS

REMEMBER THIS: POWERFUL LOW-POWER KNOB

Bulk Pin Exposed (Body-Bias Ready)
 The linear region
Vds < Vgs-Vt
VGS VDS
S
G ID
D

n+ –
V(x)
+ n+

L x

p-substrate

MOS transistor and its bias conditions

Linear dependency between Id and Vds (for small values of Vds)

 The saturation region
VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

When Vds increases the channel voltage is larger

Pinch-off
 the threshold all along the channel stops
 VDS = VGS – VT (no more linear dependency on VDS)
Current-Voltage Relations
Long-Channel Device
Can be ignored for small values of Vds
A model for manual analysis
 Linear Region
IDLIN-SHORT-CHANNEL = IDLIN-LONG-CHANNEL
Velocity Saturation
u n (m/s)
Saturation Region

Approximation

usat = 105
Constant velocity

Constant mobility (slope = µ)

c = 1.5  (V/µm)
 Perspective
ID
Long-channel device

VGS = VDD
Short-channel device

V DSAT VGS - V T VDS

 ID versus VDS
voltage-controlled resistor voltage-controlled current generator

-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V VGS= 2.5 V

Quadratic Dependence
5

Linear Dependence
2

Saturation VGS= 2.0 V

4 Resistive VGS= 2.0 V 1.5

ID (A)
ID (A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V

0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel (L= 10µm)

Short Channel (L= 0.25µm)
 ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
I D (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel (L= 10µm) Short Channel (L= 0.25µm)

A unified model
for manual analysis

S D

B
Simple Model versus SPICE
-4
x 10
2.5

VDS=VDSAT
2

Velocity
1.5
Saturated
ID (A)

Linear
1

VDSAT=VGT
0.5
VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)
A PMOS Transistor
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8 VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)
Transistor Model
for Manual Analysis
The Sub-Micron MOS Transistor
 Threshold Variations
 Subthreshold Conduction
 Parasitic Resistances
 Threshold Variations
Vt model ignores depletion regions of source and reverse-biased drain junction
 becoming important when shrinking channel length
 VT0 decreases with L for short channel devices

VT VT

Long-channel threshold Low VDS threshold

VDS
L

Threshold as a function of Drain-induced barrier lowering

the length (for low VDS) (for lowL)
L = Lmin in most digital circuits not a big issue Similarly, Vt0 decreases for high Vds  DIBL
Big issue for voltage scaling  power
 Sub-Threshold Conduction
The Slope Factor
-2
10

Linear qVGS
CD
, n  1
-4 nkT
10 I D ~ I 0e
C ox
-6
10 Quadratic
S is DVGS for ID2/ID1 =10
ID (A)

-8
10

-10 Exponential
10

-12
VT Typical values for S:
10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)
Sub-Threshold ID vs VGS
qVGS
 qV
 DS 
I D  I 0e nkT 1  e kT 
 
 

VDS from 0 to 0.5V

Sub-Threshold ID vs VDS qVGS
 qV
 DS 
I D  I 0e nkT 1  e kT 1    VDS 
 
VGS from 0 to 0.3V  
Examples
 CMOS process at 0.13 µm
Vdd = 1.2 V tox = 2 nm (20 Å)
n-channel MOS, L = Lmin = 0.13 um

HS (High Speed)

Vtn = 315 mV Imax/W = 670 uA/um Ioff/W = 58 nA/um
LL (Low Leakage)
Vtn = 450 mV Imax/W = 535 uA/um Ioff/W = 500 pA/um
ULL (Ultra Low Leakage)
Vtn = 630 mV Imax/W = 360 uA/um Ioff/W = 10 pA/um

Imax = Ids(Vgs=Vds=Vdd, Vsb = 0)

Ioff = Ids(Vgs=0, Vds=Vdd, Vsb = 0)
 n-MOSFETs
 Characteristics W = 10 um L = 0.13 um (W/L = 77)
 Ids (Vgs) @ Vds = 0.01 V and Vbs = 0 (linear and log scale)
 Ids (Vgs) @ Vds = Vgs and Vbs = 0
 Ids (Vds) in steps of Vgs with Vbs = 0; HS transistor

 Characteristics W = 0.15 um L= 0.13 um

Ids (Vds) in steps of Vgs with Vbs = 0; HS transistor
 Ids (Vgs) at Vds = 10 mV and Vbs = 0
W = 10 μm, L = 0.13 μm
I (A)
Ids(Vds) at Vds = 10 mV and Vbs = 0
W = 10 μm, L = 0.13 μm
 Ids (Vds) at Vds = Vgs and Vbs = 0
W = 10 μm, L = 0.13 μm
I (A) 6.7 mA

5.3 mA

3.6 mA
 Ids (Vds) with ΔVgs = 0.3 V and Vbs = 0
W = 10 μm, L = 130 μm
6.7 mA
(Vgs = 1.2 V
I (A) Vgs –VTN ≈
0.885 V)

Linear
Relationship

2.1 mA
(Vgs = 0.6 V
Vgs –VTN ≈
0.285 V)

Vtn,HS = 0.315 V
 Output characteristic
Ids (Vds) with ΔVgs = 0.3 V at Vbs=0
W = 0.15 μm, L = 0.13 μm
I (A)

0.105 mA

Linear
Relationship
 Comparison of n-MOS and p-MOS HS
characteristics

Characteristics: W=10 μm L= 0.13 μm

 Ids (Vgs) at |Vds| = 0.01 V and Vbs = 0

 Ids (Vgs) at Vds = Vgs and Vbs = 0
 Ids (Vds) at |Vgs| = Vdd and Vbs = 0
 CMOS process at 0.13 µm, year 2003
Vdd = 1.2 V tox = 2 nm (20 Å)
HS (High Speed)
• Vtn = 315 mV Vtp = -300 mV
• (Imax/W)n = 670 uA/um (Imax/W)p = 320 uA/um
(Imax/W)n / (Imax/W)p = 2.09
MOBILITY!!!
• (Ioff/W)n = 58 nA/um (Ioff/W)p = 11 nA
(Ioff/W)n / (Imax/W)p = 5.2

• LL (Low Leakage)
(Imax/W)n / (Imax/W)p = 2.22
• ULL (Low Leakage)
(Imax/W)n / (Imax/W)p = 2.11
 Comparison of n-MOS e p-MOS turn-on
characteristics at |Vds| = 10 mV

In,lin
I (A)

In,lin/Ip,lin
≈ 3.6

Ip,lin
 Comparison of n-MOS e p-MOS turn-on
characteristics at Vds = Vgs

In,sat
I (A)

In,sat/Ip,sat

Ip,sat ≈ 2.12
 Comparison of HS n_MOS and p-MOS
output characteristics |Ids| / |Vds| at |Vgs| = Vdd
I (A)

In,sat

In,sat/Ip,sat

Ip,sat ≈ 2.12
 Ioff vs. Temperature
Vds = 1 V, Vsb = 0, Vgs = 0

Ioff (nA) +115%

43 nA a 27°C

-40% temp (°C)

 Imax vs. Temperature
Vds = 1 V, Vsb = 0, Vgs = 1 V

+10%
514 uA
Imax (uA) 27 °C

-20%

temp (°C)
 Imax vs. Vdd 49

705 uA
Vdd = 1.25 V

514 uA
Vdd = 1.0 V 591 uA
475 uA
Vdd = 1.1 V
Vdd = 0.95 V

T = 27°C , typical parameters, LVT

 Imax vs. PVT
(nMOS VTL, W = 415 um)

Vdd T Process Imax

(Vgs = Vds = Vdd)
1V 27 °C Typ 514 uA Typical corner
0.90 V 125 °C Slow 286 uA
1.1 V 0°C Fast 701 uA Slow corner

Fast corner

Fast and Slow Corners are used for design and Signoff,
Typical Corner is good for estimations.
MOS Capacitances
Dynamic Behavior
Dynamic Behavior of MOS Transistor
G

CGS CGD

S D

CSB CGB CDB

B
The Gate Capacitance
Polysilicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld
overlap
Top view
Gate oxide
tox
n+ L n+

Cross section
Gate Capacitance
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

CG C
WLC ox WLC ox
CG C
2WLC ox
CG CS
C G CS = CG CD 3
WLC ox CGC B WLC ox
2 2 CGCD

VG S 0 V DS /(V G S-V T) 1
Vt
Capacitance as a function of VGS Capacitance as a function of the
(with VDS = 0) degree of saturation
 Gate Capacitance
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

Diffusion Capacitance
Channel-stop implant
NA1

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS Substrate N A
Parasitic Resistances

Polysilicon gate
Drain
contact
G LD

VGS,eff

W
S D

RS RD

Drain
 Summary of MOSFET Operating
Regions
 Strong Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT
 Weak Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence
 Near Threshold VGS ~ VT
 Extremely relevant in modern digital systems
 To be continued…