03 Design Metrics PDF

IC figure of merits
Digital Systems M
Master Degree in Electronic Engineering
Curriculum Electronic technologies for
Big-Data and Internet of Things
A.A. 2018-19
Prof. Elena Gnani
© Digital Integrated Circuits2nd Inverter

The CMOS Inverter: A First Glance
V DD
V in V out
CL

CMOS Inverter Load Characteristics
ID n
V in = 0 V in = 2.5
PMOS Vin = 0.5 V in = 2 NMOS
Vin = 1 Vin = 1.5

Vin = 1.5 Vin = 1
Vin = 1.5 V in = 1
V in = 2 Vin = 0.5
Vin = 2.5 Vin = 0
Vout

CMOS Inverter VTC
Vout
NMOS off
2.5 PMOS res
NMOS s at
PMOS res
2
NMOS sat
1.5
PMOS sat
1
NMOS res
PMOS sat NMOS res
0.5
PMOS off
0.5 1 1.5 2 2.5 Vin

Simulated VTC
2.5
1.5
Vout(V)
0.5
0
0 0.5 1 1.5 2 2.5
V (V)
in

CMOS Inverter
N Well VDD
VDD PMOS 2l
Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS
NMOS
GND

Two Inverters
Share power and ground
Abut cells
VDD
Connect in Metal

Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
1.5
Vout(V)
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0 0.5 1 1.5 2 2.5
Vin (V)

CMOS Inverter
First-Order DC Analysis
V DD V DD
Rp
VOL = 0
VOH = VDD
V out VM = f(Rn, Rp)
V out
Rn
V in 5 V DD V in 5 0

CMOS Inverter: Transient Response
V DD V DD
Rp tpHL = f(Ron.CL)
= 0.69 RonCL
V out
V out
CL
CL
Rn
V in 5 0 V in 5 V DD
(a) Low-to-high (b) High-to-low

Definitions

Design Metrics
 How to evaluate performance of a
digital circuit (gate, block, …)?
 Cost
 Reliability
 Scalability
 Speed (delay, operating frequency)
 Power dissipation
 Energy to perform a function
12
Cost of Integrated Circuits
 NRE (non-recurrent engineering) costs

 design time and effort, mask generation
 one-time cost factor
 Recurrent costs
 silicon processing, packaging, test
 proportional to volume
 proportional to chip area
13
Yield
No. of good chips per wafer
Y  100 %
Total number of chips per wafer
Wafer cost
Die cost 
Dies per wafer  Die yield
  wafer diameter/2 2   wafer diameter
Dies per wafer  
die area 2  die area
14
Defects

 defects per unit area  die area 
die yield  1  
  
 is approximately 3
die cost  f (die area) 4

15
Reliability―
Noise in Digital Integrated Circuits
v(t) V DD
i(t)
Inductive coupling Capacitive coupling Power and ground

noise
16
DC Operation
Voltage Transfer Characteristic
V(y)
VOH = f(VOL)
V f
OH
V(y)=V(x)
VOL = f(VOH)
VM = f(VM)
VM Switching Threshold
V OL
V OL V V(x)
OH
Nominal Voltage Levels (high and low)
17
Mapping between analog and digital signals
V
V
out
“ 1” OH
V Slope = -1
V OH
IH
Undefined
Region
V
IL
Slope = -1
“ 0”
V
V OL
OL
V V V
IL IH in
18
Definition of Noise Margins
"1"
NMHH=VOH-VIH
V
OH
NM H Noise margin high
V
IH
Undefined
Region
NM L V
V IL Noise margin low
OL
"0" NMHL=VIL-VOL
Gate Output Gate Input
19
Noise Budget
 Allocates gross noise margin to

expected sources of noise
 Sources: supply noise, cross talk,
interference, offset
 Differentiate between fixed and
proportional noise sources
20
Key Reliability Properties
 Absolute noise margin values are deceptive
 a floating node is more easily disturbed than a
node driven by a low impedance (in terms of
voltage)
 Noise immunity is the more important metric –
the capability to suppress noise sources
 Key metrics: Noise transfer functions, Output
impedance of the driver and input impedance of the
receiver;
21
Regenerative Property
Regenerative Non-Regenerative
22
Regenerative Property
v0 v1 v2 v3 v4 v5 v6
A chain of inverters
Simulated response
23
Fan-in and Fan-out
M
N
Fan-out N Fan-in M
24
The Ideal Gate
V out
Ri = 
Ro = 0
Fanout = 
g=
NMH = NML = VDD/2
V in
25
Propagation Delay

Delay Definitions
27
A First-Order RC Network
R
vout
vin C
tp = ln (2) t = 0.69 RC
Important model – matches delay of inverter

28
CMOS Inverter Propagation Delay
VDD
tpHL = f(R on .CL )

= 0.69 Ron CL
Vout
Vout ln(0.5)
CL
1 VDD
Ron
0.5
0.36
Vin = V DD
t
RonCL

Transient Response
3
2.5
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
Vout(V)
tpLH tpHL
1
0.5
-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10

Design for Performance
 Keep capacitances small

 Increase transistor sizes
 watch out for self-loading!
 Increase VDD (????)

Delay as a function of VDD
5.5
4.5
4
tp(normalized)
3.5
2.5
1.5
1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
V (V)
DD

Device Sizing
-11
x 10
3.8
3.6 (for fixed load)
3.4
3.2
tp(sec)
2.8 Self-loading effect:

2.6 Intrinsic capacitances
dominate
2.4
2.2
2
2 4 6 8 10 12 14
S

Impact of Rise Time on Delay
0.35
0.3
tpH L (nsec)
0.25
0.2
0.15
0 0.2 0.4 0.6 0.8 1
trise (nsec)

NMOS/PMOS ratio
-11
x 10
5
tpLH tpHL
4.5
tp b = Wp/Wn
tp(sec)
3.5
3
1 1.5 2 2.5 3 3.5 4 4.5 5
b
Tp LH and HL very sensitive to Beta!!!

Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)
Peak power:
Ppeak = Vsupplyipeak
Average power:
1 t T Vsupply t T
Pave   p (t ) dt   isupply t dt
T t T t
40
Energy and Energy-Delay
Power-Delay Product (PDP) =

E = Energy per operation = Pav  tp
Energy-Delay Product (EDP) =

quality metric of gate = E  tp
41
A First-Order RC Network
Vdd
E0->1 = C LVdd2
R PMOS i
vout supply
A1 NETWORK
vAinN CVLout
CL
NMOS
NETWORK
T T Vdd
=  P  t  dt = V = C V 2
dd  sup ply 
E i t dt = V  C dV
01 dd L out L dd
0 0 0
T T Vdd
1 2
cap   out ca p 
E = P t dt =  V i t dt = -C  V
 C L Vout dVout = --
ca p 2 L dd
0 0 0
42
Summary
 Digital integrated circuits have come a long
way and still have quite some potential left for
the coming decades
 Some interesting challenges ahead
 Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
 Understanding the design metrics that govern
digital design is crucial
 Cost, reliability, speed, power and energy
dissipation
43

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IC figure of merits

Prof. Elena Gnani

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

PMOS Vin = 0.5 V in = 2 NMOS

Vin = 1 Vin = 1.5

Vin = 2.5 Vin = 0

© Digital Integrated Circuits2nd Inverter

0.5 1 1.5 2 2.5 Vin

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

 NRE (non-recurrent engineering) costs

die cost  f (die area) 4

Inductive coupling Capacitive coupling Power and ground

Nominal Voltage Levels (high and low)

 Allocates gross noise margin to

© Digital Integrated Circuits2nd Inverter

Important model – matches delay of inverter

tpHL = f(R on .CL )

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

 Keep capacitances small

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

3.6 (for fixed load)

2.8 Self-loading effect:

© Digital Integrated Circuits2nd Inverter

© Digital Integrated Circuits2nd Inverter

Tp LH and HL very sensitive to Beta!!!

Power-Delay Product (PDP) =

Energy-Delay Product (EDP) =

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