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  • CTS

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    RamakrishnaRao Soogoori
    17 views2 pages
    This document contains questions about clock tree synthesis (CTS), clock skew, buffer selection, metal layer usage for clocks, and analyzing setup and hold violations. It asks about the inputs and purpose of CTS, defining insertion delay and skew, how to select clock slew, differences between normal and clock buffers, which metal layers are used for clocks and why, impacts and fixes for missed setup and hold violations, reasons for not doing hold analysis before CTS, differentiating global and local skew, and analyzing setup/hold slacks at different clock frequencies. Setup and hold analysis questions are included for a sample design with multiple flip-flops.

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    clock tree synthesis

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    This document contains questions about clock tree synthesis (CTS), clock skew, buffer selection, metal layer usage for clocks, and analyzing setup and hold violations. It asks about the inputs and purpose of CTS, defining insertion delay and skew, how to select clock slew, differences between normal and clock buffers, which metal layers are used for clocks and why, impacts and fixes for missed setup and hold violations, reasons for not doing hold analysis before CTS, differentiating global and local skew, and analyzing setup/hold slacks at different clock frequencies. Setup and hold analysis questions are included for a sample design with multiple flip-flops.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    17 views2 pages

    CTS

    Uploaded by

    RamakrishnaRao Soogoori
    This document contains questions about clock tree synthesis (CTS), clock skew, buffer selection, metal layer usage for clocks, and analyzing setup and hold violations. It asks about the inputs and purpose of CTS, defining insertion delay and skew, how to select clock slew, differences between normal and clock buffers, which metal layers are used for clocks and why, impacts and fixes for missed setup and hold violations, reasons for not doing hold analysis before CTS, differentiating global and local skew, and analyzing setup/hold slacks at different clock frequencies. Setup and hold analysis questions are included for a sample design with multiple flip-flops.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    1) What is CTS? Explain clock behavior before-CTS and after-CTS?

    2) What are the inputs to CTS step? 

    3) What is Insertion Delay or latency of clock tree?

    4) What is clock-skew. How does skew impact timing?

    5) How do you pick clock slew/transition target for the clock tree in your design.
    6) What is the difference between normal buffer and clock buffer?
    7) Which metal layers in a given metal stack are used for clock routing and Why?

    8) Suppose you missed fixing a setup violation and found it post silicon. What is the impact. What would
    you want to do now.

    9) Suppose you missed fixing a hold violation and found it post silicon. What is the impact. What would
    you want to do now.
    10) Why don't we perform Hold analysis before CTS?

    11) Differentiate b/w global and local skews

    12) Assume that we time a design for setup and hold with clock period defined as 1ns and see setup and
    hold WNS of +200 ps and +150 ps respectively. Now if the SDC is updated such that the new clock
    frequency is 1.5GHz and then if the design is timed again, what are the new setup and hold WNS you
    would see in the design.

    13) Note the below design with 3 flipflops. Consider a propagated clock and answer the questions
    below. Clock tree is denoted using green colored lines.

    Assume the following

    input delay on input port IN1 = 250 ps

    input delay on input port IN2 = 800 ps

    output delay on output port OUT = 250 ps


    C1 is combinational delay = 50 ps

    C2 is combinational delay = 250 ps

    Setup time of FF1 = 250 ps & Hold time of FF1 = 300 ps

    Setup time of FF2 = 250 ps & Hold time of FF2 = 300 ps

    Setup time of FF3 = 250 ps & Hold time of FF3 = 300 ps

    CK-Q delay of FF1 = 250 ps

    CK-Q delay of FF2 = 250 ps

    CK-Q delay of FF3 = 250 ps

    Delay of clock buffer chain “A” = 600 ps

    Delay of clock buffer chain “B” = 50ps

    Question 1 : What is the maximum frequency this design can operate at ?

    Question 2 : Given that the clock frequency is set to 1GHz, What is the setup WNS of this design?

    Question 3 : Does this design have any hold violations. If yes, how many hold violations ? what is the
    worst hold slack ?

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