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    This document contains a quiz question and model answer about optimizing the frequency of a digital ASIC design consisting of 4 cascaded logic blocks. The maximum frequency is 500 MHz due to the longest block delay of 500 ps. Pipelining with one register between blocks can achieve this frequency by balancing the delays, at the cost of increased latency, area, and power. To reach a target frequency of 100 MHz, options include partitioning each block into many sub-blocks with 10 ps delay each and inserting over 100 registers, or using a faster technology to reduce all block delays by a factor of 10 but at a higher cost.

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    This document contains a quiz question and model answer about optimizing the frequency of a digital ASIC design consisting of 4 cascaded logic blocks. The maximum frequency is 500 MHz due to the longest block delay of 500 ps. Pipelining with one register between blocks can achieve this frequency by balancing the delays, at the cost of increased latency, area, and power. To reach a target frequency of 100 MHz, options include partitioning each block into many sub-blocks with 10 ps delay each and inserting over 100 registers, or using a faster technology to reduce all block delays by a factor of 10 but at a higher cost.

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    © All Rights Reserved
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    1 views2 pages

    Quiz 2 - Model Answer

    Uploaded by

    201901363
    This document contains a quiz question and model answer about optimizing the frequency of a digital ASIC design consisting of 4 cascaded logic blocks. The maximum frequency is 500 MHz due to the longest block delay of 500 ps. Pipelining with one register between blocks can achieve this frequency by balancing the delays, at the cost of increased latency, area, and power. To reach a target frequency of 100 MHz, options include partitioning each block into many sub-blocks with 10 ps delay each and inserting over 100 registers, or using a faster technology to reduce all block delays by a factor of 10 but at a higher cost.

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    of 2

    University of Science and Technology

    Nanotechnology and Nanoelectronics Engineering


    NANENG 501 – Advanced Digital ASIC Design
    Instructor: Dr. Hassan Mostafa
    TAs: Bassant Hassan – Mohamed Gharib
    Fall 2021

    Quiz 2 – Model Answer

    A design is consisted of 4 cascaded blocks of combinational logic with estimated delays as


    shown below. This design operates with a clock frequency of 1 .

    Block #1 Block #2 Block #3 Block #4


    $" ! " ! "# ! !

    It is required to:
    1- Find the maximum frequency that can be achieved by this system and propose how to
    achieve it.
    Maximum frequency is related to the minimum possible clock period for this system, which is
    the maximum combinational logic block delay. So,
    1 1
    = = =2
    ( #4) 500

    To achieve this frequency, registers could be inserted between the blocks (Pipelining) to reduce
    the critical path delay. Only one register is required to have balanced combinational logic delays
    between registers. This approach increases the latency by one clock cycle and increase the power
    and area of the design by that of one flip-flop.

    Block #1 Block #2 Block #3 Block #4


    FF
    $" ! " ! "# ! !

    1
    2- Propose a modification that enhances the frequency of operation to 100 .
    To achieve 100 , the critical path delay should be reduced to 10 . There are several
    approaches that reduce the delay and each with its cost:
    a. Partition the combinational logic blocks:
    Assuming that each block could be divided into sub-blocks of 10 delay, the number of
    sub-blocks would be 100. Then, 3 flip-flops are inserted between the blocks and 97 flip-
    flops (20 + 9 + 18 + 49) are inserted between the sub-blocks to achieve the required
    critical path delay. The cost is huge latency (+100 clock cycle), area, and power.

    Block #1

    FF FF … FF
    Sub-Block #1 Sub-Block #2 Sub-Block #21
    " ! " ! " !

    b. Use faster technology:


    Implementing the design using faster technologies (*+ transistors) could reduce the
    delay of the blocks by a factor of 10. As a result, the critical path is reduced from
    1000 to 10 . The cost is buying a new technology with higher price and higher
    power.

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