Heat Transfer Engineering

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Microjet Cooler with Distributed Returns

Govindarajan Natarajan & R. J. Bezama

To cite this article: Govindarajan Natarajan & R. J. Bezama (2007) Microjet Cooler with Distributed
Returns, Heat Transfer Engineering, 28:8-9, 779-787, DOI: 10.1080/01457630701328627

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Heat Transfer Engineering, 28(8–9):779–787, 2007
Copyright

C Taylor and Francis Group, LLC
ISSN: 0145-7632 print / 1521-0537 online
DOI: 10.1080/01457630701328627

Microjet Cooler with Distributed

Returns

GOVINDARAJAN NATARAJAN and R. J. BEZAMA

Server and Technology Group, IBM Corporation, East Fishkill, New York, USA

This paper details the technology elements developed to design and manufacture a liquid microjet array cooling device for the
thermal management of very high power dissipating electronic chips. Multilayer ceramic technology (MLC) is used to build
the cooling device with micron-size jet arrays, which includes a distributed return network for the spent fluid. Intertwined
microchannel flow networks inside the cooler body distribute the flow in and out of the device. A cooler with 1600 jets and
1681 interstitial returns for the drains built using glass ceramic material is discussed. When tested with an 18 mm heated
silicon chip and an average convection coefficient of 0.052 MW/m2 K, the device demonstrated a cooling capability greater
than 2.5 MW/m2 with a water pressure drop of < 70 kPa. Further extension of the cooling capability to greater than 6 MW/m2 ,
as predicted by the simulation, is also discussed.

INTRODUCTION direction. In addition, the new trend to fabricate microproces-

Single-phase liquid cooling is again becoming the dominant
cooling technology used to dissipate heat from high performance
microprocessors. In the past, this cooling technology was usu-
ally found inside supercomputers and mainframe computers,
when the electronic logic circuitry was based on bipolar transis-
tors; however, with the advent of complementary metal-oxide
semiconductor (CMOS) transistors and lower power dissipation
per CPU, air cooling became the main cooling technology for
all kinds of computing devices mainly to minimize operating
costs. However, the integration of higher operating frequency
electronic devices into silicon chips and the increase in transis-
tor density requires a higher cooling capability of the micro-
processor assembly. The chip technology progress warrants the
cooling capability to exceed the thermal performance of typi-
cal heat spreaders with forced air flow. Also, the need to keep
logic functions close together within the microprocessor chip to
minimize signal propagation delay creates localized areas in the
chip with significantly higher power dissipation densities than
the chip average. These localized areas, known as hot spots, are
difficult to control thermally with heat spreaders because the ra-
dial heat flux away from the hot spot creates additional thermal
gradient in the typical cooling device along the assembled axial
Address correspondence to Dr. Govindarajan Natarajan, Server and Technol-
ogy Group, IBM Corporation, East Fishkill, 2070 Route 52, Hopewell Junction,
NY 12533, USA. E-mail: gnataraj@us.ibm.com
779
sors with more than one CPU per chip magnifies the thermal
management problem of the microprocessor chip by increas-
ing the number of hot spots in every chip. While both single-
and two-phase liquid coolers are capable of providing high ther-
mal performance and hot spot thermal management functions,
only single-phase coolers, such as microchannel and jet im-
pingement coolers, have demonstrated consistently the thermal
performance above 2 MW/m2 [1]. Additionally, in the case of
microprocessor cooling, they meet the operating temperature
range requirement as well, where the maximum temperature
should not exceed an intended value (e.g., 85◦ C), and with an
associated liquid pressure drop in the cooler maintained below
100 kPa. The use of single fluid two-phase coolers, such as heat
pipes or vapor chambers, is limited to performance below 1
MW/m2 [2]. Above this range, nucleation boiling occurs at the
evaporator section followed by potential wick dryout when gas
bubbles interfere with the evaporator liquid feeding lines. Also,
evaporation-based coolers using high pressure drop liquid spray
nozzles are also limited in cooling performance, which is below 1
MW/m2 to avoid the difficulties of providing consistent cooling
capability when the evaporator regime changes from a control-
lable film boiling mode to the unpredictable nucleation boiling
mode.
Single-fluid phase jet arrays have been used in industry for
heating or cooling processes for a long time, mainly because they
can deliver higher localized heat transfer rates than the typical
forced convection-based devices. Also their performance opti-
mization can be done with the simple manipulation of the device
780 G. NATARAJAN AND R. J. BEZAMA
Figure 1 A schematic view of ceramic microjet cooler with distributed
returns.
geometric parameters, sometimes with only modest impact to the
device operating pressure. For a given jet fluid velocity, the av-
erage heat transfer coefficient will increase if the jet diameter is
reduced while the device pressure drop is not directly dependent
on this parameter. Information on the design and optimization
methodology of generic jet arrays can be found in the exten-
sive compilation of Martin [3], and Webb and Ma [4]. The cited
works apply to both submerged (one phase) and free surface (two
phase, no boiling) jet arrays operating at relatively high jet ve-
locities (jet Reynolds number above 2000). Unfortunately, under
these conditions, it is easy to generate large pressure drop in the
cooler, which is not desired as it affects severely the mechanical
reliability of the overall system. Consequently, we need to limit
the fluid velocity to a lower range with related Reynolds number
well below 500, and then increase the heat transfer rate propor-
tionately by reducing the jet array geometry. Because shrinking
the jet array parameters increases the jet count dramatically, it
is necessary to consider the impact to the thermal performance
uniformity of the cooler. Jet arrays with large jet counts result
in significant average drainage velocity at the cooler periphery
and hence perform poorly in such locations, as a high drainage
velocity relative to the jet velocity will reduce the local heat
transfer rate.
Recently, Berger et al. [5] and Michel et al. [6] introduced the
concept of distributed returns in micron-sized jet arrays. Accord-
ingly, micro-sized jet array can become a powerful alternative
to other high performance coolers due to the use of a distributed
returns network in a single manifold, as shown in Figure 1.
Here, the impinging jets are located at the center of each indi-
vidual square, and the returns are distributed at the corners of
each squares. This design change eliminates the impact of fluid
drainage on thermal performance as well as the restriction on
the limit on number of jets on the device. In addition, distributed
return technology also simplifies device optimization for ther-
mal performance by separating the design into small individual
cells that can be optimized separately from the group and then
replicated over the entire cooling area. However, the combined
technology including micron-scale jet arrays and distributed re-
turn generates a new flow distribution build problem. It requires
the creation of a complex three-dimensional intertwined mani-
fold structure to supply the fresh cold fluid and collect the spent
hot fluid from the jet impingement surface.
heat transfer engineering
This paper describes how this problem has been resolved
with the use of multilayer ceramic (MLC) fabrication technol-
ogy. First, some of the issues associated with the selection of an
appropriate jet array design with and without distributed returns
are discussed. Then, the process of building a cooling mod-
ule with its associated flow distributed manifold is described.
The design of an unit jet cell of the manifold involves the use
of computational fluid dynamics, or CFD, by optimizing the
design thermal performance against customized alternate unit
cell design cases. Finally, some of the results from CFD sim-
ulations and experimental testing are presented. In all cases,
the fluid selected is water, given the advantages of its thermal
properties.
JET ARRAY DESIGN METHODOLOGY
The design of jet arrays to satisfy a prescribed minimum
heat transfer performance and maximum cooler pressure drop
requires an iterative approach that combines both CFD simu-
lation and experimental verification effort. For a given cooling
capability and maximum chip junction temperature, the cooler
device must provide the prescribed performance within a given
maximum pressure drop, usually set to 50–100 kPa to avoid
leaks in external feeding line and manage with the capability of
existing fluid pumps.
The main motivation for the construction of an MLC cooler
was to design and evaluate a cooler made of thermally non-
conductive material when in use with an 18 mm2 silicon chip for
a cooling capability of ∼ 2 MW/m2 and a cooler pressure drop
of <70 KPa (or <10 psig) between inlet and outlet connectors.
Other factors such as a water supply at 22◦ C as coolant and the
heat dissipating chip maximum temperature <85◦ C were also
used for cooler design optimization. Under these conditions,
the total thermal resistance of such a system needs to be equal
to or less than 32.5 m2 K/MW. But the thermal resistance of
a typical silicon chip is approximately 5.8 m2 K/MW, assuming
130 W/mK for the thermal conductivity and ∼750 microns as the
typical chip thickness. Therefore, the target thermal resistance
for the cooler is 23.7 m2 K/MW. This demands the cooler to yield
an average convection coefficient greater than 0.042 MW/m2 K
to meet the design target.
While the thermal performance of a microjet array with or
without distributed return network can be estimated with rea-
sonable accuracy using an appropriate commercially available
CFD code, trying to calculate an accurate pressure drop inside
a complex network manifold, with micron-sized features and
built using MLC technology, is not trivial. Thus, the design ap-
proach taken here is to use CFD code to determine the jet array
dimensions and pressure drop only in the jet impingement cav-
ity, while the determination of total cooler pressure drop is done
experimentally.
The design methodology followed here can be divided into
two sequential steps. First, the geometric details of the jet array
section of the cooler are selected using the three-step procedure
vol. 28 nos. 8–9 2007
 G. NATARAJAN AND R. J. BEZAMA 781

detailed below. Then, the flow manifold section that feeds the
jet array section of the cooler is designed by taking advantage of
the capabilities of MLC technology. Of course, the complexity
and effort required of the second section depends mainly on
whether the cooler does or does not include a distributed return
manifold, and so this design aspect must be defined together
with the selection of jet array geometry.
Many combinations of cooler geometric parameters will sat-
isfy the given requirements for thermal performance and cooler
pressure drop. Thus, the first step in the design effort is to select
a manufacturable jet pitch and diameter capable of delivering
the required thermal performance. The existing MLC manufac-
turing plant at IBM East Fishkill builds sophisticated micro-
electronic MLC modules for high-end computers with stringent
ground rules for features. This gives us flexibility to test the best
options possible. Considering that the allowed pressure drop is
relatively low, the jet velocity for cooler using water as fluid
was kept below 2.5–3.0 m/s. Under these conditions, a jet diam-
eter of 200 microns or less will operate with a low jet Reynolds
number, such as Re < 500, which is well within the laminar
flow regime. Nevertheless, an initial estimate for the jet-to-jet
pitch, jet diameter, and jet-to-chip gap can be obtained using the
following correlation provided by Martin [3], in spite of the fact
that the given correlations apply to jet arrays without distributed
return and relatively large jet Reynolds number, or Re > 2000,
which can get into the turbulent jet regime.

Nu = 0.5K1 Re0.67 Pr0.42 (1)

where

K1 = K2 (1 + ((H/D)K3 /0.6)6 )−0.05

K2 = K3 (2 − 4.4K3 )/(1 + 0.2(H/D − 6)K3 )
K3 = 0.886/(P/D)
2000 < Re < 100,000; 0.004 < K23 < 0.040; 2 < H/D < 12
To verify the applicability of using Martin’s correlation to pre-
dict jet array Nusselt number for low Reynolds number regime,
we have run a limited number of simulations using CFD code us-
ing jet array geometric parameters in a range that is compatible
with MLC fabrication technology. The results of this compari-
son, illustrated graphically in Figure 2a (Re = 75 to 600), show
that Martin’s correlation systematically underpredicts the jet
Nusselt number by about 10–20% in this low Reynolds regime;
hence, it is suitable for use to get a preliminary design region of
interest for the desired jet array.
The most significant aspect of Martin’s correlation, which
makes it a powerful design tool, is that it decouples the jet
geometric parameters from the fluid operating conditions and
thermal properties. In our analysis, all geometric parameters
are made dimensionless using the jet diameter as characteristic
length. A detailed scrutiny of correlation dependency on jet ge-
ometry suggests maximum thermal performance peaks for any
heat transfer engineering
Figure 2 (a) Convection coefficient for jet impingement using water at room
temperature as a function of jet diameter. In all cases, the jet velocity is 3 m/s,
P/D = 3.5, and H/D = 2. Martin’s correlation is used to extrapolate the convection
coefficient to lower Reynolds number. (b) Thermal coefficient K1 , from Eq. (1),
depends only on the geometric ratios P/D and H/D. Depending on H/D ratio,
the optimal P/D ratio falls in the 3-4 range.
jet diameter when the dimensionless jet pitch falls in the range of
3 to 4 units, as per Figure 2b. Also, the correlation predicts an in-
creasing thermal performance with a decreasing dimensionless
jet-to-chip gap size and projects even higher performance below
the given dimensionless gap limit of 2 units. However, this trend
is not supported by CFD simulations. Instead, CFD predicts op-
timal thermal performance with limited pressure drop when the
dimensionless gap is about 2 units. As the dimensionless gap
ratio gets below 2 units, frictional losses at the top and bottom
gap surfaces increase sufficiently to reduce the jet vortex circu-
lation speed and thus reduces the heat transfer rate. Using this
approach, we estimate that the jet diameter and pitch must fall
within 100–150 microns and 400–450 microns, respectively, to
deliver the target cooling rate of 2 MW/m2 .
The second step is to decide if distributed return is needed
or not. Because distributed return increases significantly the
vol. 28 nos. 8–9 2007
782 G. NATARAJAN AND R. J. BEZAMA

Figure 4 Contours of velocity under a submerged jet array with 625 jets. Jet
numbers start from 1 at center of array. Jet diameter is 100 microns, H/D = 3,
P/D = 4, V = 3 m/s, q = 4 MW/m2 .

chip. The resulting velocity fields are shown in Figure 4. For

this array configuration, the expected average drainage velocity
around jet number 12 (array periphery) is approximately 1.5 m/s,
or half the jet velocity, though the simulation shows the drainage
flow already perturbing the flow under jet number 6.
The impact to the local heat transfer coefficient was also eval-
uated from the simulation, and the resulting local convection
coefficient can be seen in Figure 5. For this jet array configura-
tion, the impact of drainage flow on heat transfer coefficient is
already significant after jet number 6, and increases to a maxi-
mum of 50% reduction in average convection coefficient under
jet number 12. Thus, to avoid such a large reduction in ther-
mal performance at the periphery, this particular jet array can be
Figure 3 Increase in relative drain velocity, VD /VJ , with the number of jets redesigned to include distributed return drainage. Because the
in the jet array (a) when all four sides are open for drainage of spent fluid and target chip is 18 mm2 , it will require 1600 jets in the array to
P/D = 4.0, and (b) when only two opposite sides are open for drainage of spent satisfy a jet-to-jet pitch of 450 microns and require distributed
fluid and P/D = 4.0.
return design to maintain an acceptable cooling rate distribution
across the entire chip.
complexity of the cooler build, it is best to reserve this tech-
nology for those cases where very high thermal performance
is needed. To answer this question, the following parameters
have to be known: total number of jets in the design, jet pitch,
jet diameter, gap size, and the number of sides in the cooler de-
vice available for fluid drainage, assuming no distributed returns.
These parameters determine the average drainage velocity at the
chip periphery, as shown in Figures 3a and 3b, in dimensionless
form (i.e., average drainage velocity over jet average velocity),
for a specific case where the dimensionless jet pitch is 4 units
and the dimensionless gap size is 2, 3, or 4 units.
Ideally, the average dimensionless drainage velocity at the
periphery of the chip should be kept well below 0.5 to avoid
significant impact to thermal performance of the peripheral jets.
To illustrate the impact of high velocity drainage on heat transfer
rates, a CFD simulation was built and run under the following
conditions: 25 × 25 jet array with jet diameter of 100 microns; Figure 5 Contours of local convection coefficient under a submerged jet ar-
H/D = 3, P/D = 4, VJ = 3 m/s, peripheral drain on all four sides, ray with 625 jets. Jet numbers start from 1 at center of array. Jet diameter is
and q = 4 MW/m2 at the bottom of an 800 microns thick silicon 100 microns, H/D = 3, P/D = 4, V = 3 m/s, q = 4 MW/m2 .

heat transfer engineering vol. 28 nos. 8–9 2007

 G. NATARAJAN AND R. J. BEZAMA 783

Table 1 Parameters and CFD results for three different jet arrays with
distributed return

Test case Case 1 Case 2 Case 3

Setup parameters
Jet pitch [microns] 500 500 350
Gap height [microns] 400 400 200
Jet velocity [m/s] 2.5 7.0 25
q” [MW/m2 ] 2.0 5.0 10.0
Results
Re 250 700 2500
Maximum chip temp [◦ C] 59.7 78.8 97.5

P [kPa] 1.7 7.3 48
h [MW/m2 K] 0.059 0.070 0.352
Nu 9.8 11.7 59
Thermal resistance [m2 K/MW] 19 11 8

In all three cases, the jet diameter is 100 microns, the chip thickness is 700
microns, and the fluid is water at 22◦ C.

Figure 6 Single submerged jet model using axisymmetric 2D geometry of
100 microns diameter jet and heated silicon solid. Fluid is water at 22◦ C, with
V = 9 m/s, H/D = 5, P/D = 5, and q = 2 MW/m2 .
The third and last step is to evaluate the expected thermal
performance of the selected cooler geometry. This work is done
using CFD simulation on a representative section of the cooler
that covers each section of the device. If the thermal performance
falls short of the target, then one or more parameters of the design
or the fluid operating conditions can be changed. The design
procedure should be restarted when the performance delta is
large.
To expedite the search for a suitable jet array geometry, a se-
ries of different cases are evaluated using a simple jet geometry,
like one jet and a 2D-axisymmetric model, as shown schemati-
cally in Figure 6a. The simulation results for this particular case
are shown in Figures 6b and 6c. This example shows a thermal
performance that significantly exceeds the 2 MW/m2 design tar-
get because the maximum temperature shown in Figure 6b is
only 55.3◦ C and the maximum temperature allowed for the chip
is 85◦ C. Unfortunately, the pressure drop of 54 kPa in the cavity
section alone is high, as it consumes most of the pressure drop
budget of 70 kPa. Ideally, the pressure drop in the jet cavity
should be less than 20 kPa for this section of the cooler. The
sensitivity of pressure drop to jet velocity and jet pitch can be
seen in the data shown in Table 1. However, these results ver-
ify that a jet array geometry with pitch below 500 microns is
capable of delivering cooling capability above the 2 MW/m2 K
target.
must connect to the main external fluid supply and return lines,
only a few inlet and outlet ports are desired. But to keep the over-
all device pressure drop low, it is necessary to preserve the fluid
velocity approximately constant and at a value lower than the
jet average fluid velocity. This is accomplished by varying the
manifold microchannel cross-section to a given predetermined
target value. We determined this value to be preferably about
1.5–2 times the total area covered by all the jets, independent
of the local manifold dimensions. With this scheme, the fluid
does not experience multiple changes in average fluid veloc-
ity within the manifold and minimize the cooler total pressure
drop.
To facilitate the manifold design and provide a means for min-
imizing the fluid pressure distribution between all inlets and/or
all outlets, the cooler body is divided into two main sections
with different interconnection functionality. The bottom section
(see Figure 7, section A), which includes at the bottom surface
both jet and distributed return arrays, is subdivided into 100
independent macro-cells each with 16 jet cells and 16 drains.
On the top side of the bottom section, each macro-cell includes
only one supply and one return port. To interconnect the top and
bottom sides of each macro-cell, both inlet and outlet ports inter-
connect to four inlet and four outlet microchannels to distribute
the fluid sideways within the cell volume, and each microchan-
nel is in turn connected to four jets or four return ports on the
cooler bottom surface. The top section of the cooler (see Figure 7,

COOLER FABRICATION PROCESS

The design of the manifold section begins once the jet array
design parameters have been selected. These parameters fully
characterize only the surface of the cooler that faces the surface Figure 7 Back side of the cooler manifold. External water into the manifold
of the chip that needs cooling. As the other side of the cooler and spent fluid out of the manifold as single units.

heat transfer engineering vol. 28 nos. 8–9 2007

784 G. NATARAJAN AND R. J. BEZAMA

Table 2 Conventional MLC process

Slurry formation / raw materials

Casting and blanking
Via punching
Metal paste formulation
Screening and via fill
Screen to form circuit lines
Dry / inspect / repair
Stack / lamination / size / sinter
Plating / electrical test

section B) has two separate flow grids that interconnect all macro
cells to each other and connect to the cooler inlet and outlet ports
on the cooler top surface.
The manufacturing process needed to build the designed
cooler is based on a recent modification [7,8] of existing MLC Figure 8 Array of jet holes and drain holes (150 microns nominal diameter)
manufacturing technology [9], which now enables us to build on square grid (jet-to-jet pitch of 450 microns nominal). The corner holes on the
intricate microchannels and interlayer connecting vias inside a square grid are drains, and the center hole is the jet.
multilayer ceramic substrate. Table 2 outlines the conventional
MLC build process, starting with Al2 O3 –MgO–SiO2 glass par- The microchannels are formed using 150 micron-diameter
ticles mixed with organic binders and solvents to form glass punches. Even though the punch grid is still kept at 450 mi-
ceramic greensheets on casting. These thin cast greensheets, crons to match with jet grids, the movement of greensheets to
when dry and blanked, are relatively easy to handle and are form channels is about a quarter of the channel width per punch
machinable. Individual greensheets are then punched to form stroke. A portion of punch pattern shown in Figure 8 is over-
50 microns or larger circular via holes. These vias become the laid on the microchannel pattern in Figure 9 for understand-
vertical connectors in eventual circuits formed between lay- ing the layered build approach of the MLC technology used
ers. Copper metal powder mixed with organics, in the consis- for the cooler build. We continue to narrow down the num-
tency of a paste, can then be screened on the greensheets us- ber of stringed jet cold fluid conduits and the drain spent fluid
ing masks in the desired circuit pattern. In doing so, the vias conduits (like the ones shown in Figure 10, which is an in-
are also filled simultaneously. After drying or evaporation of termediate greensheet layer) to less than about 4, as shown in
solvents, several screened layers are then stacked precisely to Figure 7 (top view). The feature shapes and sizes are deliber-
align via to via in adjacent sheets. The stack then is laminated ate and verified by CFD to accomplish reduced fluid resistance.
using adequate heat and pressure for a given time. The lami- Figure 7 also shows the cross-section of the ceramic microjet
nates are subjected to proper sinter process to remove the or- fluid distribution manifold with intertwined cold and spent flu-
ganics and co-densify the glass particles and the metal powder idic networks.
with near zero pattern distortion. IBM’s unique sinter process
further crystallizes the glass-copper composite into a cordierite-
based multilayered ceramic with dense co-fired copper inter-
connects. Subsequently, surface finishing and a plating pro-
cess occur to yield electrically good modules capable of
having semiconductor chips mounted on them for use in com-
puter applications.
In order to build a cooler with a 3D microfluidic flow network,
based on the mature and reliable MLC processing, several new
processes had to be developed. The formations of long channels,
preservation of channel dimensions in the assembled green body,
and stability of open structures during sintering are all major
challenges. Figure 8 is an example of the array of holes formed
in a greensheet for jets and drains.
The punch size used to form these holes were 150 mi-
crons in diameter and sheets were moved 225 microns per
punch stroke. The adjacent greensheet layer that strings mul-
tiple jets together and the respective drains together is shown in
Figure 9. Figure 9 Array of microchannels that feeds fluid to multiple jets and drains.

heat transfer engineering vol. 28 nos. 8–9 2007

 G. NATARAJAN AND R. J. BEZAMA 785

Figure 11 Module pressure drop with water at room temperature.

Figure 10 Array of internal interconnect greensheet layer. section and the aluminum enclosure used to hold and feed the
cooler. To quantify the predictability of CFD code when applied
RESULTS AND DISCUSSION to this particular thermal situation, two 3D models were built
using the measured characteristics of the tested module. The
To determine thermal and fluid dynamic characteristic re- models included all 16 jets, 16 drains, and internal microchan-
sponse of this cooling device, the cooler was assembled with nels located in one macro-cell of the cooler bottom section, and
a heated silicon chip with calibrated temperature sensors into a also included a relevant section of the heated chip. One model
test module with appropriate and fully monitored inlet and outlet was built with a 300 micron gap, while the other was built with
fluid ports. The cooler substrates, characterized after sintering, a 165 micron gap. Results of the simulation are shown in Table
have jet diameter of 126 ± 2 microns and jet pitch of 438 ± 6 3, and the pressure and temperature distribution for Case A are
microns. The gap between the silicon chip and the cooler in the shown in Figures 12 and 13, respectively.
assembled module was determined to be 165 ± 5 microns. Inspection of the results for Case C show a very close agree-
The module pressure drop was measured with flowing room ment between the experimental data and the CFD code. Case
temperature water at different flow rates while monitoring the C data projects a convection coefficient of 0.064 MW/m2K
differential pressure between the inlet and outlet ports. The de- (Nu = 12.8) for jet velocity equal to 2 m/s (Re = 252). Scaling
vice pressure drop is made dimensionless by converting the ex- the Nusselt number prediction using Reynolds number with 0.73
perimental data into equivalent lengths, or Le, relative to the jet exponential dependency (reported [10] for equivalent fluid flow
diameter, using the following relationship: conditions) yields Nu = 10.7 for Re = 198 and validates the use

 of this particular CFD code to project thermal performance for
Le =
P Re/32ρV2J (2)
The resulting characteristic pressure drop curve for this device,
shown in Figure 11, projects a maximum operating jet velocity
of 1.8 m/s (Re = 239, Le = 148) for a given maximum operating
pressure drop of <70 kPa.
The thermal response of this cooling device was character-
ized using a heated chip, assembled into a module with a 165
micron gap. Analysis of the thermal data collected shows the
measured convection coefficient of 0.052 MW/m2 K (Nu = 10.4)
with an average jet velocity of 1.6 m/s (Re = 198) and a pres-
sure drop of 53 kPa (Le = 126). Because the pressure drop
calculated with the CFD model for this geometry predicts a
pressure drop of only < 17 kPa for the bottom section, we can
deduce that more than two-thirds of the total pressure drop in
this cooler is driven by the top section of the cooler and may
be related to the specific selection of manifold design on this
section of the cooler. This larger fraction of the total pressure
drop can be reduced significantly by careful redesign of this Figure 12 Pressure distribution for Case A in Table 3.

heat transfer engineering vol. 28 nos. 8–9 2007

786 G. NATARAJAN AND R. J. BEZAMA

Table 3 Sensitivity analysis using CFD for built cooler jet array geometry,
with water at room temperature

Case A B C

Parameters
VJ m/s 2.0 3.0 2.0
Gap Microns 300 300 165
Results

P kPa 17 33 19
TJ ◦C 63.1 57.8 65.3
h MW/m2 K 0.069 0.084 0.064
q max MW/m2 3.1 3.5 2.9

Parameters are jet velocity and gap size. The power flux is 2 MW/m2 , chip
thickness is 780 microns, and jet diameter and pitch are 126 microns and
438 microns, respectively.

these devices, as the deviation between the experimental data

and the model is just ∼ 3%.
Because our MLC technology can produce ceramic products
with internal feature dimensions considerably smaller than the
ones used in the tested cooler, it is important to explore the po-
tential thermal improvement for a cooler designed with higher
jet density. To accomplish this objective we have also evaluated
a design with a jet diameter of 70 microns, jet pitch of 250 mi-
crons, and distributed return using CFD code. This geometry is
manufacturable in our plant, although with considerably greater
effort and challenges than for the device tested.
The results from this simulation, shown in Figure 14, predicts
that this device can deliver a convective heat transfer coefficient
of 0.125 MW/m2 K (Nu = 13.9) with water jet velocity of 3 m/s
(Re = 210). To satisfy the pressure drop requirement, this second
jet array must be designed to exhibit a 50% lower pressure in the
top section of the cooler than the tested cooler. In combination
with a thinner than usual silicon chip (for example, a thickness of
300 microns), this second cooler design can deliver an enhanced
cooling capability greater than 6 MW/m2 .
Figure 14 CFD evaluation for jet-to-jet pitch of 250 microns.
CONCLUSIONS
Multilayer ceramic technology can be used to build liquid
phase jet impingement cooling devices with high performance
cooling capability. The existing MLC manufacturing technology
at IBM East Fishkill has been successfully extended to produce
a glass ceramic-based cooler with micron size jet array and dis-
tributed return flow manifolds. One such cooler was designed,
built, and tested to deliver a cooling capability greater than
2.5 MW/m2 with a pressure drop lower than 70 kPa using water
as coolant.
ACKNOWLEDGMENTS
The authors wish to thank many members of the Packaging
Organization in IBM Fishkill for their help in fabrication and
IBM’s Thermal Team for technology support. The authors also
thank Hilton Toy and Levi Campbell for their assistance with
assembling and testing the thermal modules, and Wynn Herron,
Daniel Berger, Bruno Michel, James Humenik, William Miller,
and Renee Weisman for many fruitful discussions.

NOMENCLATURE

D jet diameter, microns

h convection coefficient, MW/m2 K
H gap between jet and chip, microns
Le equivalent length, Eq. (1)
Nu Nusselt number
P jet-to-jet pitch, microns
Pr Prandtl number
q heat flux, MW/m2
Re Reynolds number
Figure 13 Temperature distribution for Case A in Table 3. TJ chip maximum temperature, K
heat transfer engineering vol. 28 nos. 8–9 2007
 G. NATARAJAN AND R. J. BEZAMA
To fluid inlet temperature, K
VJ jet average velocity, m/s
VD drainage velocity, m/s
Greek Symbols

P pressure drop, kPa
ρ fluid density, kg/m3
REFERENCES
[1] Peterson, G. P., and Ma, H. B., Theoretical Analysis of the Maxi-
mum Heat Transport in Triangular Grooves: A Study of Idealized
Micro Heat Pipes, IMECE, HTD-Vol. 317-1, pp. 185–192, 1995.
[2] Lu, M., Mok, L., and Bezama, R. J., A Vapor Chamber Using
Graphite Foams as Wicks for Cooling High Heat Flux Electronics,
Proc. IPACK2005-73170, ASME InterPACK’05, J. of Electronic
Packaging, vol. 128, pp. 427–431, 2006. 2005.
[3] Martin, H., Heat and Mass Transfer between Impinging Gas Jets
and Solid Surfaces, Adv. Heat Transfer, vol. 13, pp. 1–60, 1977.
[4] Webb, B. W., and Ma, C. F., Single-Phase Liquid Jet Impingement
Heat Transfer, Adv. Heat Transfer, vol. 26, pp. 105–217, 1995.
[5] Berger, D., Bezama, R. J., Herron, W. L., Michel, B., and
Natarajan, G., High Performance Integrated MLC Cooling De-
vice for High Power Density IC’s and Method of Manufacturing,
US Patent Application, 2005.
[6] Michel, B., Brunschwiler, T., Rothuizen, H. E., Kloter, U., and
Linderman, R., Cooling Device, European Patent Application,
2005.
[7] Natarajan, G., and Humenik, J. N., 3D Ceramic Microfluidic De-
vice Manufacturing, J. Physics: Conference Series, vol. 34, pp.
533–539, 2006.
[8] Natarajan, G., Humenik, J. N., and Cranmer, M., Method and
Structure to Enable Fine Grid MLC Technology, US Patent
Application, 2006.
heat transfer engineering
787
[9] Knickerbocker, J. U., Pompeo, F. L., Tai, A. F., Thomas, D.
L., Weekly, R. D., Nealon, M. G., Hamel, H. C., Haridass, A.,
Humenik, J. N., Shelleman, R. A., Reddy, S. N., Prettyman, K.
M., Fasano, B. V., Ray, S. K., Lombardi, T. E., Marston, K. C.,
Coico, P. A., Brofman, P. J., Goldmann, L. S., Edwards, D. L., Zitz,
J. A., Iruvanti, S., Shinde, S. L., and Longworth, H. P., An Ad-
vanced Multichip Module (MCM) for High-Performance UNIX
Servers, IBM J. Res. & Dev., vol. 46, no. 6, pp. 779–804, 2002.
[10] Brunschwiler, T., Rothuizen, H., Fabbri, M., Kloter, U., Michel,
B., Bezama, R. J., and Natarajan, G., Direct Liquid Jet Impinge-
ment with Micron-Sized Nozzle Array and Distributed Return
Architecture, 20th ITHERM Conference, San Diego, Calif., May
2006.
Govindarajan Natarajan is a senior engineer at
IBM Corporation, Server and Technology Group,
East Fishkill, New York, USA. He received his Ph.D.
in chemical engineering in 1981 from the University
of Missouri, Columbia, Missouri, and subsequently
worked at Washington University, St. Louis, Mis-
souri, and Ames Laboratory, Ames, Iowa, as a re-
search associate before joining Advanced Packag-
ing Organization at IBM in 1985. He holds 63 U.S.
patents and more from other regions, co-authored a
book, and published more than 25 papers. Currently, he is working on chip
cooling, micromachining, microfluidics, biochips, and MEMS.
R. J. Bezama is a distinguished engineer at IBM Cor-
poration, Server and Technology Group, East Fishkill,
New York, USA. He received his Ph.D. in chemical
engineering in 1983 from the University of Utah, Salt
Lake City, Utah. He holds more than 30 U.S. patents
and has authored and co-authored approximately 10
technical papers. His current activities include SCM
and MCM microelectronic packaging research and
development, research and development of high per-
formance cooling devices, and providing CFD mod-
eling support to both development and manufacturing engineering groups.
vol. 28 nos. 8–9 2007