Area-Performance Analysis of Hamming Code on 90-nm CMOS Technology

Muhammad Hanif A.K. Khushik, Tayab Din Memon

Hanif.khushk@gmail.com, tayabuddin.memon@faculty.muet.edu.pk

Institue of Information and Communication Technology,

Mehran University of Engineering and Technology, Jamshoro,
Sindh, Pakistan.

Abstract. Faster and reliable communication has always been the need of time. In order to achieve reliability
many techniques are used. Hamming Code is one of such techniques which make communication error free.
As Hamming code has ability to detect and correct single bit errors moreover Extended Hamming Code has the
ability to detect and correct single bit error and it can also detect double bit errors. Its ability to correct single bit
errors saves the time and efforts of communication system. As receiver will not request for resending of data, if
single bit error has occurred. Hamming code enables receiver to request only for retransmission if double bit er-
ror has occurred in channel. The possible solution for the delay in communication is to implement such tech-
niques on faster available devices. Field Programmable Gate Arrays (FPGAs) are considered to be the fastest
technology available, currently. In this paper, we have designed and implemented efficiently Hamming Code
algorithm on CMOS 90-nm small commercial FPGA devices and analyzed its area- performance at different
architectures. The overall design is tested and verified using Modelsim Altera. Maximum operating frequency
found with Stratix –II is in the range of 900 MHz and is in the range of 500 MHz with cyclone – II device. It is
found that increasing the number of parity bits impacts slightly upon chip area but increases the performance at
higher rate.

Keywords – Hamming Code, Single Bit and Double Bit Errors, Field Programmable Gate array (FPGA) and
VHDL.

1 Introduction

Hamming code is a technique discovered by Richard W. Hamming in 1940s that is widely used to first detect then
correct single (bit) error. It can also be used for the detection of double bit error [1]. Hamming Code used to find,
remove single bit error and also to find two bit errors is called Extended Hamming Code. Hamming Code does not
need too many calculations so it works faster.
In order to get the faster communication the implementation of such techniques on the fastest available tech-
nologies is required. These days Field Programmable Gate Arrays (FPGAs) are considered the fastest technology
among all the technologies. So the implementation of Hamming code on the FPGA will lead to the faster and
reliable communication.
In order to Program an FPGA a Hardware Description Language (HDL) is used. There are two most commonly
used Hardware Description Languages known as very high speed integrated circuit hardware description language
(VHDL) and Verilog.
A much work has reported on hardware implementation of hamming code. In the work by NutanShep and
Mrs P.H. Bhagat [1] the Hamming Code is implemented using Verilog HDL to identify and remove single bit
errors but didn‟t report anything on double bit error.
In this research work, we have worked on efficient hardware implementation of Hamming code using VHDL
programming in FPGA and implemented the extended Hamming Code that is also known as double bit error de-
tection.
Further to this implementation, we have carried out area- performance and power-analysis of implemented al-
gorithm, using small commercial FPGA devices from Altera. Area performance has been computed at different data
lengths and recorded how performance improves by varying data length at the cost of chip area.
The remainder of this paper proceeds as follows. In section II, working of hamming code is described that is
followed by extended hamming code.
2 Working of Hamming Code

Working of the Hamming code is based on either of two parities known as (a) Even Parity and (b) Odd parity. In
this paper we have implemented the Hamming Code by using even parity. In Even Parity we have utilized the
property of XOR gate i.e., when the number of one‟s at the input of XOR gate is even it will produce output„0‟ and
when the number of one‟s is odd it will produce output „1‟.In this way, number of parity bits needed for the Detec-
tion and Correction of Single bit error can be calculated as follow:
1 (1)

Where m is the number of parity bits needed, K is the number of data bits. The number of parity bits can
also be calculated as follows

(2)

In this paper, we have taken 4 bit long message which is to be transmitted. For 4 bit data the number of
parity bits we need, can be calculated by the equation either (1) or (2). By putting K=4 and r=3 in any of the equa-
tion (1), (2), we will get the equation as follow:

It means for four bit data number of parity bits needed will be three and it is known as Hamming (7, 4). These parity
bits will be added to the data at the powers of two‟s positions and the length of code will become „7‟.
(3)

In this perspective, setting of the code will be as follow

K4 K3 K2 M3 K1 M2 M1
Calculation of Parity bits M1, M2, and M3 is given below:

M1= K1XOR K3XOR K5XOR K7

M2= K2XOR K3XOR K6XOR K7
M3= K4 XOR K5 XOR K6 XOR K7
The hamming code for the detection and correction of single-bit error is discussed above whereas, in order to
detect double bit errors extended Hamming code is used. Extended hamming code working principle is almost
same as that of Hamming code for the detection and correction of single bit error. However there is one difference
that is additional parity bit is used which is termed as Overall parity bit which checks all the data bits as well as
parity bits [2] and finally sets overall code with even number of one‟s. For example – extended Hamming code
converts Hamming (7, 4) into Hamming (8, 4).
In Hamming code, detection and correction of errors is done by creating a data packet in which redundant bits are
added. For instance, four bit data as discussed previously is converted into eight bit code which contains four data
bits, three parity bits often known as “Syndrome”, and an overall parity.
Enabling for the detection and correction of errors, receiver/decoder will calculate the parity bits in the same
fashion as sender/encoder has set their values. On the receiver side following possibilities will be there:
Syndrome and overall parity both are zero; it shows communication has no any error.
Overall parity is „1‟, and syndrome is also non-zero, it shows a single bit error has occurred. Syndrome
will indicate the erroneous bit. By flipping that bit error can be corrected.
Overall parity is „0‟and Syndrome is non-zero which is the identification of two bit errors, which can only be de-
tected but not found.
Overall parity is „1‟ and Syndrome is “000” it is the indication of error in overall parity bit.

3 System Design

The system design of the Hamming code is done in VHDL and following blocks especially designed are included
Hamming Encoder, Process of extraction of message bits from encoded code by the encoder, Process for genera-
tion of overall parity at the decoder, Process for generation of parity bits at decoder side, Process for checking ei-
ther sent parity bits and received parity bits are same or not, Process for correction of single bit errors and Process
for detection of Double Bit Errors.

The flow chart of hamming encoder and decoder is shown in figure 1 and figure 2.
 START

START
8 BIT R
START

8 BIT RECEIVED CODE

CALACULATION OF
PARITY BITS EXT
CALACULATION OF MESSA
PARITY BITS EXTRACTION OF
CALCULATION OF PARITY MESSAGE,PARITY BITS
BITS AND THEIR
CALCULATION OF PARITY INSERTION AT PROPER CALC
BITS AND THEIR PAR
INSERTION AT PROPER POSITIONS CALCULATION OF
PARITTY BITS AT REC
POSITIONS
RECEIVER SIDE

8-BIT CODE C
8-BIT CODE CHECK THE
CON
CONDITIONS FOR
SINGLE AND DOUBLE SINGLE
BIT ERROR B

CORRECTION AND
STOP CORR
STOP DETECTION OF ERRORS
DETECT

STOP

Fig. 1 Flow Chart of Hamming Encoder Fig 2. Flow Chart of

Hamming Decoder
Fig. 1 Flow Chart of Hamming Encoder F

The process that generates the hamming encoder is written using VHDL code and is obtained through following
statements:
Hamming_encode: Process (Data_in)
Begin
Data_out (0) <= Data_in (0) xor Data_in (1) xor data_in (3);
Data_out(1) <= Data_in (0) xor data_in (2) xor data_in (3);
Data_out(3) <= Data_in (1) xor data_in(2) xor data_in (3);
Data_out (7) <= Data_in (0) xor Data_in (1) xor data_in (3) xor Data_in
(0) xor data_in (2) xor data_in (3) xor Data_in(1) xor data_in(2) xor data_in
(3) xor Data_in (0) xor data_in (1) xor data_in (2) xor Data_in (3);
Data_out (2)<= Data_in(0);
Data_out (4)<= Data_in(1);
Data_out (5)<= Data_in (2);
Data_out (6)<= Data_in (3);
end Process Hamming_encode;

In this code, we have initiated two ports data_in and data_out. Data_in is for desired input data and data_out is
for encoded data leaving from encoder. Output data from encoder i.e., Data_out is calculated by using X-OR gate
as explained in section 2.
As discussed above, the encoder has to convert the actual 4-bit long message into an 8-bit long code, containing
both the parity bits and the actual message. VHDL code that extracts the message from the transmitted code (i.e.,
encoded) is done by the following portion of the decoder program.

EXT_MSG: process (code_in)

begin
 msg(0) <= code_in(2);
msg(1) <= code_in(4);
msg(2) <= code_in(5);
msg(3) <= code_in(6);
end process EXT_MSG;

This is done by knowing the positions of message bits in the code and assigning those bits to a new signal i.e.
msg (3 downto 0) in this process. The code transmitted by the encoder also contains the parity bits. Which are
placed at the positions . In the following section bits at the positions are assigned to a signal i.e. rec_parity (2
downto 0). This task is accomplished by the VHDL Code given
EXT_PARITY: process (code_in)
Begin
rec_parity(0) <= code_in(0);
rec_parity(1) <= code_in(1);
rec_parity(2) <= code_in(3);
end process EXT_PARITY;

For the detection of double bit errors extended Hamming code is used. The extended Hamming code has one
additional parity bit known as overall parity bit. Overall parity at the decoder side is generated through the VHDL
code given below.
GEN_OPARITY: process (code_in)
Begin
overall_parity <= code_in (0) xor Code_in (1) xor code_in (3) xor… code_in (0)
xor code_in (2) xor code_in (3) xor… code_in (1) xor code_in(2) xor code_in (3)
xor … code_in (0) xor code_in (1) xor code_in (2) xor code_in (3);
end process GEN_OPARITY;

Overall parity bit performs bit to bit XOR operation including parity bits also. It counts the total number of one‟s
in the code. If the total number of One‟s is even then overall Parity bit is set to “0” if the number of 1‟s is odd, then
overall parity bit is set to “1”, to make even number of one‟s.

As Hamming code is based upon the parity bits. The encoder calculates the parity bits by XOR operation on the
actual message and put those bits on positions. Decoder will also calculate the parity bits by the same method
as encoder. . In this section of the system design it is explained how parity bits are calculated at the decoder side.
PARITY_GEN: process (msg)
begin
gen_parity(0) <= msg(0) xor msg(1) xor msg(3);
gen_parity(1) <= msg(0) xor msg(2) xor msg(3) ;
gen_parity(2) <= msg(1) xor msg(2) xor msg(3);
end process PARITY_GEN;

The decoder has extracted the parity bits, and it has assigned those values to the signal rec_parity. How the pari-
ty bits are calculated at the decoder side.
In this section the decoder will check either the received parity bits are same or not. As the property of xor gate
is that it produces output „0‟ at the same inputs, and produces output „1‟, at the different inputs. If the value of sig-
nal Syndrome is “000” it will indicate that communication is error free. If the value of Syndrome is non-zero, it
will indicate the error position. For example if it is “101”, it is equal to 5, means the fifth bit is erroneous. This
syndrome generation is done through VHDL code as described below
SYNDROME_GEN: process (gen_parity,rec_parity)
Begin
syndrome(0) <= gen_parity(0) xor rec_parity(0);
syndrome(1) <= gen_parity(1) xor rec_parity(1);
syndrome(2) <= gen_parity(2) xor rec_parity(2);
end process SYNDROME_GEN;

As in the previous paragraphs, it is described that syndrome will indicate the erroneous bit. By inverting that
bit error will be removed. In the following section the process for the correction of error is shown. In this portion
a case statement is used. Case statement is a sequential statement which is mostly used within the process. In this
code value of the syndrome faulty bit is inverted by using the property of x-or gate.

CORRECT_ERRORS: process (CLK) -- to correct single bit errors

begin
 if (clk'event and clk='1') then
if rst = '1' then
corrected_code <= b"000_0000"
else
case syndrome is
When "000" => corrected_code(6 downto 0) <= code_in(6 downto 0);
When "001" => corrected_code <= code_in(6 downto 0) xor "0000001"; -
- invert faulty bit
When "010" => corrected_code <= code_in(6 downto 0) xor "0000010";
When "011" => corrected_code <= code_in(6 downto 0) xor "0000100";
When "100" => corrected_code <= code_in(6 downto 0) xor "0001000";
When "101" => corrected_code <= code_in(6 downto 0) xor "0010000";
When "110" => corrected_code <= code_in(6 downto 0) xor "0100000";
When "111" => corrected_code <= code_in(6 downto 0) xor "1000000";
When others => corrected_code <= code_in(6 downto 0);
end case;
end if;
end if;
end process CORRECT_ERRORS;

The process for detection of double bit errors becomes easy if syndrome and overall parity bit conditions are
known. If both are zero; it shows communication has no any error. However, if overall parity is „1‟, and syn-
drome is also non-zero, it shows a single bit error has occurred. Syndrome will indicate the erroneous bit. By
flipping that bit error can be corrected. In the worst case, if overall parity is „0‟and syndrome is non-zero that
means two bit errors are received. It can only be detected but not corrected.
If in case, overall parity is „1‟ and Syndrome is “000” it is the indication of error in overall parity bit. In the
VHDL code for the process of detection of double bit error, Error_out is the signal which represents the number
of error.

DETECT_ERRORS: process (syndrome,overall_parity)

begin

if (syndrome = "00000" and overall_parity = '0') then

error_out <= "00"; --NO_ERROR

-- If syndrome not equal to 0 and overall Parity = 1 => SINGLE

ERROR (Correctable)
elsif (syndrome /= "000" and overall_parity = '1') then
error_out <= "01"; --SINGLE_ERROR

-- If syndrome not equal to 0 and overall Parity = 0 => DOUBLE

ERROR (Cannot be corrected)
elsif (syndrome /= "000" and overall_parity = '0') then
error_out <= "10"; --DOUBLE_ERROR

-- If syndrome = 0 and P5 = 1 => overall Parity ERROR (Cor-

rectable)
else
error_out <= "11"; --PARITY_ERROR
end if;
end process DETECT_ERRORS;
 Fig. 1. RTL View of Hamming (8,4)

4 System Simulation

The overall design was designed, synthesized and simulated in Quartus-II 9.1 and Modelsim Altera using small
commercial FPGA devices from the family of cyclone – II and Stratix – II. The simulated results snapshots taken
from Modelsim Altera are provided here.
In Figure 4, communication without error is shown. Msg_in indicate the actual message which sender wants to
transmit and it is “1101”. Encoder has encoded it as “01100110”, counting from right side first, second, fourth bits
are parity bits where as eighth bit is overall parity bit.
Syndrome signal in the simulation figure3, shows it has value “000”, and overall_parity signal has also “0”value
which is the condition for no error. And it can be seen that encoder_output and decoder_input has same value.
Means communication is without error.
.

Fig. 2. Sample of Communication without error.

In Figure 2, communication with single bit error is shown. It can be seen that encoder_output and decod-
er_input signals differ in the bit position seven, which is also encircled. Technically signal syndrome has the value
“111”, which is a non-zero value and also overall_parity signal has value „1‟ which is the condition of single bit
error. Question arises that how will hardware detect which bit has got error? The answer of this question is simple
the syndrome has the value “111”, which is the binary representation of 7,it indicates that seventh bit has got the
error, which is corrected and is shown in the figure 3, as signal corrected_code signal also actual message is re-
trieved and is shown as corrected_msg in figure 3.
 Fig. 3. . Single bit error detection and correction

In figure 4, detection of two bit errors is given. Hamming Code also has the ability to detect double bit errors. The
identification of double bit error is that if the overall parity is „0‟and the Syndrome is non-zero. In the figure5, an
example of double bit error detection is shown. Encoder_output and Decoder_input differ at the second and
sixth bits and it is also highlighted. Identification of double bit error is also verified as it can be seen that signal
overall_parity has„0‟ value and the signal Syndrome is non- zero which is the indication of double bit error.

Fig. 4. Detection of double bit errors

5 Overall Area Performance of the System

Area performance is an important parameter to check the efficiency of the overall system and it is indicated
by FMAX. Maximum Clock Frequency (Fmax) actually indicates the maximum speed of clock it can attain in
running a program without disturbing the internal clock setup time as well as clock hold time [4]. Clock setup
time is the least duration for which the data must reach prior to the clock edge active. Clock hold time is the least
period of time data should be stable after the clock edge active. The Number of Data Bits in the tables represents
the length of actual message bits only. It does not include parity bits. If we consider the parity bits it will be like
Hamming (16, 11) or (8, 4).
From the results given in Table 1 and Table 2, it is evident that overall performance reduces as we increase
number of bits i.e., original message transmitted after encoding.

Table 1. Area Performance of Cyclone-II devices

Number of
S.No Device Fmax(MHz)
data bits

1 4 EP2C5F256C 529.94
2 4 7
EP2C5Q208C 531.91
3 4 7
EP2C5AF256 511.25
4 11 A7
EP2C5F256C 277.16
5 11 7
EP2C5Q208C 331.9
6 11 7
EP2C5AF256 267.76
A7
Stratix- II devices have a two-dimensional row- and column-based architecture to implement custom logic. A se-
ries of column and row interconnects of varying length and speed provides signal interconnects between logic array
blocks (LABs), memory block structures (M512 RAM, M4K RAM, and M-RAM blocks), and digital signal pro-
cessing (DSP) blocks. Every Logic Array Block (LAB) has eight adaptive logic modules (ALMs). An ALM is the
Stratix II device family‟s basic building block of logic providing efficient implementation of user logic functions.
LABs are grouped into rows and columns across the device.
 Whereas, CycloneII has also devices have a two-dimensional row- and column-based architecture to implement
custom logic Column and row interconnects of varying speeds provide signal interconnects between logic array
blocks (LABs), embedded memory blocks, and embedded multipliers. The logic array consists of LABs, with 16
logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic
functions. LABs are grouped into rows and columns across the device. Cyclone II devices range in density from
4,608 to 68,416 LEs. Due to difference in architecture and functionality StratixII devices perform better than Cy-
clone II devices. It can also be seen in the table 1 and 2 given below.

Table 2. Area performance of Stratix-II

Number
S.No. of Device Fmax
Data (MHz)
1 Bits4 EP2S15F672 717.88
2 4 C5EP2S15F672 998.00
3 4 C3 EP2S15F672I 862.07
4 11 4 EP2S15F672 330.25
5 11 C5EP2S15F672 451.88
6 11 C3 EP2S15F672I 411.86
4

6 Applications of Hamming Code

An advantage of Hamming Code is that by using this code there is no need to transmit data string again by
transmitter at the source end, if only one bit error is there. By using Hamming Code receiver can itself get the
original transmitted data. As Hamming Code can detect Double Bit errors, it enables receiver to request for
retransmission of data when such condition occurs [5]. It has various applications for example – Mobile Com-
munication (Cellular telephones, Wireless etc.), CD, DVD, DRAM, Digital Television, High Speed Modems,
and Computer Networking

7 Conclusion

In this paper, we have focused on hardware synthesize of Hamming code detection and correction of single bit
errors with small commercial FPGA devices. It is found that, higher number of bits, impacts directly upon the per-
formance of the device counted in maximum frequency term (FMAX). Further to this, double bit error detection
i.e., extended Hamming code is designed and simulated successfully.
This will lead to a reliable and faster communication. In future, we aim to further work on extended code and de-
velop model that can remove double bit errors as well.

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