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  • STM8S103F3P6 Schematic Diagram

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    Moshkan Miraghazadeh
    473 views1 page
    This document provides a circuit diagram for a voltage regulator that steps down an input voltage of 5V to a regulated 3.3V output voltage. The key components are: 1) A voltage regulator IC (AMS1117-3.3) that regulates the output voltage. 2) Resistors (R1, R2, R3) and capacitors (C1, C2, C3) that set the input/output voltage and provide filtering. 3) Header connectors (P1-P5) that provide connections for power input/output and grounds.

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    STM8S103F3P6-Schematic-Diagram

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    This document provides a circuit diagram for a voltage regulator that steps down an input voltage of 5V to a regulated 3.3V output voltage. The key components are: 1) A voltage regulator IC (AMS1117-3.3) that regulates the output voltage. 2) Resistors (R1, R2, R3) and capacitors (C1, C2, C3) that set the input/output voltage and provide filtering. 3) Header connectors (P1-P5) that provide connections for power input/output and grounds.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    473 views1 page

    STM8S103F3P6 Schematic Diagram

    Uploaded by

    Moshkan Miraghazadeh
    This document provides a circuit diagram for a voltage regulator that steps down an input voltage of 5V to a regulated 3.3V output voltage. The key components are: 1) A voltage regulator IC (AMS1117-3.3) that regulates the output voltage. 2) Resistors (R1, R2, R3) and capacitors (C1, C2, C3) that set the input/output voltage and provide filtering. 3) Header connectors (P1-P5) that provide connections for power input/output and grounds.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    1 2 3 4

    5V VCC
    R3
    0R
    GND AMS1117-3.3
    R1 D1
    Vin Vout GND
    P1 1K
    A GND A
    5 LED
    C1 C2 C3
    4 10uF 10uF 0.1uF
    3
    2
    1
    MHDR1X5
    5V GND

    5V P2 VCC
    1 2
    3 4
    Header 2X2 U1
    GND GND PD4 1 20 PD3
    UART1_CK/TIM2_CH1/BEEP/(HS)PD4 PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
    PD5 2 19 PD2
    UART1_TX/AIN5/(HS) PD5 PD2 (HS) [AIN3] [TIM2_CH3]
    PD6 3 18 PD1
    UART1_RX/AIN6/(HS) PD6 PD1(HS)/SWIM
    C7 NRST 4 17 PC7
    B NRST PC7 (HS)/SPI_MISO [TIM1_CH2] B
    PA1 5 16 PC6
    OSCIN/PA1 PC6 (HS)/SPI_MOSI [TIM1_CH1]
    PA2 6 15 PC5
    OSCOUT/PA2 PC5 (HS)/SPI_SCK [TIM2_CH1]
    1

    22pF 7 14 PC4
    Y1 GND VSS PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]
    VCAP 8 13 PC3
    VCAP PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
    C6 8MHZ 9 12 PB4
    VCC VDD PB4 (T)/I2C_SCL [ADC_ETR]
    2

    PA3 10 11 PB5
    GND [SPI_NSS] TIM2_CH3/(HS) PA3 PB5 (T)/ I2C_SDA [TIM1_BKIN]
    22pF
    STM8S103F
    C4
    1uF

    R2 NRST
    VCC
    10K
    GND

    S1 C5
    0.1uF P4 P5
    C C
    PD4 PD3
    1 1
    PD5 PD2
    2 2
    PD6 PD1
    3 3
    NRST PC7
    4 4
    GND PA1 PC6
    5 5
    PA2 PC5
    6 6
    PA3 PC4
    7 7
    VCAP PC3
    8 8
    PB4
    VCC 9 9
    P3 PB5
    10 10
    4 VCC
    PD1 Header 10 Header 10
    3
    GND
    2 GND
    NRST
    1
    Header 4

    Title
    D D

    Size Number Revision


    A4
    Date: 2013/9/2 Sheet of
    File: D:\PCB\..\STM8S103F3P6.SchDoc Drawn By:
    1 2 3 4

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