Splice loss results: The splice loss distribution as measured by In the second experiment the 31-5 km system was
5 km system was fusion-
OTDR {X = 1-3 /zm) is shown in Fig. 1 with a mean value of
0-22 dB. This result agrees well with the mean splice loss
obtained by the cutback technique, 0-215 dB at X = 1-3 /im.
Theoretical calculations of the intrinsic losses4 due to profile
mismatch and to concentricity error show that a 015 dB
mean loss is expected. These calculations are based on the
splice loss formulas of Nemoto and Makimoto6 and use as
input data the measured values of the fibre concentricity error
and ESI parameters for the fibre pair at each splice. A com-
puter program accounts for the statistical nature of the azi-
muthal orientation of the concentricity error vectors, and the
expected splice loss is predicted for the link.
Losses due to core deformation,4 arising from the fusion
technique and the machine parameters used, have shown that
for 'good' concentricity fibre a mean splice loss of 008 dB is
expected (Fig. 2). The sum of these losses (0-23 dB) is the
expected mean splice loss for the system and this value agrees
very well with the measured mean splice loss (0-215 dB). This
result also shows that the splice loss of this system is domi-
nated by intrinsic losses due to fibre tolerances. It should be
noted that the fibre used in this trial was made from several
preform types and under diverse manufacturing conditions
and hence the spread in fibre parameters was quite large. This
indicates that once a particular fibre design is adopted im-
proved tolerances may lead to reduced splice losses.
005 OK) 0-15 , ,0-20
loss.dB
Fig. 2 Splice-loss histogram for identical fibres
20 splices (two rejected on visual appearance)
k= 1-3 ^m
Mean loss = 008 dB (18 splices)
Standard deviation = 0 0 4 d B
Concentricity error =s 0-3 /im
ESI core radius = 4-3 /im
ESI An = 3-2 x 10~ 3 = n, - n2
The mean splice loss obtained from cutback measurements
at X = 1-55 ^m is 0-25 dB. This is a larger loss than that
predicted by splice loss calculations. Experiments are currently
under way to investigate whether the extra loss may be at-
tributable to micro- or macrobending effects caused by coiling
the fibres in the joint housing.
Systems operation: After completion of the cable installation
and measurement programme two systems experiments were
carried out.
In the first experiment 650 Mbit/s and 140 Mbit/s systems
were operated at X = 1-3 ^m (10*-9 BER) over the 31-5 km of
fibre. The power budget for these systems is shown in Table 2.
Table 2
System budget: X = 1-3 /zm 140 Mbit/s 650 Mbit/s
Fibre loss (cabled) 14-8 dB 14-8 dB
Total splice loss 6-5 dB 6-5 dB
(30 splices at 0-215 dB mean)
Connector loss 0-6 dB 0-6 dB
Receiver sensitivity - 4 5 dBm - 3 4 dBm
Launch power -7dBm -8-7 dBm
Margin 161 dB 3-4 dB
Total installed system length = 31-5 km
The receiver assembly was as described by Malyon and Mc-
Donna,6 while the connector was a precision ferrule device
manufactured at BTRL.
632
spliced to a previously reported laboratory 31-6 km cabled
monomode link.3 The connector and 500 m of fibre were re-
moved and a 140 Mbit/s system (X = 1-3 urn, 10*-9 BER)
operated over 62 km of cabled monomode fibre. The link
contained 44 splices (mean splice loss = 0-203 dB) and provid-
ed 38 dB optical loss.
Conclusions: These results have shown the feasibility of the
field installation of monomode fibre systems unrepeatered
over 30 km and operating at 650 Mbit/s. We have also shown
that the target unrepeatered link length of 30 km for the UK
inland trunk network may indeed be conservative for 140
Mbit/s systems.
Acknowledgments: We should like to thank our colleagues in
the Optical Communications Technology groups at BTRL for
their advice and support—in particular, B. J. Ainslie (fibre),
D. J. Gooch (ESI measurements), S. Hornung (spectral loss
measurements), A.P. McDonna (systems studies), and J. D.
Rush (fibre). We also acknowledge staff of the Colchester Tel-
ephone Area, R. McGlashon, GEC Optical Fibres Ltd., M.
Smith, E. George and G. Waterman, TCL, and the Director of
BTRL for permission to publish this letter.
J. R. STERN 21st May 1982
D. B. PAYNE
D. j . MCCARTNEY
P. HEALEY
P. LINDSEY
D. M. RUSS
J. H. STEWART
British Telecom Research Laboratories
Martlesham Heath, Ipswich IP5 7RE, England
References
1 AINSLIE, B. J., BEALES, K. J., DAY, c. R., and RUSH, J. D.: 'The repro-
ducible fabrication of ultra low loss single mode fibre'. Proc. 7th
European Conf. on optical commun., Copenhagen, 1981, 2.5.1
2 MILUAR, c. A.: 'Application of automated ESI profiling to a 31-6
km monomode fibre system'. Proc. OFC 82, Phoenix, Arizona,
1982, ThEE3
3 PAYNE, D. B., MCCARTNEY, D. J., and HEALEY, p.: 'Fusion splicing of
a 31-6 km monomode optical fibre system', Electron. Lett., 1982,
18, pp. 82-84
4 PAYNE, D. B., and MCCARTNEY, D. J.: 'Splicing and connectors for
single mode fibres'. Proc. Int. Conf. on commun., Denver, 1981,
27.6.1
5 NEMOTO, s., and MAKIMOTO, T. : 'Analysis of splice loss in single
mode fibres using a Gaussian field approximation', Opt. & Quan-
tum Electron., 1979, 11, pp. 447-457
6 MALYON, D., and MCDONNA, A. p.: 'A 102 km monomode fibre
systems experiment at 140 Mbit/s with an injection locked 1 -52
laser transmitter', Electron. Lett., 1982, 18, pp. 445-447
0013-5194/82/140631-02S1.50/0
SIMPLE AND ACCURATE SIZE
CALCULATION OF MOS TRANSISTOR
Indexing terms: Semiconductor devices and materials, Metal-
oxide-semiconductor circuits and devices, Transistors
The letter describes an analytical solution to the problem of
finding a correct size of a MOS transistor required to charge
a load capacitance to a wanted voltage level within a given
time. The resultant formula is extremely simple, yet very ac-
curate. It could be utilised by an LSI designer, as well as in
automatic design algorithms. The expression for the channel
width over channel length ratio was derived from the
second-order drain current equations for both regions, satu-
rated as well as linear (not from simplified, first-order
approximations).
Introduction: One of the most basic tasks in MOS design is a
determination of channel width over channel length ratio
ELECTRONICS LETTERS 8th July 1982 Vol. 18 No. 14
(W/L) for a transistor charging a capacitor. This ratio is a where k = 1-38 x 10" 2 3 [J/K] = Boltzman constant,
function of great number of parameters (e.g. capacitance, T = temperature in K, q = electron charge = 1-6 x 10" 1 9 C,
charging time, threshold voltage, gate-to-source-and-back bias Nsub = concentration of a substrate doping deep in bulk, and
voltages, dopings, temperature etc.). Most of these parameters iV, = intrinsic doping (different for different L).
implicitly depend on each other. Additionally, the cur-
rent/voltage function is nonlinear. For these reasons it is vir- _J(2qeSiNsJ
tually impossible to express W/L explicitly. 1 (6)
CV
To help a MOS designer in his horendous task, software
programs (e.g. SPICE, CIRC, ASPEC etc.) were developed. ll
in which £Sl = dielectric constant of Si ( = 3-588 x 10 F/m)
These programs show a relationship between a charging time and Cox = gate oxide capacitance:
and a voltage on a capacitor being charged by a MOS transi-
stor. Unfortunately, W/L has to be known before a program
can be run. In other words, the programs are generally used to cox = — (7)
confirm the W/L choice. *ox
MOS designers, in general, follow two routes in a determi- where 71, = oxide thickness,
nation of W/L:

(a) They utilise simplified current/voltage equations (using (8)

piecewise linear approximations) and completely ignor the im- C
plicit dependence between the parameters. y/(2qeSiNsurf)
(b) Relying on their experience, they simply 'guess' (with years 72 = (9)
Cox
of experience fairly accurately) what W/L should be.
where Nsurf = concentration of a substrate doping near sur-
The disadvantages of both above approaches are obvious. The face
first gives poor estimates, resulting in many simulation runs
(costly); the second one requires a lot of experience which
comes to nothing when a MOS manufacturing process is (10)
changed.
The following considers a technique which enables a design-
er to calculate W/L, to ± 1 0 ns, with childlike ease for any in which VBO = empirical parameter used to achieve a better
process. The technique can be applied for both P-MOS as well fit between a theoretical and a real distribution of a doping in
as N-MOS enhancement transistors. the substrate.

(c) Temperature dependence: Knowing <j)F, VT and /? at temper-

Mathematical models: The second-order equations which de-
scribe a MOS transistor are as follows: ature T K, we can evaluate them at some other temperature
7" K through the following relationships:
(a) Saturated region: When
(11)
\vGS-vT\ < \vDS\ (la)
- Tcoef(T' - T) (12)
the current through a transistor is, for a medium to long
channel, where Tcoef = temperature coefficient and
"(3/2)
; -l*LtV -V)2 (\b) p = pm\-= (13)

(b) Nonsaturated region: When MOS transistor charging a capacitor C: In order to demon-
strate the idea of the W/L evaluation, let us consider charging
\vGS-vT\>\vDS\ (2a)

the current through a transistor is

/ - R — \(V
1
- V W - ^ I (2b) V
D — P T \\ yGS V
Tt VDS 2 DS

both regions having a condition for conductance:

VGS ~ VT > 0 for N-MOS (3a)

V vc_ v
VGS ~ T < 0 for P-MOS (3b)

In the above: VGS = gate-to-source voltage, VDS =

drain-to-source voltage, VT = threshold voltage, ID = (drain)
current through a transistor, /? = K' = transconductance, Fig. 1
W = effective channel width, and L = effective channel length.
Regardless of a region in which the device operates, the
following equations are used to specify VT: v(t) =vc

= VTO + WSB\+ 24>F) - (4)

where VT0 = empirical threshold voltage with a zero back

bias, •/ = as given by eqn. 10, VSB = source-to-back voltage,
and 4>F = Fermi potential. It is given by

(5)
Fig. 2

ELECTRONICS LETTERS 8th July 1982 Vol. 18 No. 14 633

a load capacitor C by a P-MOS enhancement transistor (see In the above expression, VT varies with process parameters
Figs. 1 and 2). and the temperature. (The VT dependence is described by eqns.
Let 4-12.) Hence, to try to evaluate At analytically by using eqns.
24 and 4-12 would be extremely difficult.
vitj = initial voltage on C ( = logic '0' level = 6) However, what one can see from eqn. 24 is the fact that the
expression within the brace equals, for a given charging time
v(t2) = such that a transistor is just in nonsaturation At and a capacitance C, a constant:
u(t3) = logic ' 1 ' level ( = VDD - e)
-2(VT AtW
(25)
We can determine v(t2) by using eqn. 2a:

\vds(t2)\ = \Vgs-VT\ The easiest way to evaluate K is to utilise a simulation pro-

gram (such as SPICE or ASPEC) by specifying the W/L, C,
\-lVDD-v(t2)-]\ = \-VDD-VT\ the process parameters and the temperature. The simulation
v(t2) = - VT = | VT |, since K^P-MOS) < 0 (14) will give one a voltage/time dependence (i.e. v(t)) from which it
is easy to find At, for given voltage levels. Knowing At, C and
The circuit's basic equations are: W/L one can now evaluate K from eqn. 25.
Once the value of K is known (for a given temperature and
q(t) t v(t) process parameters), W/L for the same parameters but an
I dq= I iddt = C \ dv (15) arbitrary capacitance C and an arbitrary charging time At can
be simply calculated from the relation

WC (26)
therefore

t
Conclusion: Eqns. 24 and 26 were derived not from exact
v[t) = xit,) + - \id dt (16) expressions for the current ID but from approximations.
Consequently, the charge time At, as calculated from eqn. 24
can vary somewhat from the simulation program results.
(a) Transistor in saturation: The current is given by eqn. \b. The variations were evaluated for a range of capacitances
Substituting it into eqn. 16, letting t = t2 (time when the tran- and a range of channel widths. The capacitance range was 0-2,
sistor is just leaving the saturation region) and remembering 0-4, 0-7, 1, 1-4, 2, 4, 7 and 10 (pF). The width range was 5, 7,
that VT = constant, since VSB = 0, we get 10, 20, 35 and 50 (//m). The channel length stayed constant at
5 fim. It was found that the discrepancies were less than 10 ns.
2(-VT-0)
U -t. = (17)
X{-VDD-VT)2 Word of caution: Since VT varies also with a channel length L,
it is important to remember that eqn. 26 can be used only for
where a length L for which the corresponding K was evaluated.

X =
pw (18)
P. BERNARDSON 6th May 1982
CL GTE Microcircuits
Tempe, AZ 85281, USA
(b) Transistor in nonsaturated region: The differential form of
eqn. 15 is References
1 GROVE, A. s.: 'Physics and technology of semiconductor devices'
dq = id dt = Cdv (19) (John Wiley & Sons, New York, 1967)
2 CRAWFORD, R. H.: 'MOSFET in circuit design' (McGraw-Hill, New
The voltage across the transistor can be expressed as York, 1967)
3 MERCKEL, c , BOREL, J., and CUPEA, N. z.: 'An accurate large-signal
-vds(t)=VDD-v(t) (20) MOS transistor model for use in computer aided design', IEEE
Trans., 1972, ED-19, pp. 681-390
By substituting for id and vds from eqns. 2b and 20, respec-
tively, into eqn. 19 and expressing dv, we obtain 0013-5194/82/140632-03$!.50/0
dv = - X C 0 - 5 1 ; 2 + VTv- VDD{0-5VDD + K r )] dt (21)

Solving the above nonlinear differential equation gives

t , - r, = (22)

The overall charging time At is given by a summation of eqns. OUTPUT NOISE SPECTRUM FROM
17 and 22: DEMODULATOR IN AN OPTICAL PFM
SYSTEM
-2(VT
= ( t 2 - tx) + ( t 3 - t 2 ) = t -t =
X(-VDD-VT)2
3 l

Indexing terms: Optics, Optical transmission

(23) An expression relating the input and output noise spectra of

X\YDD + 'r) a PFM demodulator used in an optical transmission system
has been derived and confirmed experimentally.
Substituting back for X, using eqn. 18, it follows that
Introduction: A pulse-frequency modulation system suitable
for the transmission of television and other wideband services
via optical fibre has been described.1 To predict the quality
with which such services can be received, it is necessary to
(24)
know the noise spectrum at the output of the PFM demodu-
lator. The receiver which precedes the demodulator consists of

634 ELECTRONICS LETTERS 8th July 1982 Vol. 18 No. 14