ASSIGNMENT-1

1. Convert the followings:

A. 0x2ED1 to Binary 2ed116 = 101110110100012
B. (−29.66)10 to Binary
C. (100111100110)2 to Hexadecimal
D. 11101110 (8-bit 2’s complement representation) to decimal
E. A computer stores the following using the IEEE754 single precision format.
What value in decimal it is representing for:
1 01111110 11000000000000000000000

2. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a

block size of 8 words. The word length is 32 bits. The size of the physical address space
is 4 GB. The number of bits for the TAG field is _____

3. Consider a 2-way set associative cache memory with 4 sets and total 8 cache blocks (0-7)
and a main memory with 128 blocks (0-127). What memory blocks will be present in the
cache after the following sequence of memory block references if LRU policy is used for
cache block replacement. Assuming that initially the cache did not have any memory
block from the current job?
0 5 3 9 7 0 16 55

(A) 0 3 5 7 16 55 (B) 0 3 5 7 9 16 55
(C) 0 5 7 9 16 55 (D) 3 5 7 9 16 55

4. A digital computer has a memory unit with 24 bits per word. The instruction set consists
of 199 different operations. All instructions have an operation code part (opcode) and an
address part (allowing for only one address). Each instruction is stored in one word of
memory.
A. How many bits are needed for the opcode?
B. How many bits are left for the address part of the instruction?
C. What is the maximum allowable size for memory?
D. What is the largest signed binary number that can be accommodated in one
word of memory?
5. Suppose you have the instruction “Add 900”. Given the memory as follows, the contents
of AC and the base register are 200 and 100 respectively.
Memory address value
800 900
900 1000
1000 500
1100 600
 1200 800
1300 250
What would be loaded into the AC, if the addressing mode for the operand is:
A. Immediate
B. Direct
C. Indirect
D. Indexed

6. Write code to implement the expression: F = (A-B)*(C*D+E) on 0-address, 1-address

and 2-address machines. In accordance with programming language practice, computing
the expression should not change the values of its operands.

7. In a computer instruction format, the instruction length is 10 bits and the size of an
address field is 3 bits. The system architect has already designed (15) FIFTEEN 2-
address instructions and (7) SEVEN 1-address instructions. How many 0-address
instruction still possible to accommodate for the instruction set architecture?

8. How are data, address and control buses involved in data transfer to and from memory?
Consider a computer system with 16 registers of 32 bit each and RAM of 1GB. Calculate
the size of data bus and address bus required for the same.

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