G.L.

Peters
G.A. Covic
J .T. Boys

Indexing terms: Inverters, Three-phase load, Vector switching, Induction motor

ment of integrated IGBT power modules and enhanced

Abstract: A new space vector switching strategy
for four-switch inverters driving three-phase
induction motors is described. The technique
allows a full range of operation, compensating for
both DC link ripple and imbalance to eliminate
torque and speed pulsations under all operating
conditions, while allowing the largest possible
voltages to be produced. The paper presents
theoretical expectations and compares these with
measured values obtained from an inverter
operating off a single phase AC supply
corresponding to worst case conditions.
List of symbols
peripheral microcontrollers. These have led to motor
drives which exhibit flexible control and high perform-
ance at reduced cost. The structure of the conventional
voltage-sourced AC motor drive remains unchanged: a
diode bridge rectifier feeding into an LC filter to give a
stiff DC voltage link, which is then connected to a six-
switch bridge inverter. Recent pressure in Europe to
force a tightening of harmonic and RFI regulations on
power converters is prompting manufacturers to mod-
ify the utility side of the converter, in some cases
replacing the diode bridge with active switches to meet
expected regulations [I]. In low power converters this is
particularly expensive, but results in unity power factor
and four-quadrant control capability which is particu-
larly beneficial in servo and torque controlled applica-
tions.

V , , , ... = voltage between points indicated by sub- H

scripts as labelled in Fig. 1
Edc,... = D C link voltage level
Y = DC link imbalance factor
LLO, ... state descriptor for inverter switches a
U,, ... = output state voltage space vector
t,, ... = time spent in corresponding switching state ' L
H
6 = acute angle between adjacent switching I

state vectors
ua,, ... = orthogonal component of output state volt-
age space vector
U, = average output voltage vector for modula-
tion period b I I
L
T = modulation period
Fig. 1 Reduced switch count four-quadrant converter topologies
0 = angle of average output voltage vector a Single- to three-phase bidirectional converter utilising six switches
b Three- to three-phase bidirectional converter utilising eight switches
V l p .U = per unit base for voltage
A = modulation depth in per unit
The desire of manufacturers to meet regulatory
1 Introduction changes as inexpensively as possible has stirred an
interest in new converter topologies. Of most interest to
Significant advances in power electronics have been AC drives manufacturers are those with reduced switch
made during the past decade, including the develop- count operating off either single or three-phase sup-
0IEE, 1998 plies, under both fixed and variable speed operation
IEE Proceedings online no. 19982022
[2-10]. Two such converters with regenerative utility
interfaces are shown in Fig. 1. The output stage is iden-
Paper first received 28th July 1997 and in revised form 19th February
1998 tical in either case, comprising only four switches which
G.L. Peters is with PDL Electronics Ltd., PO Box 741, Napier, New Zea- are connected to two phases of the motor. The third
land phase of the motor is connected to the midpoint of the
G.A. Covic and J.T. Boys are with the Department of Electrical and Elec- DC link. There are a number of application issues
tronic Engineering, University of Auckland, Private Bag 92019, New Zea- regarding the performance of such topologies, of most
land
importance is the ability to maintain balanced output
326 IEE Puoc.-Electr. Power Appl., Vol. 145. No. 4, July 1998
waveforms in the presdnce of nonideal DC link condi-
tions.
This paper considers the causes, effects and remedies
pertaining to the output distortion resulting from volt-
age imbalance in the split DC link. The theoretical
development herein de,scribes the major factors leading
to voltage imbalance and the effect it has on the output
voltages produced by the four-switch inverter. Practical
implementation issues and results showing typical link
imbalance conditions are also given. The effectiveness
of the dynamic imba1,ance compensation technique is
illustrated with measurements taken from a four-switch
inverter driving a three-phase induction motor load.
2 Asymmetric space vector modulation for four-
switch inverters
2.1 Four-switch inverter and DC link voltage
imbalance
The direct coupling of input and output stages in
switch minimised topologies, as shown in Fig. 1, causes
the generated three-phase waveforms to be particularly
sensitive to ripple in the DC link. Imbalance between
the two halves of the split link is of greatest concern as
it directly affects the ability to generate a balanced out-
put. There are two sources of imbalance: the first is
caused by rectification of the supply, the second occurs
at low output frequencies where unequal loading of the
split link occurs for extended periods. The reduction of
the resulting output distortion can be handled in sev-
eral ways. The first is i,o increase the amount of capac-
itance in the DC link !so as to minimise the amount of
imbalance generated. This would add considerable cost
and require careful consideration of initial charging
requirements, both of which would most likely increase
the dimensions of the resulting converter. Another
more cost effective method is to use real-time compen-
sation techniques when generating the inverter switch-
ing control signals as outlined in [111.
To aid the development of a ripple and offset imbal-
ance compensation technique the following definition
(eqn. I) will be used to describe the split DC link volt-
age levels in the four-switch inverter, where Edc is the
total link voltage:
Ed+,= (1- ?)Edc and EG = (-?)Ed, (1)
The imbalance factor y is used to describe the relative
distribution of voltage across the split DC link. Under
ideal conditions y has ,% value of 0.5.
The four-switch inverter topology of Fig. 1 can only
produce four differeni, output voltage vectors (states)
that do not short-circuit or open-circuit the DC voltage
link. These states are LLO, HLO, HHO and LHO as
shown in Fig. 2. The state descriptor describes the state
of the inverter legs connected to motor phases, U, V
and W, respectively. An ‘H’ denotes that the line is
connected to the posiiive voltage rail, similarly an ‘L’
denotes connection to the negative voltage rail. Phase
W is connected to the midpoint of the DC link so for
completeness it is included as a ‘0’.
Two of the invertelr switching states (LLO, HHO)
cause unequal loading of the split link capacitors. This
causes one half of the link to discharge at a faster rate
than the other, resulting in the generation of a voltage
imbalance. At low output frequencies considerable
periods of time can be spent predominantly in one of
the unbalanced states, leading to an imbalance that has
a noticeable effect on waveform quality.
IEE Proc -Electr Power Appl Vol 145, No 4, July 1998
The standard approach to generating pulse width
modulation (PWM) waveforms from the four-switch
inverter has been to assume that the link is balanced
and of constant voltage. This assumption ceases to
remain valid as the output frequency is reduced to low
levels. An analytical treatment of the interaction
between two reduced switch count converters sharing
the same DC link (Fig. lb) was first presented in [lo].
A link voltage compensation scheme based on sine-tri-
angle PWM was briefly mentioned, however no results
showing its effectiveness were presented.
u v w
H L O
0
H fv
E,f, I
uvw
L H O
- r L
Fig.2 Inverter switching states and their respective DC link loading pat-
terns
Only recently have the concepts of space vector mod-
ulation been applied to four-switch inverters operating
from a split DC voltage link [7-91. The four-switch
inverter can only output four voltage vector compo-
nents, all of which are active states. However, by fol-
lowing the fundamental concepts of space vector
modulation, a generation strategy can be developed
that produces three-phase output waveforms of varia-
ble voltage and variable frequency.
2.2 Definition of inverter state vectors
The inverter state vectors are derived by transforming
the three output voltage quantities (Vue, Vyo, Vwo)
resulting from each of the four-switching states into
orthogonal components in the space vector plane.
A matrix representing the output of the inverter as a
function of switch states is shown in eqn. 2, where Edc
is the overall DC link voltage:
L H H L
[L L H H I + 1
10 0 0 01
(1- ?)Ed,
-?Ed,
(1- ?)Ed,
(1- ?)Ed,
-?Ed,
(1 - :)Ed,,
1
0 0
(2)
The inverter output state voltage matrix (eqn. 2) can be
transformed into space vector form using the following
321

0 0
l o
This results in the output voltage space vectors being
defined as
(44
Ud = Edc I)%( )(44
[ (7-1 - y
+j
Voltage imbalance in the DC link causes the space vec-
tor origin to shift along the Ua/U, axis, with U, and U,
no longer being equal in magnitude, as described in
eqn. 4. The resulting vector relationships illustrating
the effects of link imbalance can be clearly seen in
Fig. 3. The angle 6 defines the acute angle between
adjacent inverter state vectors.
'b a
'
a b
Fig.3 Space vector diagram of switching state space vectors, with maxi-
mum permissible circular trajectory shown
a Balanced DC link voltages ( y = 0.5)
b Unbalanced DC link voltages ( y < 0.5)
For a fixed value of total link voltage Ed,, the verti-
ces of the four-switch inverter rhombus remain fixed
and only the origin shifts with imbalance. Fig. 36
shows how the maximum circular voltage locus that the
rotating space vector can prescribe within the rhombus
has been reduced by the imbalance. In a similar man-
ner to the six-switch inverter, higher output voltages
can be generated by forcing the rotating space vector to
follow a hexagonal locus [12]; the main difference here
being that the vertices of the maximum hexagonal locus
must be constrained to be less than or equal to the
smallest switching state vector.
2.3 Definition of switching times
The four-switch inverter cannot produce any physical
null switching states like those inherent in the six-
switch inverter, so in order to regulate the magnitude
of U, a new mechanism is needed. Here the excess
modulation time is shared between two opposing vec-
tors (U,, U,) or (Ub, U,). The choice of which vector
pair to use for the production of these effective null
states represents the required degree of freedom, with-
out a significant increase in switching frequency. Covic
et al. [7] presented an efficient asymmetric space vector
328
modulation (ASVM) generation technique that is also
applicable here providing the DC link imbalance can
be taken into account. The technique gave the smallest
torque ripple with the least number of switching
changes over the modulation period.
Similarly, Blaabjerg et al. [9] investigated torque rip-
ple minimisation by selecting some of the switching
states more than once in a modulation period. This
minimisation, however, was at the expense of increased
computational complexity and higher switching rates.
Therefore, while motor harmonic losses may be
reduced slightly, inverter switching losses will increase.
In small compact inverter drives, where such switch-
minimised topologies are likely to be used, this may
affect mechanical sizing due to thermal management
requirements.
There are numerous combinations of vectors and
times that can be used to define U,, but the method
shown here represents one that has minimal computa-
tional requirements, and each output only changes
state once per modulation period. Eqns. 5 and 6 are the
volt-second integrals for the orthogonal components of
U,, taking into account the displacement of the switch-
ing state vectors caused by DC link voltage imbalance
as shown in Fig. 3:
( U , sin 8)T = (Ubsin 6 ) t b (5)
( U , COS 8)T U,t, - Uct, - ( U , COS 6 ) t b
1
(6)
Expressing the switching state vector magnitudes in
terms of DC link voltages gives
(9)
2
U , = 5(1 - ?)Ed, (10)
If one per unit voltage is defined as the magnitude of
the maximum circular trajectory vector under balanced
conditions ( y = 0.5) then
Ed c
v1p.u. = -
2&
This corresponds to the maximum sinusoidal RMS line
voltage that can be applied to the motor (neglecting
on-state voltage drop). If the rotating space vector fol-
lows the hexagonal locus, then the resulting trapezoidal
line voltages have a fundamental component that is
5.3% larger than the sinusoidal case. Taking A as the
per unit modulation depth, and T the modulation
period, then eqns. 12-14 for the space vector switching
times are obtained using eqns. 5-11 for 8 in the range
0-180":
IEE ProcElectr. Power AppL, Vol. 145, No. 4, July 1998
Similar expressions can be derived for the period 180-
360" where the Ub veci.or becomes redundant ( t b = 0),
and Ud becomes active. Eqns. 12-14 are modified by
replacing t b with td to reflect these changes.
2.4 Waveform generation using ASVM
An instantaneous voltage vector (U,) can be produced
along a desired circular trajectory, using only three of
the four possible switching states U,, Ub, U, and Ud, as
illustrated in Figs. 4a and b. In practice, the voltage U,
shown is simply the avcrage value output over a PWM
switching period T resulting from appropriately allocat-
ing portions of the time T to each of the realisable
three states [7, 81. Achieving this output voltage is not
trivial, however, because the relative magnitudes of the
switching states U, ... lJd change with imbalance in the
DC link, as illustrated in Fig. 4c. Thus, if the switching
times spent at each state (t, ... t d ) are calculated ignor-
ing this effect, the actuid voltage vector produced (over
period T, will have errors in both magnitude and phase
(Fig. 4 4 . As a consequence, the desired voltage trajec-
tory will not be output and there will be noticeable dis-
tortion in the output current. The switching method
developed in the previous Section ensures that these
switching times are dynamically adjusted for each
period T to compensate for the DC link imbalance
(Fig. 4e), allowing any desirable trajectory (circular or
hexagonal) to be output providing this voltage is within
the available limits.
__.--.__
,. .~~.-._
d motors whose rated voltage is much higher than that
-__..._
. capable of being output, as could be the case if operat-
Fig.4 Production of a rotat8ngspace vector U, using only three switch-
ine state vectors
* &notes a reference quantity
a Switching vectors for y = 0.5 (halanced link)
b SVM using link conditions shown in Fig. 4a (A* = 0.3, 8* = 30 deg)
c Switching vectors for y = 0.3 (unbalanced link)
d SVM using link conditions shown in Fig. 4c with no attempt to compensate
for imbalance (A* = 0.3, 8* = 3Cl deg)
e SVM using link conditions shown in Fig. 4c with dynamic imbalance com-
pensation (A* = 0.3, O* = 30 de€)
The generation of circular space vector trajectories
that comes from effective compensation is only possible
if the modulation depth is constrained to be less than
the length of the shortest switching state vector
(Fig. 5a). It should be noted that Fig. 5 shows effec-
IEE Proc.-Electr. Power Appl., Vol. 145, No. 4 , July 1998
tively a snapshot in time and the imbalance will be
oscillating along the UalU, axis, causing the constraint
to vary with time.
Fig.5 Maximum space vector locifor a given level of imbalance
a Circular locus for sinusoidal output voltage ( y < 0.5)
b Hexagonal locus for trapezoidal output generation ( y < 0.5)
The maximum modulation depth allowable for a cir-
cular trajectory is defined as
V y < 0.5
Amaz czrc - -{'?
2 ( l - y) b'y > 0.5
(15)
V y = 0.5
The waveform generation strategy thus far has concen-
trated on the generation of sinusoidal output wave-
forms. The space vector switching times, as calculated
by eqns. 12-14, are valid for modulation depths that
are constrained within the maximum rhombic locus
prescribed by the switching state vectors. The genera-
tion of trapezoidal line voltages (hexagonal locus) is
easily done by dynamically scaling the circular modula-
tion depth as a function of 8. This allows the rotating
space vector to extend into the vertex region of the hex-
agonal locus where the maximum modulation depth is
defined by eqn. 16. The maximum hexagonal modula-
tion depth will give a hexagonal vertex length of
Vy < 0.5
A m a z hex at vertices = 2/fiVy = 0.5
{&
)/:I; Vy > 0.5
(16)
The maximum hexagonal locus constraint is illustrated
in Fig. 56.
These constraints usually have little impact in stand-
ard motor drive controllers since at low frequency,
where the imbalance is greatest, the modulation depth
is quite low. Consideration of this constraint may be
required when applying the four-switch inverter to
ing from a reduced voltage input or battery supply
where eqns. 15 and 16 should be taken into account.
3 Experimental results
3. I Practical implementation
Most commercial AC drives measure the DC link volt-
age level for control and protection purposes. Provid-
ing an additional voltage feedback signal from the
midpoint of the split D C link allows the degree of link
voltage imbalance (y) to be determined. Implementa-
tion of the compensation technique within the wave-
form generation interrupt routine can be done with a
few additional lines of software. A single 80C196KB
microcontroller running at 12MHz was used to control
the four-switch inverter to prove that such a low-cost
16 bit processor was more than adequate to provide
compensated waveform generation, I/O handling, sys-
tem protection and host communications. A 1.5kHz
switching frequency was used in the generation of the
329
following results, this could easily have been increased
to improve output current ripple. The low modulation
depth usually associated with low output frequencies
may require the effects of dead time to be considered as
the switching frequency is increased.
An initial study of the effects of link imbalance on
waveform quality was carried out using an evaluation
circuit. This circuit utilised the gating waveforms gener-
ated by the 80C196, logic gates to mimic the inverter
action, and two separately regulated adjustable voltage
sources to emulate a D C link imbalance. Fig. 6a illus-
trates the origin shift in the space vector plane for a
fixed D C imbalance if waveforms are generated assum-
ing balanced conditions. Fig. 66 also shows that it is
possible to successfully remove the output offset and
return the circular space vector trajectory to the origin,
indicative of a balanced system, by accounting for the
changed magnitude and phase relationships between
the switching state vectors when calculating switching
times.
for a 50Hz supply. In consequence, the voltages on the
two halves form a total level ripple at a frequency of
100Hz, and an imbalance ripple of 50Hz. Secondly, the
operation of the four-switch inverter loads the D C link
in a manner which causes imbalance ripple at the
output frequency; this effect is much worse at lower
frequencies and lower modulation depths. The combi-
nation of these two imbalance generating phenomena
results in complex harmonic and imbalanced voltages
in the D C link.
Figs. 7 and 8 show the AC measured link voltages
for a four-switch inverter operating from a total DC
link voltage of 500V. Each of these results shows a
snapshot in time lasting 400ms. With reference to
Fig. 1; the total link voltage is measured as (VHo+
V,,) and the imbalance as (VHo- V,,). Figs. 7a and b
show these link voltages ( VHo+ VoL)and ( VHo- VoL),
respectively, at an output frequency of 10Hz. The
imbalance ripple resulting from unequal loading of the
split D C link by the four-switch inverter is clearly
shown in Fig. 7b, where the dominant frequency com-
ponent is the fundamental output frequency (1OHz).
15, , I I I
10
> 5
a i 0
-B
a
-5
-10
-15f 1
>
-20
a
' '
time (25ms/div)
I

",Iu, b time (25ms/div)

a Fig.7 Ripple components in the split DC link foy IOHz output
a Total link level AC ripple
b Link imbalance AC ripple

I"

> 5
g o
m
r -5
9 -10
, /
time (25msidiv)
40: , , ,

b b time (25msidiv)
Fig.6 Voltage vector trajectory for aJixed D C offset imbalance Fig.8 Ripple components in the split D C link for 17.5Hz output
a Assuming fixed y = 0.5 a Total link level AC ripple
b Accounting for variable y b Link imbalance AC ripple

3.2 DC link conditions
In general, a single phase uncontrolled diode rectifier
causes the worst case imbalance conditions to occur in
the D C link. For this reason the remainder of the
paper will consider the dynamic imbalance compensa-
tion of three-phase output waveforms from a four-
switch inverter supplied by a voltage-doubling single-
phase diode rectifier.
As discussed in Section 2.1, the DC link is affected
by two load dependent phenomena. First, with a volt-
age-doubling rectifier the different halves of the split
link are charged at different times, some lOms apart
330
Figs. Sa and b illustrate the reducing imbalance con-
tribution of the four-switch inverter as the output fre-
quency is increased. As a consequence of this, the 50Hz
imbalance component caused by input rectification
becomes more pronounced (Fig. 86).
3.3 Distortion caused by uncompensated
link imbalance
If PWM output voltages are produced without consid-
ering the nonideal D C link conditions described in Sec-
tion 3.2 then unbalanced stator voltages will result at
low output frequencies. Relatively small voltage asym-
IEE Pvoc.-Electi. Power Appl., Vol. 145, No. 4,July 1998
metries can cause large stator current variations [13].
There are two torque Icomponents that result from such
asymmetry: an average component produced by the
summation of positive and negative sequence compo-
nents, and a pulsating component at twice output fre-
quency resulting from the interaction between the
stator currents and stator flux linkages [14]. This is in
addition to the pulsating torque components produced
due to the PWM switching pattern, which can be
reduced by increasing the switching frequency of the
inverter,
At an output frequency of lOHz the stator flux
space-vector trajectory is elliptical due to the close rela-
tionship between the imbalance ripple frequency and
resonance. The increased stator and rotor losses result-
ing from operating motors with unbalanced voltages
may also necessitate derating of the motor [15].
3.4 Effectiveness of compensation
Using the same experimental technique as used to
obtain the results shown in Section 3.3, and enabling
the compensation described in Section 2.3, output
waveform distortions due to voltage imbalance in the
DC link are eliminated. This is clearly shown in
Fig. IOU where the flux trajectory is circular, and
Fig. 10b where balanced stator currents are produced.
1.c

output fundamental. IJsing a ‘vector visualiser’, the sta-

tor flux trajectory is shown in Fig. 9a. The current
asymmetry resulting fiom the generation of such a tra- 0.:
jectory is clearly shown in Fig. 9b.
1.o 5
g
= o
2.

0.5
-0.5
g
3
x‘ 0
=
> -1 .c
-1 .o -0.5 0 0.5 1 .o
X flux, Wb
-0.5

-1.o
-1.o -0.5 0 0.5 1.o
X flux, Wb
a

-2
0.2 0.3 0.4 0.5 0.6 0.7
time, s
b
Fig. 10 Motor supply with compensationfor DC link voltage imbalance
clearly showing restoration of balanced inverter output supply
a Stator flux space-vector trajectory (10Hz)
h Stator current (10Hz)

-2
0.2 0.3 0.4 0.5 0.6
time, s
b
Fig.9 Motor supply without compensation for DC link voltage imbal-
ance
a Stator flux space-vector trajeztory (lOHz), ideal circular pattern also shown
b Stator current (10Ha)
It is important to note that for a given level of volt-
age imbalance in the IIC link the relative output distor-
tion caused increases dramatically as the modulation
depth is lowered. This characteristic has limited the
adoption of the four-switch topology as a low-cost gen-
eral purpose inverter. The torque ripple effects resulting
from such distortion limit its use in low speed applica-
tions, especially in fadduct systems where the low
frequency torque ripple could cause annoying duct
IEE Proc -Electr Power Appl, Vol 145, No 4, July 1998
1
0.7 The compensation technique described in this paper
allows high quality balanced three phase voltages to be
generated down to near DC output frequency. In a
bidirectional single to three phase converter (Fig. la)
the lower limit in frequency is governed by the level of
input current distortion allowed as the switching
rectifier looses its ability to force input currents
correctly [8, lo].
4 Conclusions
Reducing the number of power switching devices in a
converter can lead to an overall cost reduction of the
unit. To do this, however, special topologies such as
the one described in this paper are required. It was
shown that the generation of a low frequency output
331
can cause considerable voltage imbalance in the DC
link. Severe output distortion will occur if this imbal-
ance is not considered when calculating the inverter
switching times.
Asymmetric space vector modulation, with link volt-
age feedback, is capable of producing a high quality
balanced three-phase supply suitable for driving cage
induction motors. The computational efficiency of the
waveform generation makes it simple to implement
such a DC link imbalance and ripple rejection scheme
while allowing maximum possible output voltages. The
real time nature of this technique provides near instan-
taneous control of frequency and amplitude, allowing
high performance control strategies to be physically
realised.
With balanced output generation now possible down
to near DC frequencies, the four-switch inverter struc-
ture is an attractive topology for low cost, small power
AC motor drives. It is particularly well suited for single
phase input applications requiring low distortion utility
interfaces and regenerative capability. This paper has
shown that it is possible to avoid adding excessive
amounts of costly DC link capacitance to limit the
voltage distortion generated at low output frequencies.
Active compensation within the modulation strategy
has proven effective in reducing the output sensitivity
of the four-switch inverter to nonideal D C link condi-
tions.
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IEE Pvoc.-Electr. Power Appl., Vol. 145, No, 4,July 1998