5 4 3 2 1

+3VPCU
L16 BLM15AG121SN1D(120,500MA)_4 +A3VPCU +3VPCU_ECPLL L11 BLM15AG121SN1D(120,500MA)_4
EC(KBC) +3VPCU_EC
S5_ON R602 10K_4
C411 C653 (For PLL Power)
0.1u/16V_4
0.1u/16V_4 +3V_S5
ECAGND
SIO_EXT_SMI# R610 *10K_4
[30] D/C# SB_ACDC [30]
R591 2.2_6 12 mils TP59 SIO_EXT_SCI# R607 *10K_4
1 2 +3VPCU_EC
+3VPCU BT_EN [21]
C652 C654 C371 C396 C660 C424 TP64 +3V
TP65
0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 0.1u/16V_4 Layout put in device side SIO_A20GATE R592 *10K_4
KBRST# R603 10K_4
USBON# [25]
R658 33_4 SERIRQ R605 *10K_4
TPD_EN [27]
R239 2.2_6
USB_CHG_MODE [25]
+3V 1 2 +3V_EC
D USB_CHG_EN [25] D
C674 SUSON R593 100K_4
LPC_CLKRUN# [6,23]
C657 R613 *8.2K 180P/50V_4 MAINON R253 100K_4
+3V
VRON R249 100K_4
0.1u/16V_4 PLTRST# R608 100K_4

114
121
106

127
PCH_RSMRST# R584 *10K_4 ITE suggest PCH_RSMRST#

11
26
50
92

74

84
83
82

19
20

99
98
97
96
93
3
U35 CPU_ID R615 *SP@0_4 PD
CPU_ID:CZ Internal PU, CZL External
10 110 PD

GPH7
VCC

AVCC
VSTBY_FSPI

EGCLK/WUI27/GPE3(Dn)
EGCS#/WUI26/GPE2(Dn)
EGAD/WUI25/GPE1(Dn)

L80HLAT/BAO/WUI24/GPE0(Dn)
L80LLAT/WUI7/GPE7(Up)

CLKRUN#/WUI16/GPH0/ID0(Dn)
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

VSTBY

WUI42/GPH6/ID6(Dn)
WUI41/GPH5/ID5(Dn)
WUI40/GPH4/ID4(Dn)
WUI19/GPH3/ID3(Dn)
[6,21,23] LPC_LAD0 LAD0/GPM0(X) SMCLK0/GPB3(X) MBCLK [30]
9 111
[6,21,23] LPC_LAD1 8 LAD1/GPM1(X) SMDAT0/GPB4(X) 115 MBDATA [30]
[6,21,23] LPC_LAD2 LAD2/GPM2(X) SMCLK1/GPC1(X) 2ND_MBCLK [4,12]
7 VSTBY 116
[6,21,23] LPC_LAD3 LAD3/GPM3(X) SMDAT1/GPC2(X) 2ND_MBDATA [4,12]
22 VCC 117 TP49
+3VPCU [5,21,23] PLTRST# 13 LPCRST#/WUI4/GPD2(Up) VSTBY PECI/SMCLK2/WUI22/GPF6(Up) 118 R660 33_4

SM BUS
[6] CLK_PCI_775 LPCCLK/GPM4(X) VCC SMDAT2/WUI23/GPF7(Up) LID591# [17]
6 C682 180P/50V_4
CLK_PCI_775
[6,21,23] LPC_LFRAME#
17
LFRAME#/GPM5(X) VSTBY
PS2CLK0/TMB0/CEC/GPF0(Up)
85
86
IOAC_RST# [20,21]
SM BUS PU(KBC)
PROCHOT_EC
LPCPD#/WUI6/GPE6(Dn) PS2DAT0/TMB1/GPF1(Up) EC_FPBACK# [17]
2

89
126 PS2CLK2/WUI20/GPF4(Up) 90 TPCLK [27]
D40
[5] SIO_A20GATE GA20/GPB5(X) VSTBY PS2DAT2/WUI21/GPF5(Up) TPDATA [27]
R611 R606 5 +3VPCU

PS/2
RB500V-40 [6,23] SERIRQ SERIRQ/GPM6(X)
100K_4 15 VCC
[5] SIO_EXT_SMI# ECSMI#/GPD4(Up) VSTBY VSTBY VSTBY
23 Layout put in device side
ECSCI#/GPD3(Up) LPC VSTBY
*22_4 MBCLK R597 4.7K_4
[5] SIO_EXT_SCI#
1

WRST# 14 GPIO MBDATA R596 4.7K_4

R604 *short_4 4 WRST# VSTBY
[5] KBRST# KBRST#/GPB6(X) VSTBY
16
[21] IOAC_WLAN_WAKE# PWUREQ#/BBO/SMCLK2ALT/GPC7(Up)/SMCLK2ALT VSTBY Change EC SMBus PU voltage from
C656 C655
*10p/50V_4 1u/6.3V_4 24 +3V_S5 +3V_GFX to +3V_S5 due to it also
PWM0/GPA0(Up) PWRLED# [26] connect to CPU(SIC/SID) and GPU.
25

[28]
[5]
KB_BL_LED
DNBSWON#
113
123 CRX0/GPC0(Dn)
CTX0/TMA0/GPB2(Dn) CIR
IT8987E/BX PWM1/GPA1(Up)
PWM2/GPA2(Up)
PWM3/GPA3(Up)
PWM4/GPA4(Up)
28
29
30
BATLED1# [26]
SUSLED# [26]
BATLED0# [26]
MAINON [33,36]
2ND_MBCLK
2ND_MBDATA
R595
R594
4.7K_4
4.7K_4
EC need read CPU temperature even
in UMA mode or GPU off mode
VSTBY 31
PWM5/GPA5(Up) USB_CTL1 [25]

PWM
TP60 80
119 DAC4/DCD0#/GPJ4(X) 47
[5] SUSB# DSR0#/GPG6(X) VSTBY TACH0A/GPD6(Dn) FANSIG [28] CORE_PWM_PROCHOT# [4,30,34,35]
Layout put in device side [5] PWROK_EC
33 48
GINT/CTS0#/GPD5(Up) TACH1A/TMA1/GPD7(Dn)

3
R612 0_4 88 TP68
[4,17] APU_DISP_BLEN 81 PS2DAT1/RTS0#/GPF3(Up) 120
R322 33_4 Q48
[17] TOUCHPANEL_ON DAC5/RIG0#/GPJ5(X) TMRI0/WUI2/GPC4(Dn) SUSON [31,33]
C 87 124 C
[20] IOAC_LAN_WAKE# 109 PS2CLK1/DTR0#/GPF2(Up) TMRI1/WUI3/GPC6(Dn) 2
TP48 TP52 PROCHOT_EC
C678 108 TXD/SOUT0/GPB1(Up)
[22] AMP_MUTE# RXD/SIN0/GPB0(Up)
180P/50V_4
71 VSTBY 107 R609 2N7002K
[24] ODD_POWER ADC5/DCD1#/WUI29/GPI5(X) PWRSW/GPE4(Up) NBSWON# [28]
72 UART port 18
[30] ACIN SUSC# [5]

1
73 ADC6/DSR1#/WUI30/GPI6(X) RI1#/WUI0/GPD0(Up) 21 HWPG 100K_4
[30] TEMP_MBAT ADC7/CTS1#/WUI31/GPI7(X) RI2#/WUI1/GPD1(Up)
35 WAKE UP
[21] IOAC_WLANPWR# RTS1#/WUI5/GPE5(Dn)
Layout put in device side 34
[22] PCBEEP_EC 122 PWM7/RIG1#/GPA7(Up) 112
R625 33_4 TP53
[24] EC_ODD_EJ DTR1#/SBUSY/GPG1/ID7(Dn) RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7(Dn) PCH_RSMRST# [5]
95 Layout put in device side
[30] AC_PROTECT 94 CTX1/WUI18/SOUT1/GPH2/SMDAT3/ID2(Dn)
C676 180P/50V_4 R635 33_4
CRX1/WUI17/SIN1/SMCLK3/GPH1/ID1(Dn) RF_EN [21]
R598 CZL@0_4 SPI_SCK_UR_R 105 C675 180P/50V_4 +3VPCU
[6] SPI_SCK
[6] SPI_CS
R601 CZL@0_4 SPI_CS0#_UR 101
102
FSCK/GPG7
FSCE#/GPG3
SPI NOR FLASH(128KB) (KBC)
[6] SPI_SDI
R213 CZL@0_4 SPI_SDI_UR
FMOSI/GPG4 EXTERNAL SERIAL FLASH ICMNT [30] +3VPCU
R214 CZL@0_4 SPI_SDO_UR 103 66
[6] SPI_SDO FMISO/GPG5 ADC0/GPI0(X)
EC_SPI_SCK R587 CZ@0_4 67 C428 10u/6.3V_6 ECAGND
ADC1/GPI1(X) U33
EC_SPI_CS0# R590 CZ@0_4
[28] MY16
56
KSO16/SMOSI/GPC3(Dn) ADC2/GPI2(X)
68
DGPU_AC_DC# [12] 25mA R566
EC_SPI_SDI R589 CZ@0_4 57 69 8 5 EC_SPI_SDI CZ@10K_4
[28] MY17 KSO17/SMISO/GPC5(Dn) ADC3/GPI3(X) VRON [5,34] +3VPCU VCC SPI_SI
EC_SPI_SDO R588 CZ@0_4 CPU_ID 32 70 2 EC_SPI_SDO
PWM6/SSCK/GPA6(Up) ADC4/WUI28/GPI4(X) IOAC_LANPWR# [20] SPI_SO 1 EC_SPI_CS0#
100 3 CS# 6
[31,32,36] S5_ON SSCE0#/GPG2(X) A/DAVCC
D/A R565 EC_SPI_WP#
WP# SPI_SCK
EC_SPI_SCK
125 SPI ENABLE CZ@10K_4
[27] PTP_PWR_EN# SSCE1#/GPG0(X) 76 TP63
36 TACH2/GPJ0(X) 77 TP62 R581 EC_SPI_HOLD# 7 4 C649
[28] MY0 37 KSO0/PD0 GPJ1(X) 78 SPI_HOLD GND
TP61 CZ@10K_4 *CZ@10P/50V_4
[28] MY1 KSO1/PD1 DAC2/TACH0B/GPJ2(X)
38 79 CZ@W25X10CLSNIG
[28] MY2 KSO2/PD2 DAC3/TACH1B/GPJ3(X) CPUFAN# [28]
R600 *10K_4 SPI_SDI_UR 39
[28] MY3 40 KSO3/PD3 VSTBY
R599 *10K_4 SPI_SDO_UR KBMX
[28] MY4 KSO4/PD4
41
[28] MY5 42 KSO5/PD5
[28] MY6 KSO6/PD6
Please do not place any [28] MY7
43
KSO7/PD7
44
pull-up resistor [28] MY8 45 KSO8/ACK#
on GPG0, GPG2, and GPG6 [28]
[28]
MY9
MY10
46 KSO9/BUSY
KSO10/PE
HWPG(KBC) +3V
(Reserved [28] MY11
51
KSO11/ERR# GPJ7
2 TP57
KSI3/SLIN#
KSI1/AFD#
KSI0/STB#

KSI2/INIT#

hardware strapping). 52 128 R300 33_4

B [28] MY12 KSO12/SLCT GPJ6 TPD_INT# [27] B
53 R241
VCORE

[28] MY13 KSO13

AVSS

54
KSI4
KSI5
KSI6
KSI7

[28] MY14
VSS

VSS
VSS
VSS
VSS

55 KSO14 C471
[28] MY15 KSO15 180P/50V_4 10K_4
SM BUS ARRANGEMENT TABLE IT8987E/BX D14 *1N4148WS HWPG
[36] HWPG_0.775VS5 HWPG [5]
58
59
60
61
62
63
64
65

27
49
91
104

75

12

SM Bus 1 Battery D16 *1N4148WS

[36] HWPG_1.8VS5
Layout put in device side
[28] MX0
C401 D17 1N4148WS
[28] MX1 [34] VRM_PWRGD
SM Bus 2 PCH/VGA
ECAGND

[28] MX2
0.1u/16V_4 D13 *1N4148WS
[28] MX3 [33] HWPG_VDDR
[28] MX4
SM Bus 3 N/A D15 *1N4148WS
[28] MX5 [32] HWPG_0.95VS5
[28] MX6
L15 BLM15AG121SN1D(120,500MA)_4 D18 *1N4148WS
[28] MX7 [31] SYS_HWPG
SM Bus 4 N/A

1 3D20 *CZ@1N4148WS
Power sequence Battery B/I SW (SYP) +3VRTC +3VPCU [35] GFX_PWRGD
Q27
CZ@2N7002K

2
+3V R256 CZ@100K/F_4
R641 R642

3
*0_4 *0_4
C437
NBSWON# TP51 CZ@0.22U/10V_4
2
[5] VDDGFX_PD
DNBSWON# TP47
Q26
SUSON TP55 R643 CZ@2N7002K
*10K_4

1
SUSB# +3VRTC
TP54
WRST#
PWROK_EC TP67
1

[30] BI
A PLTRST# TP66 R640 C671 A
3

100K_4 *0.1u/16V_4
HWPG TP18 Vgs = 1.5V
2

MAINON 2 BI_GATE
TP58
Vgs = 1.5V
SW1
1

PCH_RSMRST# TP50
3
4

PJA138K C672 BI_SW

S5_ON Q55 *0.1u/25V_6 6
TP56
1

5
Q56
*PJ4N3KDW
Quanta Computer Inc.
PROJECT : ZRZ
4

1
1
2

Size Document Number Rev

1A
EC (ITE8987E/BX)
Date: Friday, March 06, 2015 Sheet 29 of 41
5 4 3 2 1