1.

)ALU program

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

ENTITY alu8bit IS
port(a, b : in std_logic_vector(7 downto 0); -- a and b are busses
op : in std_logic_vector(2 downto 0);
zero : out std_logic;
f : out std_logic_vector(7 downto 0));
END alu8bit;

architecture behavioral of alu8bit is

begin
process(op)
variable temp: std_logic_vector(7 downto 0);
begin
case op is
when "000" =>
temp := a and b;
when "100" =>
temp := a and b;
when "001" =>
temp := a or b;
when "101" =>
temp := a or b;
when "010" =>
temp := a + b;
when "110" =>
temp := a - b;
when "111" =>
if a < b then
temp := "11111111";
else
temp := "00000000";
end if;
when others =>
temp := a - b;
end case;
if temp="00000000" then
zero <= '1';
else
zero <= '0';
end if;
f <= temp;
end process;
end behavioral;

2.)UART PROGRAM
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FIFO is

port(
--input data
d_in:in std_logic_vector(1 downto 0);

--output data
d_out :out std_logic_vector(1 downto 0);

--write operation
wr_clk:in std_logic;
we:in std_logic;

--read operation
rd_clk:in std_logic;
re:in std_logic;

--FIFO status
full:out std_logic:= '0';
empty:out std_logic:='1'

);

end FIFO;

architecture FIFO_arch of FIFO is

type FIFO_MEM is array( 0 to 3) of std_logic_vector(1 downto 0);

signal fifo :FIFO_MEM;

signal status: std_logic_vector(1 downto 0);
signal wr,rd: integer:= 1; --acts as FIFO pointer
signal wp,rp: integer:= 0 ;

begin

process(wr,rd,wr_clk,rd_clk)
begin
if wr = 0 and rd = 0 then
status <= "11";
elsif wr = 0 then
status <= "10";
elsif rd = 0 then
status <= "01";
else
status <= "00";
end if;
end process;

process(wr_clk,we,rd_clk,re)
begin
if rising_edge(wr_clk) then
if we = '1' then
if (status = "11" and (wp-rp=4)) or (status = "10" and (wr = rd))or (status = "00"
and (wp >4) and (wr = rd))or (status = "01" and (wp - rp = 4)) then
full <= '1';
else
full <= '0';
wp <= wp+1;
wr <= wp rem 4;
fifo(wr) <= d_in;
end if;
end if;
end if;

if rising_edge(rd_clk) then
if re = '1' then
if ((status = "11" or status = "01")and (wp = rp))or (status = "00" and (wp < 4 )
and (rd>=wr)) then
empty <= '1';
else
empty <= '0';
rp <= rp +1;
rd <= rp rem 4;
d_out <= fifo(rd);
end if;
end if;
end if;

end process;

3.)RAM PROGRAM

module i2c_sp_ram(
//Inputs
clk, //clock
wr_en, //write enable
rd_en, //read enable
addr, //address
data_in,//data in

//Output
data_out//data out
);

//Parameter Declaration
parameter DEPTH = 8; //depth of FIFO
parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width
parameter DATA_BUS_WD = 8; //data bus width

//Inputs Declarations
input clk; //Clock
input wr_en; //Write Enable
input rd_en; //Read Enable
input [ADDR_BUS_WD-1:0] addr; //Address Width
input [DATA_BUS_WD-1:0] data_in; //Data Input

//output Declarations
output [DATA_BUS_WD-1:0] data_out; //Data Output

//reg Declarations
reg [DATA_BUS_WD-1:0] mem [DEPTH-1:0];//Memory
reg [DATA_BUS_WD-1:0] data_out; //Data Output

//Generation of data_out
always @(posedge clk)
 begin : READ_GEN
if(rd_en) data_out <= mem[addr];
end
//Generation Writing data into memory
always @(posedge clk)
begin: WRITE_GEN
if(wr_en) mem[addr] <= data_in;
end

4.)8 to 1 multiplexer program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2t1 is
Port ( A : in std_logic;
B : in std_logic;
S : in std_logic;
Y : out std_logic);
end mux2t1;

architecture Behavioral1 of mux2t1 is

begin
process(A, B, S)
begin
if(S = '1') then
Y <= A;
else
Y <= B;
end if;
end process;
end Behavioral1;

architecture Behavioral2 of mux2t1 is

begin
process(A, B, S)
begin
case S is
when '1' =>
Y <= A;
when others=>
Y <= B;
end case;
end process;
end Behavioral2;

architecture Behavioral3 of mux2t1 is

begin
Y <= A when (S = '1') else B;
end Behavioral3;

architecture Behavioral4 of mux2t1 is

begin
with S select
Y <= A when '1',
B when others;
end Behavioral4;
5.)FIR filter program

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;

library maths;
use maths.maths_class.all;
library matrix;
use matrix.matrix_class.all;

entity FIR_32tap_8_8 is
port (
a : in std_logic_vector(7 downto 0);
b : in logic_8_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
y : out std_logic_vector(20 downto 0)
);
end FIR_32tap_8_8;

architecture behavioural of FIR_32tap_8_8 is

constant number_of_taps: integer := 32;

signal data_table: single_vector(number_of_taps-1 downto 0);

signal coefficient_table: single_vector(number_of_taps-1 downto 0);

begin

-- y <= sum_over (0, k-1, a((k-1)-i), b(i))

-- coefficient_table <= b;

fir_algorithm: process (clock)

variable data_out : single;
variable fir_result : single;
variable data_table_var: single_vector(number_of_taps-1 downto 0);
-- the coeff table assignment really ought to be handled at the entity
interface
variable coefficient_table_var: single_vector(number_of_taps-1 downto 0);
variable tmp : single_vector(number_of_taps-1 downto 0);
variable tmp2 : single;
variable tmp3 : single_vector(number_of_taps-1 downto 0);
variable tmp4 : integer;
variable num_taps_minus_1 : integer;
variable y_result : signed(20 downto 0);
begin
if rising_edge(clock) then
-- data_table_var := data_table(number_of_taps-1) &
data_table(number_of_taps-2 downto 0);
-- putting the coeff table in a loop like this allows dynamic coeff updating
for i in 0 to number_of_taps-1 loop
coefficient_table_var(i) := single(to_integer(unsigned(b(i))))/127.0;
end loop;
-- tmp := reverse_order(data_table_var);
 -- tmp2 := 0.15; + to_integer(a);
data_table_var := data_table;
tmp2 := single(to_integer(signed(a)));
data_table_var := shift_fifo (data_table_var, tmp2); -- fifo => data_in =>
data_table <= data_table_var;

-- tmp3 := reverse_order(data_table_var);
-- tmp4 := 0;
num_taps_minus_1 := number_of_taps-1;
fir_result := sum_of_products (
lower_limit => 0,
upper_limit => number_of_taps-1,
a_in => reverse_order(data_table_var),
b_in => coefficient_table_var
);
y_result := to_signed(integer(fir_result), y_result'length);
y <= std_logic_vector(y_result);
end if;
end process;

end behavioural;

6.) finite state machine program

library ieee;
use ieee.std_logic_1164.all;
entity finitestatemachine is
port
( reset, clk, x : in std_logic;
z : out std_logic );
end finitestatemachine;

architecture behavioral of finitestatemachine is

-- The following is an example of a user defined "enumerated" data type
type statetype is (s0, s1, s2,s3,s4);
-- Declaration of two signals of this type
signal state, next_state : statetype := s0; -- Both signals initialized to s0
begin
comb_proc : process (state, x)
begin
case state is
when s0 =>
if x = '0' then
next_state <= s1;
z <= '0';
else
next_state <= s0;
z <= '0';
end if;
when s1 =>
if x = '1' then
next_state <= s2;
z <= '0';
else
next_state <= s1;
z <= '0';
end if;
when s2 =>
if x = '1' then
next_state <= s3;
z <= '0';
else
next_state <= s1;
z <= '0';
end if;
when s3 =>
if x = '1' then
next_state <= s0;
z <= '0';
else
next_state <= s4;
z <= '0';
end if;
when s4 =>
if x = '0' then
next_state <= s1;
z <= '1';
else
next_state <= s2;
z <= '1';
end if;
end case;
end process;
clk_proc : process
begin
wait until (clk'event and clk = '1'); -- wait for rising edge of clk
if reset = '1' then
state <= s0;
else
state <= next_state;
end if;
end process;
end behavioral;

7.) frequency divider program

library ieee;
use ieee.standard_logic_1164.all;

entity freq_div is

port ( clk, rst, d : inout std_logic;

q, qbar : inout std_logic );

end freq_div;

architecture freq_div_a of freq_div is

begin

process(clk, rst)

begin
if (clk'event and clk='1') then
if rst ='1' then
q <= '0';
qbar <= '1';
d <= '0';
else

q <= d;
qbar <= not d;
d <= not q;

end if;

end if;

end process;
end freq_div_a;

8.)bit transmitter(rs232) program

LIBRARY ieee,toplevelib;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use toplevelib.uart_model.all;

ENTITY datacomm_tb1_vhd_tb IS
END datacomm_tb1_vhd_tb;

ARCHITECTURE behavior OF datacomm_tb1_vhd_tb IS

COMPONENT datacomm
PORT(
clk : IN std_logic;
Din : IN std_logic;
DATABUS : INOUT std_logic_vector(7 downto 0);
LD : OUT std_logic_vector(7 downto 0);
SRAMADDRUpper : OUT std_logic_vector(9 downto 0);
SRAMADDR : OUT std_logic_vector(7 downto 0);
OE : OUT std_logic;
WE : OUT std_logic;
LB : OUT std_logic;
UB : OUT std_logic;
CE1 : OUT std_logic;
CE2 : OUT std_logic;
data_out : OUT std_logic_vector(7 downto 0);
AN : OUT std_logic_vector(3 downto 0);
Seven_seg : OUT std_logic_vector(6 downto 0)
);
END COMPONENT;

SIGNAL clk : std_logic;

SIGNAL Din : std_logic;
SIGNAL LD : std_logic_vector(7 downto 0);
SIGNAL SRAMADDRUpper : std_logic_vector(9 downto 0);
SIGNAL SRAMADDR : std_logic_vector(7 downto 0);
SIGNAL DATABUS : std_logic_vector(7 downto 0);
SIGNAL OE : std_logic;
SIGNAL WE : std_logic;
SIGNAL LB : std_logic;
SIGNAL UB : std_logic;
SIGNAL CE1 : std_logic;
SIGNAL CE2 : std_logic;
SIGNAL data_out : std_logic_vector(7 downto 0);
SIGNAL AN : std_logic_vector(3 downto 0);
SIGNAL Seven_seg : std_logic_vector(6 downto 0);

-- A signal for the tester to drive, initialised to "marking"

signal serial_line: std_logic := '1';
BEGIN

uut: datacomm PORT MAP(

clk => clk,
Din => serial_line,
LD => LD,
SRAMADDRUpper => SRAMADDRUpper,
SRAMADDR => SRAMADDR,
DATABUS => DATABUS,
OE => OE,
WE => WE,
LB => LB,
UB => UB,
CE1 => CE1,
CE2 => CE2,
data_out => data_out,
AN => AN,
Seven_seg => Seven_seg
);

-- *** Test Bench - User Defined Section ***

clk <= not clk after 6 us;

tb : PROCESS
constant My_Baud_Rate: integer := 9600;

-- Make a jacket procedure around UART_tx, for convenience

procedure send (data: in std_logic_vector) is
begin
UART_tx(
tx_line => serial_line,
data => data,
baud_rate => My_Baud_Rate
);
end;

variable D: std_logic_vector(7 downto 0);

BEGIN

-- Idle awhile
wait for 1 ms;

-- Send an 8-bit character as a test

send("10001110");

-- Idle some more

wait for 1 ms;

wait; -- will wait forever

END PROCESS;
-- *** End Test Bench - User Defined Section ***
END;