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• Create your directory in explorer
For Example D:\SiMS
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ALTERA Max + plus II Main Tool Window
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File ->Project->Name
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SELLECT YOUR DIRECTORIES :SIMS
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WRITE THE PROJECT NAME E.G.VLSI
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Your project VLSI is created in your specified directory(SiMS)
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FILE -> NEW:SELECT Text Editor FOR WRITING HDL CODE
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Select ‘Text Editor file’ Radio Button -> Ok
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WRITE code IN TEXT EDITOR
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SAVE THE FILE
File ->Save
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Note: Your Entity Name & file name should be same with extension
(*.vhd)
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File ->Project ->Set Project To Current File
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NOTE:-During compilation the design will be compiled &
implemented to the default device:-MAX7000 in one execution
Click Start
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NOTE:-BY DEFAULT IT’S TIMING SIMULATION
Error MessageWindow 19
SIMULATION FOR THE
DESIGN
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Select The waveform Editor for simulation
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SIMULATION :-DEFAULT TIMING
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Right Click Here & Select The Nodes From SNF
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CLICK ON THE LIST & TRANSFER THE DATA USING SYMBOL
SYMBOL List
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Ok
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NOTE:-SAVE THE FILE ONLY ONCE
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Ok 27
We will apply the Stimulus value to the node from the menu bar
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We will apply predefined clock to node a
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MAX + plus -> Simulator
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CLICK ON START TIMING SIMULATION BY DEFAULT
Start 31
RESULT OF YOUR DESIGN
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FUNCTIONAL SUMULATION:GO TO COMPILER
WINDOW,CLICK ON PROCESSING SELECT THE FUNCTIONAL
EXTRACTOR BELOW
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COMPILE THE DESIGN AGAIN
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MAX + plus -> Simulator
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CLICK ON START& OPEN SCF :VERIFY THE DESIGN
Start 36
FOR OTHER FOMAT ,SELECT THE MENU AND COMPILE
AGAIN
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MAX + plus II Floorplan View Of Your Design in Selected
Editor Device
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FLOORPLAN VIEW
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PROGRAMMING TO THE TARGET DEVICE(UVLSI)
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SELLECT THE TARGET DEVICE
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Down Loading the DESIGN to the device
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CHOOSE RADIO BUTTON ‘GRAPHICAL EDITOR FILE’
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DOUBLE CLICK ON THE PAGE
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ENTER THE SYMBOL/LOGIC
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WRITE THE SYMBOL NAME E.G. AND2 -> OK
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NOTE :BUFFERS(I/0) TO CONNECT TO ALL THE INPUT &
OUT PUT
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COPY THE INPUT BUFFER & PASTE IT .DOUBLE CLICK FOR
SELLECTINGLOGIC
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Now we will join the pads with the ports
F3
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Save the Graphical Editor File.
File ->Save
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Give the file name e.g. and2.gdf 64
AND Gate view after saving with .gdf extension 65
Give Port name (a,b,c)by double clicking on the pad.
File -> save 66
Set the the project to current file
Click on Start 69
File has been compiled.
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Max+ plus II -> Compiler
Click On Start 73
You will get the VHDL Netlist generated file
‘and2.vho’