VHDL BASICS

By
JAYMIN BHALANI
Sr. Lecturer, CIT-CHANGA
VHDL BASICS
 VHDL(VHSIC) It is very high speed integrated
circuit hardware descriptive language.
 What for it is used?
 Used to model digital system.
 What are its characterstics?
 It is case- in sensitive, means Ram,RAM rAM all
equal it VHDL.
 -- is used for comments.
 language is similar to ADA,
 If you know C++ or PASCAL it is easy.
 VHDL Basics
 what it is ?
 It is a hardware description language that can be
used to model a digital system at many levels of
abstraction language, ranging from algorithm
level to gate level.
 VHDL BASICS
 What It has?
It has an amalgamation of
.sequential language
.concurrent language
.net-list language
.timing specifications
.waveform generation language
 VHDL HISTORY
 What is its History?
 DOD of USA had started in 1981.
 They thought that it could act as
medium for information
 Exchange between chip foundries and
CAD tool operations.
 Because of Defence it was kept
classified till 1985.
 VHDL HISTORY
 Then lot of private industry participated
for development of this language
 In 1985 DOD had granted permission to
hand over to spec to IEEE.
 IEEE released the number as IEEE
1076 /A. standard in dec 1987.
 IEEE revised in 1993.
 VHDL IS CUNNING
 Advantage of this language is
 Same language is used for analysis and
synthesis
 But, Be careful, some are only simulatable
and not synthesisable.
 Pl, Note
 At the present moment, what can be
synthesizable is very vague, and much are
tool Dependable.
 VHDL IS CUNNING
 Still IEEE is worming on a synthesisable
subset of VHDL which will be supplied
by all the Synthesis vendors.
 VHDL CAPABILITIES
 It is a language, hence it can be used as an
exchange medium between chip vendors and
CAD tool users.
 Means, chip vendors can provide VHDL
descriptions of their components to system
designers. CAD tool users can use them to
capture the behavior of the design at a high
level of abstraction for function simulation.
.
VHDL CAPABILITIES
 It supports hierarchy,
 A Digital system can be modelled as a set of
interconnected components, each
components in turn can be modelled as some
of interconnection subcomponents.
 Simillar to other languages this also supports
flexible design methrodologies top-down
bottom - up or mixed.
 VHDL CAPABILITIES
 It is a Language hence it can also be
used as a common medium between
different CAD and CAE tools. Eg:.
Schematic capture program may be
used to generate a VHDL description
for the design, which can be used as an
input to a simulation program.
 It supports hierarchy,
 VHDL CAPABILITIES
 A Digital system can be modeled as a set of
interconnected components, each
components in turn can be modeled as some
of interconnection sub-components.
 Similar to other languages this also supports
flexible design methodologies top-down
bottom - up or mixed.
 The language is not technology specific
 VHDL CAPABILITIES
 but is capable of supporting technology
specific feature, supports various handware
technology. Eg: You may define new logic
types and new components. You can also
model technology dependent components.
 By being technology independent the same
model can be synthesized in to different
vendor libraries.
 VHDL CAPABILITIES
 Supports both synchronous and
asynchronous timing models.
 You can use, FSMs, state tables, algorithm
descriptions, Boolean, wave form entry, etc,
 Nowadays the new tools like VISUAL HDL
are available using them even flowchart,
block level, also can be used as design entry.
 It is similar to English language.
 VHDL SUPPORTS
.structural,
.data-flow,
.behavior
 A combination of all the three also
possible.
 Wide range of abstraction levels from
abstract behavior description to very
precise gate level.
 But, below transistor level not possible.
 VHDL SUPPORTS
It has elements, that make large scale
design modeling easier.
HOW?
Using this you can create
components, functions, procedures,
and packages, test benches,
you can model Propagation delay, Min-
max delay, setup and hold time etc.,
 VHDL SUPPORTS
 One can use generics, and attributes
which are useful in describing
paramaterised model.
 c o n tro l b u s
add bus
d ig it a l s y s t e m
d a ta b u s eg:
m ic r o p r o c e s s o r

in t lin e s ,

e x te r n a l v ie w

a r c h ite
a c c u la in t c tu re
a lu m e m o ry
to r h a n d lin g 1
d e v ic e d e v ic e
d e v ic e d e v ic e
e n tity e n tity
e n tity e n tity
a r c h it e
c tu re 1 a r c h ite c tu r e
2
o n ly 1 o n ly 1 a r c h ite
a r c h it e a r c h it e a r c h ite c tu re 3
c u tre c tu re c tu re
2
 VHDL Terminology
 Digital system can be as simple as logic
gate to complex system.
 Hardware abstraction of this system called
entity ( component) .
 An entity X when used in entity Y becomes
a component for the entity Y.
VHDL Terminology
 VHDL provides five different types of
primary constructs, called design units
 1. Entity declaration
 2. Architecture body
 3. Configuration Delcaration
 4. Package declaration
 5. Package body
 VHDL Terminology
E n t it y E 1 E n tity E 2

M 1 :...

B X :... C X :...

E 2_A 1 E 2_A 2

E 1_A 1 E 1_A 2 E 1_A 3

E n t it y E 3

E 3_A 1 E 3_A 2 E 3_A 3

VHDL Analyzer
 Once an entity is modeled,it needs to be
analyzed and finally it has to be simulated.
 Then we can say a component is created.
 So Next step is analyzer and simulator
 analyzer reads in one or more design units
contained in a single file and compiles them
into a design library after validating syntax
 VHDL Analyzer
 and performing some static semantic
checks. This design library is your library,
means your project library.
 design library is a place in the host
environment where compiled design units
are stored.
 VHDL Simulator
 The simulator simulates
 entity
 we know that each “entity” is represented
by an “entity-architecture” pair or by a
configuration, by reading in its compiled
description from the design library and then
performing the following steps.
 VHDL Simulator
 Elaboration
 initialization
 simulation
 Entity
 Entity declaration specifies the name of the
design ( component) being modeled and the
set of interface ports.
 Ports are signals through which entity
communicates with the other models in its
external environment.
Entity Example
A sum
x1

B
A1 c a rry

- - s t a r t o f e n t it y
e n t i t y H A L F _ A D D E R is
- - p o r t d e c la r a t io n s t a r t s
po r t ( A , B :in B I T ; S U M ,C A R R Y : o u t B IT ) ;
- - p o r t d e c la r a t io n e n d s
end H ALF_AD D ER ;
- - e n d o f e n tity d e c la r a tio n
VHDL Architecture Body
 What does architecture does?
 It describes the internal details of an entity.
 How it does?
 Using any of the following modeling styles:
 A set of interconnected components ( to
represent structure)
VHDL Architecture Body
 A set of concurrent assignment
statements( to represent dataflow)
 A set of sequential assignments ( to
represent behavior)
 As any combination of the above three.
  VHDL Structural style

 Here entity is described as a set of

interconnected component. Example for
Half_adder is
VHDL Structural style example
a r c h it e c t u r e H A _ S T R U C T U R E o f H A L F _ A D D E R is
c o m p o n e n t x o r2
p o r t ( in 1 , in 2 : in B it ; o 1 :o u t B IT ) ;
e n d c o m p o n e n t;
com ponent A N D 2
p o r t ( X , Y : in B it ; Z :o u t B I T ) ;
e n d c o m p o n e n t;
b e g in
u 1 : x o r2 p o rtm a p (H A P P Y 1 ,H A P P Y 2 ,A L L H A P P Y );
U 2 : a n d 2 p o r t m a p ( s a d 1 ,s a d 2 , a lls a d ) ;
e n d H A _ S tru c tu re ;
 VHDL Structural style
 HA_STRUCTURE is the name of the architecture.
 HALF_ADDER is an entity
 BEGIN and END are key words used to say start
and end of the architecture.
 The two components xor2,and2 are declared in the
declarative part of the architecture body.
 Between Begin and End is the statement part.
 VHDL Structural style
 Where these xor2, and and2 exists?
 They may be predefined components in a
library or, if they do not exist, they may
later be bound to other components in a
library.
 The declared components are instantiated in
the statement part of the architecture body
using component instantiation statements.
 VHDL Structural style
 U1, u2 are components labels for the
components.
 Signals in the port map of a component
instantiation and the port signals in the port
map of a component instantiation and the
port signals in the component declaration
are associated by position (called positional
association.
 VHDL Structural style
 The structural representation for the
HALF_ADDER does not say anything
about its functionality. Separate entity
models would be described for the
compoenents xor2 and and2, each having its
own entity declaration and architecture
body.
VHDL Data Flow style
 Here the flow of data through the entity is
expressed primarily using concurrent signal
assignment statements. The structure of the
entity is not explicitly specified in this
modeling style, but it can be implicitly
deduced. Look at this example.
 VHDL Structural style
 architecture HA_CONCURRENT of
HALF_ADDER is
 begin
 sum <= A xor B after 8 ns;-- concurrent stat
 Carry <= A and B after 4 ns ;-- concurrent
stat end HA_CONCURRENT;
  VHDL Structural style
 The data flow model for the HALF_ADDER is
described using two concurrent signal assignment
statements.
 In a signal assignment statement, the symbol <=
implies an assignment of a value to a signal. The
value of the expression on the right hand side of
the statement is computed and is assigned to the
signal on the left hand side, called target signal.
  VHDL Structural style
 Remember, a concurrent signal assignment
statement is executed only when any signal used
in the expression on the right hand side has an
event on it that is, the value for the signal changes.
 Concurrent signal assignment statements are
concurrent statements, the ordering of these
statements in an architecture body is not important
  VHDL Structural style
 “After” clauses needed to incorporate the delay.
 Here both signal assignments statements execute
concurrently.
 Means, here we have two signals
 Signal A or B, which are input port signals of our
Half_Adder, It has an event, say at time T,

 VHDL Structural style
 the right hand side expressions of both
signal assignment statements are evaluated
Signal SUM is scheduled to get the new
value after 8 ns.
 while signal CARRY is scheduled to get the
new value after 4 ns. CARRY will get its
new value,and when simulation time
advances to (T+8)ns, SUM will get its new
value.
 VHDL Structural style
 The after clause may be used to generate a
clock signal
 clk <= not CLK after 10ns;
 this statement creates a periodic waveform
on the signal CLK with a time period of 20
ns,

CLK
10 20 30 40 50 60 70
 VHDL Behavioral style
 This modeling is in contrast to earlier
modelings.
 The behavioral style modeling specifies the
behavior of an entity as a set of statements
that are executed sequentially in the
specified order. This set of sequential
statements, which are specified inside a
process statement, do not explicitly specify
 VHDL Behavioral style
 the structure of the entity but merely its
functionality. A process statement is a concurrent
statement that can appear within an architecture
body.
a r c h ite c tu r e D E C _ S E Q U E N T IA L O F D E C O D E R 2 X 4 IS
b e g in
p ro c e s s (A ,B ,E N A B L E )
V A R IA B L E a b a r , b b a r : b it;
b e g in
a b a r := n o t A ;
b b a r:= n o t B l
if e n a b le = '1 ' t h e n
z (3 ) < = n o t ( A a n d B );
z (0 ) < = n o t (a b a r a n d b b a r);
z (2 ) < = n o t ( A a n d b b a r);
z (1 ) < = n o t ( a b a r a n d B );
e ls e
z < = "1 1 1 1 ";
e n d if ;
e n d p ro c e s s ;
e n d D e c _ S e q u e n tia l;
VHDL Behavioral style
 VHDL Behavioral style
 A process statement also has a declarative
part( before keyword begin) and statement part
( between the keyword begin and end process).
The statements appearing within the statement part
are sequential statements and are executed
sequentially. The list of signals specified within
the parentheses after the keyword process
constitutes a sensitivity list, and the process
statement is invoked whenever there is an event on
any
 VHDL Behavioral style
 signal in this list. In the previous example when
an event occurs on signals A, B, or Enable, the
statements appearing within the process statement
are executed sequentially.
 Variables declared in the processes have their
scope limited to that process. Variables can also
be declared in sub programs.
 It is possible to use case or loop statements within
a process.
 VHDL process
 We can use case, loop etc within process.
Normally they are similar as C or pascal.
 An explicit wait statement can also be used
to suspend a process. It can be used to wait
for a certain amount of time, until a certain
condition becomes true, or until an event
occurs on one or more signals.
 Eg: process
 begin
 clk <= ‘0’;wait for 20 ns;
 clk <= ‘1’;wait for 12 ns;
 end process;

c lk

0 20 32 52 64 84 96
 VHDL process
 This process does not sensitivity list pl. observe
the code.
 Because explicit wait statements are present inside
the process. It is important to remember that a
process never terminates. It is always either being
executed or in suspended state. All processes are
executed once during the initialization phase of
simulation until they get suspended.
 VHDL process
 A process with no sensitivity list and no
explicit wait statement will never suspend
itself.
 Eg: of DFF.
 Entity DFF IS
 Port (Q:out BIT; D,clk: in BIT);
 End DFF;
 VHDL process
 Architecture DFF_beh of DFF is
 Begin
 Process ( D,clk)
 Begin
 If clk = '1' then
 Q <= D;
 End if;
 End process;
 End Dff_beh;
 VHDL process
 This process executes whever there is an even
on signal D or CLK. If the value of CLK is '1' ,
the value of D is assigned to Q. If CLK is '0',
then no assignment to Q takes place. Thus, as
long as CLK is '1' any change on D will appear
on Q. Once clk becomes '0', the value in Q is
retained.
VHDL Mixed style modeling
 Within architecture All three can be mixed.
 Ie.,
 we can use component
instantiation( structure)
 concurrent signal assignments(dataflow)
process statements ( behavior).
VHDL FULL ADDER MIXED
Entity FA is
Port ( a,b,cin:in bit; sum,cout:out bit);
End FA
Architecture FA_mixed of FA is
Component xor2
Port(p1,p2:in bit; pz :out BIT);
End component;
Signal s1:bit;
Begin
X1:xor2 portmap (A,B,S1); -- - structure
Process ( A,B,CIN) -- - behavior
Variable t1,t2,t3:bit;
Begin
T1 := A and B;
T2 := B and cin;
T3 := a and cin;
Cout <= t1 or t2 or t3;
End process;
Sum <= s1 xor cin; -- -- dataflow
End FA;
 EXAMPLE FOR MIXED
MODELING
A
x1
x1
S U M
C IN
B

C A R R Y

B E H A V IO R

This FA is done with one component instantiation

one process statement ,
one concurrent signal assignment.
Note all these statements are concurrent statements.
Therefore their order of appearance within the architecture
body is not important.
 This is done using one component instantiation
one process statement and ond concurrent
signal assignment. Note all these statements
are concurrent statements. Therefore their order
of appearance within the architecture body is not
important.
 VHDL configuration
declaration
 As discussed earlier, an entity can consists
of any no of architectures but, while
compilation only one architecture should be
there. This can be dictated by configuration
file .
 So, a configuration is used to select one of
the possiblly many architecture bodies that
an entity may, have, and to bind coponents,
 VHDL configuration
declaration
 Used to represent structure in that architecture
body, to entities represented by an entity-
architecture pair or by a configuration which
reside in a design library,
 eg:
 VHDL configuration
declaration
Library cmos_lib,my_lib; -- - library clause both library visible in configuration
Configuration Ha_binding of half_adder is - -configuration name Ha_binding and specifies
For ha_structure -- specifies that the architecture body it has two components
-- threfore two configuration. X1 repesents entity architecture pair,
For x1:xor2 -- - xor gate and dataflow architecture which resides com_lib
-- - design library.
Use entity cmos_lib.xor_gate(dataflow);
End for;
For A1:and2 -- similarly for and2 also.
Use configuration My_lib,and_config;
End for;
End for;
End Ha_binding;
 Package declaration
A package declaration is used to store a set of common
declarations such as components,types, procedures, and
functions. These declarations can then be imported into other
design units using a "use" clause.
Package ex_traffic_light is ---- name of package it has type,
component, function
 see that int2bit_Vec does not appear in the
package
 -- only interface appears,
Type color is (red,green,yello);
Component D_myFF
Port (D,CK: in bit; Q :out BIT); End component;
Constant pin2pin_delay :time := 125ns;
Function int2bit_vec ( int_value:integer)
Return bit_vector;
End ex_traffic_light;
 Package declaration
Used to store the definitions of functions and procedures that
were declared in the corresponding package declaration, and
also the complete constant declarations for any declarations
of any deferred constants that appear in the package
declaration.
Package body is always associated with package declaration.
Package declaration can have at most one package body
associated with it. Contrast this with an architecture body and
an entity declaration, where multiple architecture bodies may
be associated wit a single entity declaration
 Package declaration
Package body exam_pack is - - name of the package is same as
package declarations
Function int2bit_vec ( int_value:integer)
Return bit_vector is
Begin
 - -behavior of function described here.
End int2bit_vec;
End exam_pack;
THANK YOU ALL
SIRS
You Need Not Read
Heavy Books
Just refer them
Just Practice,
It makes you Perfect
Wish you
all the Best.