Low-Error and Efficient Fixed-Width Squarer for
Digital Signal Processing Applications
Van-Phuc Hoang and Cong-Kha Pham
VLSI Laboratory, Department of Electronic Engineering
The University of Electro-Communications
1-5-1 Chofugaoka, Chofu-shi, Tokyo, 182-8585, Japan
Email: hoang (at) vlsilab.ee.uec.ac.jp
Abstract—This paper presents a new approach of using the
improved hybrid LUT-based architecture for the low-error and
efficient fixed-width squarer circuits. By employing both LUT-
based and simple conventional logic circuits, the good trade-off
between hardware complexity and performance can be achieved.
Moreover, the mathematical identity of squaring operation is
exploited so that the error can be reduced significantly compared
with other methods. The proposed method can also improve the
speed and reduce the area of squarer circuit. The implementation
and chip measurement results in 0.18-µm CMOS technology are
also presented and discussed.
I. I NTRODUCTION
High performance multiplier and squarer circuits are exten-
sively used and play an essential role in modern and future
digital signal processing (DSP) systems due to the increas-
ing demand of high speed applications. Especially, squaring
is a fundamental arithmetic operation in many applications
such as Viterbi decoding, digital filtering, vector quantiza-
tion, pattern recognition and image compression. However,
direct implementation of general parallel squarer circuits often
requires high hardware complexity and may lead to high
power consumption. Moreover, the high increase of mobile
and portable devices leads to the emerging requirement of low
power consumption and low complexity digital circuits [1].
Therefore, recently, there have been many researches trying to
find the efficient architectures for low area, low power and high
performance squarer circuit. Some proposed methods such as
folded technique [2], merged technique [3] and K.-J. Cho et al.
method [4] employ some mathematic identities to reduce the
hardware complexity and improve the performance of the full-
width squaring circuit. A. G. M. Strollo et al. [5] proposed an
improved method that combines Booth recoding with folded
technique and some specific sub-circuits.
On the other hand, in many DSP applications, when the
squaring result is not required to be full-width but the same bit-
width as the operand, the architecture for high performance,
low complexity fixed-width squarer becomes an important
topic with many issues needed to be considered such as error
compensation, hardware efficiency and squarer performance.
Authors in [6] and [7] have proposed some methods to improve
the accuracy and performance of the truncated and fixed-width
squarer circuits, but more improvements are desired, especially
for future DSP systems which require high performance,
978-1-4673-2493-9/12/$31.00 ©2012 IEEE
low power consumption circuit to meet the high demand of
portability and mobility.
Moreover, lookup table (LUT)-based computation has great
potential to be employed in future DSP and communication
systems because it mainly relies on memory access operations
resulting in high speed computation and low power consump-
tion [8]. The disadvantage that limits the popularity of LUT-
based architecture in current systems is the exponential growth
of LUT size as the operand width increases. Therefore, it is
reasonable to find a proper hybrid architecture that takes the
advantage of both LUT-based circuit and conventional logic
circuits so that the good trade-off between squarer performance
and hardware complexity can be achieved. And in this paper,
we present a new approach for designing the fixed-width
squarer circuit for specific DSP applications by employing an
improved hybrid LUT-based architecture to reduce the error,
delay and hardware complexity. The main contribution of our
paper is that an improved architecture for low error and area-
delay efficient fixed-width squarer is proposed by employing
a specific mathematic identity of squaring operation in a new
approach with some improvements.
The rest of this paper is organized as follows. Section II
introduces briefly about fixed-width squarer and section III
presents the proposed hybrid LUT-based architecture for fixed-
width squarer. Section IV shows the error analysis results
and section V summaries the implementation and chip mea-
surement results of proposed squarer architecture using 0.18-
µm CMOS technology. Finally, the conclusion is included in
section VI.
II. F IXED - WIDTH SQUARER
In this paper, we consider the square of W -bit binary
number X and the full-width (2W -bit) square X 2 can be
written as:
(W ∑ −1 )2 W∑−1 W
∑ −1
i
S=X = 2
xi 2 = xi xj 2i+j (1)
i=0 i=0 j=0
where xi and xj denote the binary bits of X. Fig. 1 shows the
original partial product matrix (PPM) for a general full width
8-bit squarer in which each partial product bit pij is computed
by an AND logic operation as: pij = xi xj .
In a full-width squarer, all partial product bits in PPM
are summed by using compression tree and adder [2]. Some
477
 p70 p60 p50 p40
p71 p61 p51 p41 p31
MSP
p72 p62 p52 p42 p32 p22
p73 p63 p53 p43 p33 p23 p13
p74 p64 p54 p44 p34 p24 p14 p04
p75 p65 p55 p45 p35 p25 p15 p05
p76 p66 p56 p46 p36 p26 p16 p06
p77 p67 p57 p47 p37 p27 p17 p07 IC
(15) (14) (13) (12) (11) (10) (9) (8) (7) (6) (5) (4)
Fig. 1. Original partial product matrix of the 8-bit fixed-width squarer.
methods proposed in [2]-[4] exploit some mathematical iden-
tities of squaring operation to reduce the complexity of PPM
summation.
However, in a fixed-width squarer, the square result is re-
quired to have the same bit-width as the operand. For example,
in the 8-bit fixed-width squarer as shown in Fig. 1, the 8-bit
square result corresponds to 8 maximum significant bits of
the full-width square result. The most accurate fixed-width
squaring method is the ideal rounding in which all partial
products in PPM are summed and the full-width (2W -bit)
result is rounded to provide the fixed-width (W -bit) result. For
more mathematical convenience, as shown in Fig. 1, the PPM
is divided into three parts: MSP (Maximum Significant Part),
IC (Input Correction) and LSP (Least Significant Part). The
ideal rounding operation can be improved by adding ’1’ to the
IC column as the correction constant before summing and then
simple dropping some least significant bits of the full-width
result to get fixed-width square result. Two above methods lead
to high complexity and long delay because all partial products
of IC and LSP are generated and accumulated. Therefore, to
reduce the hardware complexity and delay, in more improved
methods of fixed-width squarer, LSP is discarded and IC is
used to compensate the error caused by discarding the LSP.
E. G. Walters III et al. [9] proposed an architecture for
truncated squarer with variable correction scheme. Kyung-
Ju Cho et al. [6] presented the adaptive error compensation
method for fixed-width squarer with more mathematical anal-
ysis and modifications of Booth folding encoding method.
And V. Garofalo et al [7] proposed an improved method by
applying the analytical technique presented in [10] and [11]
to find the sub-optimal linear compensation function to reduce
the error and number of partial products. The approximated
linear function of f (IC) is based on the IC column so that
the approximated square Xt2 is computed as:
Xt2 ≃ SM SP + f (IC) + KR
where KR and SM SP denote the correction constant and
weighted sum of M SP , respectively. This method results
in the reduction of mean error from 5% to 20% compared
with previous methods and also improves the performance of
squarer circuit.
p30 p20 p10 p00
p21 p11 p01 W Lookup 2W
X X2
p12 p02 Table
p03
LSP
Fig. 2. General LUT-based full-width squarer.
(3) (2) (1) (0) III. P ROPOSED HYBRID LUT- BASED FIXED - WIDTH
SQUARER
The LUT-based circuit provides the outputs by accessing the
pre-stored lookup table (LUT) other than actual computations.
This look-up only operation leads to high speed computation
because it mainly requires only time for accessing the pre-
stored tables. Moreover, LUT-based circuits consume less
dynamic power because of less bit-switching [12]. As shown
in Fig. 2, an LUT-based full-width squarer requires an LUT
of 2W × 2W bit to store 2W words with the word length of
2W -bit. For the case of fixed-width squarer using this direct
LUT-based architecture, an LUT of 2W × W bit is required
to store ideally rounded values of squaring computation. The
maximum error in this ideally rounded direct LUT-based
squarer is restricted by only 0.5 LSB (Least Significant Bit)
of the squaring result. However, this direct LUT-based imple-
mentation leads to exponentially growth of LUT size when
the operand width increases. Therefore, some methods were
proposed to reduce the LUT size for LUT-based computation
design.
Pramod Kumar Meher [8] has proposed some methods
of the LUT optimization that can reduce the LUT size sig-
nificantly for LUT-based constant multiplier. However, these
methods can not be applied directly for the fixed-width squarer
because of the different PPMs and truncation operation re-
quired in fixed-width squaring computation. And some im-
proved methods for fixed-width and truncated multipliers can
not be employed directly for design of fixed-width squarer
[11]. As a result, a more accurate and efficient architecture
for fixed-width squarer is highly desired. And it is reasonable
to make the good trade-off between LUT-size and squarer
performance by employing a hybrid LUT-based structure for
squarer by properly using both LUT and conventional logic
circuits.
Again, consider the square of the W -bit binary number
as presented in (1). In this section, we apply the mathe-
matic characteristics presented in [13] and [14] with some
modifications and improvements as described below. The
(2) novelty of our proposed approach is that a specific mathematic
identity of squaring operation presented in [13] and [14] is
employed in a new method to derive an efficient architecture
for the fixed-width squarer circuit with lower error and higher
area-delay efficiency. Let X = (xW −1 xW −2 . . . x1 x0 ) and
Y = (yW −1 yW −2 . . . y1 y0 ) be two W -bit binary numbers
satisfying that yi = xi , 0≤ i ≤ (W − 1), the difference D
478

Fig. 3. Proposed hybrid LUT-based architecture for fixed-width squarer.
between squares of two numbers can be expressed as:
D = |X| − |Y | = −yn−1 2W (2W + 1) +
2 2
|xW −2 xW −3 . . . x1 x0 0yW −2 yW −3 . . . y1 y0 1|
where |X| denotes the absolute value of the binary number
X. Therefore, when yW −1 = 0, i.e. xW −1 = 1, it is derived
that:
D = |xW −2 xW −3 . . . x1 x0 0yW −2 yW −3 . . . y1 y0 1|
Exploiting this mathematical property, we can derive the
relationship between the square of the number X and its binary
bits as shown in table I for the case of four-folding together
with the following equation:
2 2
|X| = |Y | + D
The four-folding method means that two maximum significant
bits of operand are used as selecting bits to form the squaring
result. Exploiting (5), to get the fixed-width result, the round-
ing operation of square can be approximated by summing the
rounding results of its components as follow:
2 2
roundW (|X| ) ≃ roundW (|Y | ) + roundW (D) (6)
in which roundW (•) denotes the operation of rounding to
W -bit result. This approximation is optimal if one of the
two rounding operations in right part of (5) is error-free. In
this section, we present a sub-optimal approximation method
using hybrid LUT architecture to reduce the error as much as
possible.
As shown in table I, the component D is divided into two
parts: DH (high part) and DL (low part), each part has the
same bit length of W . Therefore, it is obvious that:
D = |DH| 2W + |DL|
As one can see in the fourth column of table I, the maximum
significant bit of DL is always zero. Hence, the operation can
be approximated by discarding the DL part and the result of
this rounding operation can be approximated by DH part.
The maximum error can be easily estimated as 1 LSB of
result compared with the ideal rounded result. Assume that
2
the operation roundW (|Y | ) can be performed by the ideal
rounding to get W -bit result, the general maximum error of
the approximation in (3) will be 1 LSB compared with ideal
A
Coarse
LUT
W-3
Adder Y2
Y
A+B
Fine
LUT
Fig. 4. Coarse/fine LUT splitting to further reduce the LUT size.
rounded result. Therefore, it is promising that this method can
result in low error squarer circuit. The results of error analysis
will be shown in the next section.
The block diagram of the proposed fixed-width squarer
using the improved hybrid LUT-based architecture is shown in
(3) Fig. 3. The AMU (Address Mapping Unit) has the function of
inverting (one’s complement) the input operand and generating
the (W -2)-bit address for the LUT. The LUT block is used
to provide the square values of its address input. The 4-input
multiplexer (MUX4) is used to generate the DH part as shown
(4) in table I by using two maximum significant bits (M SB2) as
the selecting bits. Then an adder provides the final fixed-width
(W -bit) square result.
In general, the LUT size is reduced to 2W −2 × (W − 3) bit
because it stores the rounding of 2(W − 2)-bit result of Y 2 .
However, for the designs with with W ≥ 10, the coarse/fine
(5) LUT splitting method [15] is also employed to further reduce
the LUT size as shown in Fig. 4. The input Y with the bit-
width of (A + B) is decomposed into two components: one
with lower bit-width (A-bit) for addressing the coarse LUT and
another with the same bit-width of (A + B)-bit for addressing
the fine LUT. The coarse LUT has the same width but fewer
storage entries than traditional one, while the fine LUT has
smaller width and the same storage entries as traditional one
to store the difference between the rounded Y 2 and coarse
LUT entries. An additional adder is needed to provide the
result of Y 2 .
IV. E RROR ANALYSIS OF THE PROPOSED FIXED - WIDTH
SQUARER
In this paper, the mean error (M E), maximum error
(M axE) and mean square error (M SE) are used as error
criteria for error analysis. The mean error and mean square
error are related to the power of the error and hence play very
(7) important role in DSP applications. However, the maximum
error becomes the most important concern in safety critical
applications [16]. The error caused by approximation in (3)
together with ME and MSE can be expressed as:
2
Er = X 2 − (roundW (|Y | ) + roundW (D)) (8)
M E = E{Er} (9)
M SE = E{Er2 } (10)
where E{•} denotes the averaging operation.
479
 TABLE I
F OUR - FOLDING METHOD FOR HYBRID LUT- BASED FIXED - WIDTH SQUARER .
M SB2 Y DH DL
00 xW −3 . . . x1 x0 000. . . . . . . . . . . . 00 (DH0) 00. . . . . . . . . . . . 00
01 xW −3 . . . x1 x0 00xW −3 . . . x1 x0 (DH1) 0xW −3 . . . x0 1
10 xW −3 . . . x1 x0 01xW −3 . . . x1 x0 (DH2) 00. . . . . . . . . 00
11 xW −3 . . . x1 x0 1xW −3 . . . x1 x0 0 (DH3) 0xW −3 . . . x0 1

TABLE II
E RROR ANALYSIS RESUTS FOR DIFFERENT FIXED - WIDTH SQUARER
ARCHITECTURES .

ME MaxE MSE
W Method
(LSB) (LSB) (LSB2 )
Walter et al. [9] 0.166 1.215 0.207
Garofalo et al. [12] 0.334 - 0.441
8
Garofalo et al. [7] 0.166 1.260 0.163
Proposed 0.100 0.106 0.105
Walter et al. [9] 0.166 - 0.226
Garofalo et al. [12] 0.333 - 0.529
10
Garofalo et al. [7] 0.166 1.263 0.181
Proposed 0.119 1.062 0.120
Walter et al. [9] 0.167 - 0.246
Garofalo et al. [12] 0.333 - 0.607
12
Garofalo et al. [7] 0.167 1.308 0.200
Proposed 0.118 1.103 0.119
Walter et al. [9] 0.167 - 0.266 Fig. 5. ADP results for different values of W .
Garofalo et al. [12] 0.333 - 0.693
14
Garofalo et al. [7] 0.167 1.365 0.220
Proposed 0.120 1.117 0.124
Walter et al. [9] 0.167 1.862 0.287
16
Garofalo et al. [12] 0.333 - 0.776 Synopsys Design tools using the same standard cell library
Garofalo et al. [7] 0.167 1.432 0.240 with the same design parameters and constrains for different
Proposed 0.122 1.120 0.125
values of W . For the designs with W ≥ 10, the coarse/fine
LUT splitting method is also employed to further reduce
TABLE III the LUT size as shown in Fig. 4. Table III shows the LUT
LUT PARAMETERS AND COMPRESSION RATIO OF THE PROPOSED
FIXED - WIDTH SQUARER DESIGNS WITH LUT SPLITTING TECHNIQUE .
parameter, size and compression ratio of different fixed-width
squarer designs using proposed hybrid LUT-based architecture
W 8 10 12 14 16 and coarse/fine LUT splitting method in which A and B denote
A - 5 7 8 9 the input widths of two split LUTs as depicted in Fig. 4. The
B - 3 3 4 5
compression ratio is calculated as the ratio between direct LUT
Proposed LUT (bits) 320 704 3072 10752 38912
size and proposed LUT size (in bits).
Direct LUT (bits) 2048 10240 49152 229376 1048576
Compression ratio 6.4:1 14.5:1 16:1 21.3:1 26.9:1 The implementation results in 0.18-µm CMOS technology
are presented in table IV and Fig. 5. It is shown that the
proposed fixed-width squarer can reduce the area and delay
significantly when compared with other methods. To compare
Table II summaries the error analysis results and the com- the overall squarer performance with different methods, the
parison between proposed squarer and other architectures. area-delay product (ADP) is used as a factor of merit for com-
It is shown that the proposed fixed-width squarer results in parison. The bold numbers in parentheses of the fifth column
lower error compared with others. The mean error and mean in table IV present the normalized ADP results of different
square error of proposed squarer can be reduced by up to fixed-width squarer designs with each value of W . Compared
40% compared with these values of V. Garofalo et al. method with the fixed-width squarer method as presented in [7], the
presented in [7] whereas the maximum error can be reduced by proposed hybrid LUT-based architecture leads to the reduction
up to 22%. The low error merit makes the proposed method of ADP up to 42%. Fig. 6 is the chip microphotograph of the
highly applicable for future DSP applications which require proposed 8-bit fixed-width squarer which is fabricated with
not only high speed and low power but also low error squarer 0.18-µm CMOS technology. Fig. 7 presents the chip functional
circuits. measurement using logic analyzer (right side) which is the
same as the simulation result in Modelsim software (left side).
V. I MPLEMENTATION RESULTS And table V shows the measurement results for average power
The proposed fixed-width squarer and other architectures consumption and longest (critical) path delay (between the
have been implemented in 0.18-µm CMOS technology by input x6 and the output s7 ) as depicted in Fig. 8.

480
 TABLE IV 40 µ m
I MPLEMENTATION RESULTS OF DIFFERENT FIXED - WIDTH SQUARER
ARCHITECTURES USING 0.18-µ M CMOS TECHNOLOGY.

Area Delay
W Method ADP (x103 )
(103 µm2 ) (ns)
Folded 2.3 6.6 15.3 (1.34)
Direct LUT-based 4.0 4.8 19.2 (1.68)
8
Garofalo et al. [7] 1.9 5.9 11.4 (1.00)
Proposed 1.5 4.4 6.6 (0.58) 40 µ m
Folded 3.8 7.4 28.3 (1.33)
Direct LUT-based 19.6 6.2 121.7 (5.73)
10
Garofalo et al. [7] 3.3 6.5 21.2 (1.00)
Proposed 2.7 5.6 15.1 (0.71)
Folded 6.1 8.6 52.9 (1.20)
Direct LUT-based 48.8 6.9 336.7 (7.66)
12
Garofalo et al. [7] 5.4 8.2 43.9 (1.00)
Proposed 5.0 6.7 33.5 (0.76)
Folded 8.7 9.9 86.6 (1.23)
Direct LUT-based 98.9 7.9 762.4 (11.1) Fig. 6. Chip microphotograph of the proposed 8-bit fixed-width squarer.
14
Garofalo et al. [7] 7.7 9.1 70.5 (1.00)
Proposed 7.4 7.6 56.2 (0.80)
Folded 10.5 11.0 115.7 (1.21) X 7E 7F 80 81 82
16
Direct LUT-based 208.7 9.4 2024.4 (21.2) x7
Garofalo et al. [7] 9.2 10.4 95.4 (1.00) x6
Proposed 8.9 9.0 80.3 (0.84)
x5
x4
TABLE V x3
C HIP PARAMETERS OF THE PROPOSED 8- BIT FIXED - WIDTH SQUARER . x2
Technology 0.18-µm x1
Supply voltage (V DD) 1.8 V x0
Average power consumption 0.362 mW @ 50 MHz S 3E 3F 40 41 42
Longest path delay 4.7 ns s7
s6
s5
s4
VI. C ONCLUSION s3
In this paper, we have presented an efficient approach for de- s2
sign of the fixed-width squarer circuits with low error and high s1
area-delay efficiency. The improved hybrid architecture em- s0
ploys both LUT-based and simple conventional logic circuits to
achieve the good trade-off between the circuit performance and Fig. 7. Simulation result in Modelsim software (left) and measurement result
complexity. The implementation and chip measurement results in logic analyzer (right).
in 0.18-µm CMOS technology have been shown together with
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