This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts
for publication in the IEEE ICC 2010 proceedings
A Novel FPGA-based 2.5Gbps D-QPSK Modem
for High Capacity Microwave Radios
Zhongxia (Simon) He† Jingjing Chen‡
zhongxia@chalmers.se
†Microwave Electronics Lab, Dept. of Microtechnology and Nanoscience, Chalmers University of Technology, Sweden
‡Microwave and High Speed Electronics Research Center, Ericsson Research, Sweden
Abstract—A novel FPGA-based Differential QPSK modem
(modulator and demodulator) is presented for data rates up
to 2.5Gbps, in which no DAC or ADC is used. The targeted
application is E-Band microwave Point-to-Point radio links in
mobile backhaul for LTE and beyond.
I. I NTRODUCTION
As wireless technology evolves toward LTE and beyond,
more and more mobile broadband services will roll out and
consequently bandwidth demanding data traffic will grow
rapidly. As a result, operators have to find the right technical
and commercial approach to meet the increasing demand in
network capacity as well as to manage the challenges of
convergence, flexibility and cost-effectiveness. In terms of
capacity, Giga-bit speed is required for LTE backhauling. Even
high capacity is predicted for the LTE-Advanced.
Microwave links have been the obvious mobile backhaul
choice for many operators [1]. Giga-bit capacity may be
provided using microwave radios in the traditional bands (6-
38GHz) with high-order modulation scheme in combination
with polarization and/or spacial multiplexing, which means
high-degree of complexity. An alternative is to use the newly
released E-band (71-76GHz and 81-86GHz) dedicated for
Point-to-Point (PtP) application. In this band, 10GHz spectrum
is available and spectrum efficiency is usually not of the
highest priority. This allows the use of low-order modulation
schemes and simple receiver implementation.
The so-called differential quadratural phase-shift keying (D-
QPSK) is popularly used in optical systems. One benefit of
using D-QPSK is the absence of phase and carrier recovery in
signal detection, resulting in simple receiver implementation.
However, the high-speed differential encoder required for D-
QPSK modulator is not commercially available and it is a
non-trivial task to design such an encoder when the data rate
is higher than 1Gbps.
FPGAs are widely used in wireless communication and
optical communication. However, in wireless communication
ADCs and DACs are often employed for IF sampling and IF
signal generation [3] [4]. While in optical communication, due
to the high data rate, external MUX/DeMUX is used to reduce
the data rate in order to overcome the limitation of the FPGA
throughput [5].
The advancement in FPGAs with multi-Gbps IO interface
offers the opportunity to adopt the digital processing platform
978-1-4244-6404-3/10/$26.00 ©2010 IEEE
Yinggang Li‡ Herbert Zirath†‡
into the microwave application domain, without DAC and
ADC. In this paper, we demonstrate a newly designed 2.5Gbps
D-QPSK modulator and demodulator (modem) using a high-
speed encoder implemented in FPGA. The encoder itself is
not limited to 2.5Gbps and may be upgraded to well above
10Gbps if state-of-the-art FPGAs are used.
The D-QPSK modem is implemented in an Altera Stratix
II GX FPGA together with microwave components such as
mixers, phase shifter and 90-degree hybrids. However, this
kind of FPGA is targeted mainly for applications in optical
communication and to adopt it to the microwave link scenario,
some critical issues have to be solved for practical implemen-
tation. These issues will be discussed and some solutions will
be provided. In section II, the architecture of modem and the
approach of it implementation are presented. In section III,
some practical issues and its solutions are discussed. Last two
sections present the measurement result and conclusions.
II. M ODEM A RCHITECTURE AND I MPLEMENTATION
Fig. 1 shows the modem architecture and its test-bench.
The upper part of the figure sketches the architecture of
the modulator, while the lower part of the figure shows
the architecture of the demodulator. Data eye diagrams are
presented for the probing points indicated in the figure, which
will be discussed in detail in IV.
A. Modulator Architecture and its Implementation Issues
As shown in the upper part of Fig. 1, the modulator
architecture itself is simple. However, it is not straightforward
to implement the encoder when data rate goes up to 2.5Gbps.
There are several ways to design the encoder. The first one is
to use two 4-to-1 selector and two D-flipflops which provide
one bit delay, as sketched in Fig.2 (a). The encoder works well
for low data rate. However, for giga-bit rate, the extra delay
caused by the feedback routing paths is no longer negligible
and therefore, it is practically difficult in real implementation.
Instead of using D-flipflop devices, it may be considered to
use delay lines to provide the required one bit delay in the
encoder. Fig.2 (c) shows an example of a delay line designed
on typical microwave PCB. It occupies an area of 3x4 cm2
for 800ps delay at 10GHz. Four such delaylines are needed to
design the encoder (differential I and Q branches) and all four
This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE ICC 2010 proceedings
Fig. 1. The architecture of D-QPSK modem & its testbench
feedback paths have to be symmetric. This will be extremely
difficult, if not impossible, for PCB design.
The so-called feedforward encoder architecture is an alter-
native which does not require any feedback path [2]. However,
the encoding rules are different from what are given in Fig.1
and the corresponding demodulation of the D-QPSK signal is
not as straightforward as using the encoding rules based on
the feedback architecture.
Fig. 2. D-QPSK enocoding rules & the encoder implementation alternatives
B. FPGA-based Modulator Implementation
Driven by the need of optical algorithm implementation, two
leading FPGA vendors Xilinx and Altera both released new
series of products with transceivers supporting data rate up
to 11.5Gbps. The multi-Gbps IO ports enable the possibility
of directly adopting FPGA for application in the microwave
frequency range. There is even no need for using ADC & DAC
in the system, which makes the design really compact.
In previous section, we mentioned that it is hard to
implement 2.5Gbps D-QPSK modulator on a PCB using the
logic components. In the present work, an FPGA is used
to implement the D-QPSK encoder whose architecture is
shown in Fig.3. The multi-Gbps transceiver ports on FPGA
are connected to the configurable MUX and DeMUX. By
configuring the DeMUX as 1:16 serial to parallel receiver,
the 2.5Gbps input is converted into 16 bit bus with a data
rate of 156.25Mbps each. The encoded output is a function
of the last I & Q bits and current input bits. After examining
the coding rule in Fig. 2(b), two properties are observed:
• For D-QPSK, when the input I & Q bits are inverted, then
the encoded output are also inverted, for instance, input ’00’
produces Ik Qk while input ’11’ produces Ik Qk
• A series of input bits can be recognized as a series
of operation over the last IQ state. The IQ output after the
operation is a function F(·) of the last IQ state and a series
of 2n-bit binary inputs:
Ik+n Qk+n = F[Ik Qk , xk , xk+1 , ..., xk+2n−1 ]
Ik+n Qk+n = F[Ik Qk , xk , xk+1 , ..., xk+2n−1 ]
Ik+n Qk+n = F[Ik Qk , xk , xk+1 , ..., xk+2n−1 ]
Ik+n Qk+n ) = F[Ik Qk , xk , xk+1 , ..., xk+2n−1 ]
To realize the differential encoding, the built-in ROM is
adopted. 16 input bits along with 2 bits of last IQ state will
produce 16-bit output. To implement this with a single ROM
would lead to an 18-bit address ROM of 16-bit data, which
needs to be initialized by a 0.5MB LUT(look-up table).
This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE ICC 2010 proceedings
Fig. 3. The architecture of the FPGA-based D-QPSK encoder
This is however too large for the FPGA initialization file.
In addition, the width of the address line is just over the
capability of the FPGA in use.
Based on the properties mentioned above, and by adopting
the symmetry property, two ROMs of 16-bit address and
16-bit data, are used instead of a single large ROM. One
ROM is designed for IQ last symbol of ’00’. When the last
IQ symbol is ’11’ the inverted ROM output is taken. The
other ROM is designed for last symbol ’01’, similarly, the
inverted ROM output will provide the correct output for last
symbol ’10’.
A switch working at 156.25MHz serves to select the correct
output from each ROM, and put the data to the transmitter
through two channel 8:1 MUX. After the MUX, encoded I &
Q at 1.25Gbps waveform is present.
C. Demodulator Architecture and its Implementation
As shown in Fig.1, the D-QPSK signal is equally split into
two branches using a power splitter. Each branch will recover
one bit from each symbol. The benefit of using D-QPSK is that
the data can be recovered from the phase difference between
current symbol and the last symbol. To do so, the current
symbol is phase shifted 45 or -45 degree before comparing
with last symbol. By using a mixer along with a low pass
filter (LPF), the phase difference can be converted into binary
data, which are represented by different voltage levels. The
recovered two bits are combined into a single high speed data
stream through a 2:1 MUX, which is also implemented in
FPGA.
III. P RACTICAL P ROBLEMS IN M ODEM IMPLEMENTATION
A. Clock synchronization
One important issue is the clock synchronization. When
using an FPGA Multi-Giga Transceiver, a reference clock is
required to support the FPGA to sample the incoming data. It
is found that as long as the FPGA reference clock is provided
by a crystal oscillator, the bit error rate is high. This is because
the input data rate may not be exactly the multiples of the
oscillator frequency. No matter how small the difference is,
error eventually occurs after sufficient accumulation.
The original and the most common application for the
FPGAs with high data rate interface is to act as a protocol
interpreter, for instance, to transfer Giga-Ethernet data to
SONET data, or to add 8B/10B coding on the fiber or cable
Fig. 4. The Gigabit Transceiver structure
Fig. 5. The structure of the 2:1 MUX
communication. The main difference between these applica-
tions and microwave links is that all these applications have
a certain frame structure, allowing time slots to compensate
possible errors caused by the clock frequency difference. How-
ever, the microwave radios under development are supposed to
transport raw data constantly passing through the link without
framing. In this case, clock frequency difference, no matter
how small it is, would cause bit error during transmission.
The reason for the clock problem is related to the structure
of the Gigabit Transceiver Block (GXB), as Fig 4 shows.
For the receiver part, a crystal oscillator is used as reference
frequency source whose frequency could be 1/8 or 1/16 of the
data rate depending on the configuration in use. Before any
data are input, the internal PLL in the receiver is locked to the
crystal oscillator. As long as data are input, the PLL locks to a
frequency extracted from the input data by a Clock-and-Data
Recover (CDR) unit. The CDR output is fed into the DeMUX
unit to convert serial data to the parallel bus. Also, the CDR
will provide a output clock, which is 1/16 of the data rate. For
the transmitter, 16-bit bus data is converted to serial data in
the 16:1 MUX and fed to the output clocked by the CDR.
A preferred structure should be like in Fig.3, where the
GXB transmitter reference clock is recovered from the receiver
CDR. Another solution is to feed both the receiver and the
transmitter reference clock with the clock signal recovered
from the incoming data by an external CDR circuit.
B. Channel Alignment in MUX implementation
In addition to the clock issue discussed in previous section,
the channel alignment is another practical issue to consider.
Even if the I & Q paths are designed to be symmetric, there
is still possibility that one channel shifts a bit ahead of the
other due to clock jitter. The structure of the 2:1MUX is
shown in Fig. 5. Normally the channels are aligned using the
frame structure in the incoming data (protocol). However, the
This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE ICC 2010 proceedings

V. C ONCLUSION AND D ISCUSSION

Fig. 6. The spectrum of 1.25GBaud D-QPSK signal at 10GHz IF
input data are completely random in this application and it
is impossible to control the incoming data to the modulator.
Instead of framing the input data, we increase the ROM output
in Fig.3, and add extra information as synchronization header
which is used as the channel alignment information in the 2:1
MUX function.
IV. M EASUREMENT R ESULT
The setup of the test-bench is described in Fig.1. A pattern
generator is used as the data source. The modulator converts
the data into D-QPSK symbol at an IF of 10GHz. The IF signal
is directly fed back into the demodulator. An error detection
measurement system is adopted to verify the modem perfor-
mance. Our test shows that the FPGA output eye is widely
open and the modem can achieve error-free for transmitting
different PRBS (from PRBS-7 up to PRBS-23). The probe A
shows the I and Q channel output from the FPGA, and probe
C is the 2.5Gbps FPGA data output. As compared with the
eye diagram in probe B, the eye opening is wider after the
FPGA.
Fig.6 shows the spectrum of 1.25GBaud D-QPSK signal at
10GHz IF.
The detailed information of FPGA logic utilization is
showed in Table.I. The logic resource consumption is really
low, which enable the possibility of implement source coding
in the same FPGA. The total power consumption is only
around 5W, which is sufficiently low for the FPGA to be
included in a practical radio system.
Newly developed FPGAs with multi-Gbps IO interface
blocks open the door to adopt a digital processing platform
into microwave applications. In this work we demonstrated
that FPGAs provide a flexible solution for implementation of
2.5Gbps D-QPSK modem. The digital processing improves the
signal quality, as wider eyes are observed in the output signal.
The 2.5Gbps data rate is a result of the chosen demonstrator
but not an upper limit of the implementation. In future work
the data rate will be upgraded to 10Gbps using state-of-the-art
FPGAs. The focus will be on making use of the flexibility
offered by FPGAs to develop a relatively general-purpose
modem and implement as much as possible of the microwave
functions in the FPGA.
VI. ACKNOWLEDGEMENT
The authors appreciate the discussions with their colleagues
at Chalmers University of Technology and Ericsson Research
(Mölndal, Sweden), especially Ola Tagman for his design
of the delayline. Special thanks go to Daniel Stackenas, Ed
Garbett and Lena Engdahl from Altera for their technical
support.
R EFERENCES
[1] Sandri, J.M, Microwave backhaul as a business: taking the next step,
Microwave Magazine, IEEE, Volume 10, Issue 5, August 2009 pp.34 -
46
[2] Serbay, M. Wree, C. Rosenkranz, W, Implementation of differential
precoder for high-speed optical DQPSK transmission, Electronics
Letters, IEEE, 2004.
[3] Dyadyuk, V. Sevimli, O. Bunton, J. Pathikulangara, J. Stokes, L., A
6Gbps Millimeter Wave Wireless Link with 2.4 bit/Hz Spectral Efficiency,
Microwave Symposium, 2007. IEEE/MTT-S International
[4] Lee, D. Gray, A. Kang, E. Haiping Tsou Lay, N. Wai Fong Fisher, D. Hoy,
S. A gigabit-per-second Ka-band demonstration using a reconfigurable
FPGA modulator, Aerospace Conference, 2005 IEEE
[5] Song, H. Adamiecki, A. Winzer, P.J. Woodworth, C. Corteselli, S.
Raybon, G. Alcatel-Lucent, Holmdel, NJ, Multiplexing and DQPSK
Precoding of 10.7-Gbps Client Signals to 107 Gbps Using an FPGA ,
Optical Fiber communication,National Fiber Optic Engineers Conference,
2008. OFC,NFOEC 2008.

TABLE I
RESOURCE UTILIZATION OF FPGA

Combinational ALUTs 143 / 72,768 <1%

Dedicated logic registers 211 / 72,768 <1%
Total block memory bits 4,096 / 4,520,448 <1%
Total GXB Receiver Channels 3 / 12 25 %
Total GXB Transmitter Channels 3 / 12 25 %