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Optimizing Multi-Station Scheduling in

Consideration of Equipment Flexibility and Loading


Balance in Semiconductor Wafer Fabrication
Ya-Tang Chuang*, Yi-Hung Chang, Jr-Fong Dang, Ren-Chyi You, Steven Min Chang
Taiwan Semiconductor Manufacturing Company, Ltd.
Hsinchu, Taiwan, R.O.C.
*
ytjuang@tsmc.com

complex allocation problem considering thousands of


Abstract—This research studies multi-station
decisions [2] [5]. Usually, in wafer fabrication, the flow of
scheduling with flexible capacity and loading balance. In
each wafer contains 300-900 processing steps [8]. Processing
semiconductor manufacturing industry, QTime restriction
step depends upon complexity of electronic circuit (IC) layout.
is one of important factors, severely affecting throughput
Therefore, multi-station scheduling problem in high
since waiting time of wafer exceeding remaining QTime
technology wafer fabrication is extremely difficult.
leads to wafer scrap. A flexible capacity to produce
multiple processes provides additional capacity for each
In the real-world, there exists a situation where the
job, and reduces job waiting time. However, operators
flexible capacity can be applied to meet various process
have to allocate capacity manually while several decisions
demands. However, the setup time occurs once we intend to
would be considered. Therefore, with the consideration of
utilize the flexible capacity. It follows that how to efficiently
flexible capacity and QTime restrictions, resource
utilize the flexible capacity to meet the demand under the
allocation is extremely difficult. We model this problem by
QTime restrictions can be a challenge in the multi-station
applying mixed integer programming. The objective is to
scheduling problem. [3] [4]. In addition, the major criteria to
minimize wafer scrap as well as cycle time. In numerical
evaluate the success of semiconductor fabrication factories are
study, we apply our model to real production line, and the
target of throughput, line balance, and bottleneck equipment
results show that the proposed strategy provides
utilization [6]. In our paper, we apply the proposed standard
significant improvements in semiconductor wafer
criteria of lost rate, throughput and cycle time, to measure the
fabrication.
performance of our proposed model.

Keywords—Mixed Integer Programming; Multi-Station


To the best of our knowledge, none or very few papers
Scheduling
address the multi-station scheduling problem and consider the
flexible capacity and QTime restrictions. Our major purpose is
I. Introduction and Literature to provide a capacity allocation decision to minimize wafer
scrap and cycle time. We apply the mixed integer
Review
programming to solve for our scheduling problem.

In 300-mm semiconductor manufacturing factories, several


factors affect wafer fabrication performance such as II. Problem Description and Model
coordinated batching, super-hot lots, and QTime restrictions
Formulation
[1]. QTime restriction is a crucial factor in advanced
technology process since the QTime violations result in wafer
Taiwan Semiconductor Manufacturing Company (tsmc)
scrap cost occurring. To avoid QTime violations, operators
manufactures several technology electronic products in the
would have clever skills and abundant experience to solve a
same assembling line. The advanced technology leads to the

978-1-4673-5007-5/13/$31.00 ©2013 IEEE 41 ASMC 2013


short QTime. Furthermore, in a modern fab, the equipment is In this paper, our proposed model considers the flexible
supposed to produce several technology products. Then we capacity to avoid the QTime violations. Without lose of
intend to investigate the loading of the equipment. The generality, we let the flexible capacity be limited. In addition,
equipment can be categorized into two types: chamber and the setup time of the flexible capacity for each job is assumed
non-chamber. This paper is not limited itself to discuss the to be the same in each station. In the following, we introduce
chamber or non-chamber equipment scheduling. The features the mixed integer programming to solve the scheduling
of the tool families also results in the challenge of developing problem. The notations utilized in this study are listed as
the scheduling. We propose a scheduling model to manage the below.
equipment feature and to meet several customers’
requirements within their due dates. Indices

The semiconductor manufacturing production i The job i, i=1,2,. . ., m.


environment consists of several stations with different QTime j The equipment j, j = 1,2,. . ., n.
restrictions. For simplicity, we address the consecutive Qtime t The station t, t=1,…, T.
restriction throughout this paper. In addition, due to some
factors such as customers’ requirements, one may apply the Variables
flexible capacity to process lots. Note that the flexible capacity Oit The Qtime violation time of job i in station t
requires setup time and is with no restriction. We can depict
TS The makespan
the multi-station QTime scheduling problem as shown in
The difference among the total process time of each
Figure 1. In Figure 2, flexible capacity can produce several D
equipment
products of different technology in some stations.
sit The starting time of job i to be processed in station t
The binary variable to determine job i processed by
xijt
equipment j in station t or not
The binary variable to determine the flexible capacity
yit
to be applied to process job i in station t or not
eit The ending time of job i to be processed in station t

Parameters

ait
The weight of the variable Oit in station t
bi The setup time of flexible capacity to process job i
Figure 1. The flow of the consecutive QTime system
arrit The arrival time of job i in station t
qit The remaining Qtime of job i in station t
pit The requiring process time of job i in station t

Scheduling model

In this paper, we formulate the real-world semiconductor


production environment as following mathematical model.

m
Min ait O
i 1
it  TS  D (1)

Figure 2. Multi-production line with flexible capacity s.t.


sit  qit  Oit ,i  1,...,m, t  1,...,T . (2)
arrit  sit , i  1,...,m, t  1,...,T . (3)

42 ASMC 2013
n

x
j 1
ijt  1, i  1,...,m , t  1,...,T . (4)

sit  pit  bi yit  eit , i  1,...,m, t  1,...,T . (5)

The objective function (1) is to minimize the makespan


considering the QTime violation time and difference among
the total process time of each equipment D. As we can see, the
variable Qit of each job i in station t is with parameter ait
which would be greater than 1 due to the yield issue. We
utilize (2) to show the starting time of job i in station t would Figure 3: Trend chart of QTime violation ratio
be earlier than its remaining QTime qit to satisfy its quality
Figure 3 demonstrates that via our scheduling model, product
specification. Eq. (3) states that the starting time of job i in
scrap count reduces to zero after scheduling model developed.
station t would be later than its arrival time processed by the
previous station. In addition, job i is supposed to be processed
by an equipment j in station t as shown in (4). Eq. (5)
describes relation between the starting time and the ending
time once lot i is processed by the flexible capacity in station t.

III. Numerical Study


In practical application, this scheduling model is applied to
solve 300-mm wafer fabrication problem in a tsmc leading
factory. In addition, the required data to solve for the model is Figure 4: Trend chart of throughput and lost rate
prepared. The require process time of a job varying with
different recipes. We know that the requiring process time of Figure 4 shows that tool lost rate average improves 60%
each job can be obtained by the historical data and assists us to and daily throughput increases additional 70% during one
predict the arrival time of the job. The QTime is defined by month data collection. We define the lost rate as the shortness
process integration department. Therefore, we are able to of the targets.
know the remaining QTime of each job based on the job
waiting time and its QTime specification. We collect around
one month data before scheduling model released. Then we
utilize the data to be the baseline to compare with the
improving results derived via our scheduling model. We apply
the commercial software to solve for the scheduling problem.

In the following, we would introduce the resulting


outcomes derived by our scheduling model. We rearrange the
data for comparative purpose. We find that our scheduling
model makes following major contributions. First one is to Figure 5: Trend chart of cycle time
eliminate wafer scrap in SPUT, which is abbreviated from
In the practical area, the cycle time also improves 19% as
sputter area. Second, this scheduling improves operators’ work
shown in Figure 5. To summarize the resulting outcomes, our
efficiency without manual assignments of lots. The scheduling
scheduling system improves the productivity efficiency.
model provides precise automatic dispatch result.

43 ASMC 2013
[2] DAL de Pablo, "On Scheduling Models: An Overview", Computers &
IV. Conclusion Industrial Engineering, PP. 153-158, 2009
[3] B. Pickett and M. Zuniga ", "Modeling, scheduling, and dispatching in
This paper studies a multi-station scheduling problem in the dynamic environment of semiconductor manufacturing at FASL,
Japan", Advanced Semiconductor Manufacturing, IEEE/SEMI
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balance. We focus on the problem of resource allocation, [4] Klaus Altendorfer, Bernhard Kabelka, and Wolfgang Stöcher, "A new
dispatching rule for optimizing machine utilization at a semiconductor
where our scheduling model is able to efficiently assign job to test field", Advanced Semiconductor Manufacturing, IEEE/SEMI
the equipment. The performance greatly improves our Conference and Workshop – ASMC, PP. 188-193, 2007
[5] Vasu Subbiah and J. Bodenstab, "Application of real-time expert
production system and can be extended to advanced systems in semiconductor manufacturing", Advanced Semiconductor
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Future research is planned as follows. The proposed model [6] Ting-Kai Hwang and Shi-Chung Chang “Design of a Lagrangian
Relaxation-Based Hierarchical Production Scheduling Environment for
would take the uncertainty of customers’ products and Semiconductor Wafer Fabrication”, IEEE Transactions on Robotics and
reliability of the equipment into consideration Automation, Vol. 19, No. 4, PP. 566-578, August 2003
[7] M. Ham “Integer programming-based real-time dispatching (i-RTD)
heuristic for wet-etch station at wafer fabrication”, International Journal
References [8]
of Production Research, Vol. 50, No. 10, PP. 2809-2822, May 2012.
Lars Mönch ·JohnW. Fowler ·Stéphane Dauzère-Pérès ·Scott J. Mason ·
Oliver Rose “A survey of problems, solution techniques, and future
[1] R. Bixby, R. Burda, and D. Miller, "Short-Interval Detailed Production challenges in scheduling semiconductor manufacturing operations” ,
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