Generate 3-Phase Sinusoidal PWM Signal with Variable Frequency

GENERATION OF 3 PHASE SINUSOIDAL PWM SIGNAL WITH VARIABLE
FREQUENCY BY USING LOW COST MICROCONTROLLER
by
S. M. Mohaiminul Islam
ID: 0520145
A Senior Project Report Presented in Partial Fulfillment

of the Requirements for the Degree
Bachelor of Science
in
Electrical & Electronics Engineering
INDEPENDENT UNIVERSITY, BANGLADESH

May 2009
Senior Project
GENERATION OF 3 PHASE SINUSOIDAL PWM SIGNAL WITH VARIABLE

FREQUENCY BY USING LOW COST MICROCONTROLLER
by
S. M. Mohaiminul Islam
ID: 0520145
has been approved

May 2009
Dr. Khosru M. Salim

Assistant Professor
School of Engineering and Computer Science
Independent University, Bangladesh
ABSTRACT
This report represents generation of three phase sinusoidal PWM (Pulse Width
Modulation) signal with variable frequency by using low cost microcontroller.
PIC18F4431 microcontroller is used for generating three phase sinusoidal PWM
signal with variable frequency. When the pulse width of a signal is changed
according to the amplitude of a sine wave is called Sinusoidal PWM signals. The
frequency will be varied depending on the pick value of PWM time base timer. Here
the pick value of PWM time base timer will be depending on ADC (Analog to Digital
Conversion) value. The ADC output is 10-bit. The PWM module also generates Dead
time. The output will be six PWM signals; three signals are in independent mode and
other three signals are in complementary mode.
iii
To my parents
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ACKNOWLEDGMENTS
We wish to thank my supervisor Dr. Khosru Mohammad Salim for his
valuable suggestions, guidance and constant support throughout this project. I am also
grateful to Mr. Gazi Mohammad Sharif and Khaled Mahmud Sujan for various
discussions among us about this work.
We wish to express our parents and university for providing all kinds of financial
support to carry out this project.
Finally, we would like to thank my class mates, particularly Hasan Mahmood and Mr.
Md. Abdul Malek, for their cooperation and interest.
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TABLE OF CONTENTS
Page
LIST OF TABLES…….……………………….……………………………………..ix
LIST OF FIGURES….………………………………………………………………...x
CHAPTER
1 GENERAL INTRODUCTION………………………………………………..... 1
1.1. Overview…………………………………………………………………. 1
1.2. Background……………………………………………………………… 3
1.3. Objective…………………………………………………………………. 3
1.4. Outline of Project……………………………………………………….... 4
2 SINUSOIDAL PWM AND HARWARE DESCRIPTION OF THE PWM
MODULE OF PIC18F4431…………………………………………………...... 5
2.1. Introduction……………………………………………………………... 5
2.2. PWM…………………………………………………………………….. 5
2.2.1. Natural Sampling PWM……………………………………… 6
2.2.2. Regular Sampling PWM…………………………………….... 8
2.2.3. Harmonic injection PWM (HPWM) technique……………… 11
2.3. Microchip PIC18F4431 Microcontroller………………………............... 14
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2.4. Generation Method of Sinusoidal PWM Waveform…………………… 16
2.4.1. PCPWM Module………………………………………………. 16
2.4.1.1. Control Registers…………………………………... 20
2.4.1.2. Module Functionality……………………………… 21
2.4.1.3. PWM Time Base…………………………………... 22
2.4.1.4. Free Running Mode………………………………... 28
2.4.1.5. PWM Time Base Prescaler………………………… 28
2.4.1.6. PWM Time Base Postscaler……………………….. 29
2.4.1.7. PWM Time Base Interrupts……………………….. 30
2.4.1.8. Interrupts in Free Running Mode………………….. 30
2.4.1.9. PWM Period……………………………………….. 30
2.4.1.10. PWM Duty Cycle………………………………….. 32
2.4.1.11. PWM Duty Cycle Registers……………………….. 32
2.4.1.12. Duty Cycle Register Buffers………………………. 33
2.4.1.13. Complementary PWM Operation………………….. 34
2.4.1.14. Dead Time Generators…………………………….. 35
3 PWM IMPLEMENTATION USING VARIABLE FREQUENCY……………. 39
vii

3.1. Introduction……………………………………………………………… 39
3.2. Generation Method of ADC…………………………………………….. 40
3.2.1. HSADC Module………………………………………………….. 42
3.2.2. Configuring the A/D converter…………………………………... 50
3.2.3. A/D Result Register……………………………………………... 52
3.3. Overview Flowchart of the Program in Generating 3 phase Sinusoidal
PWM Signal with Variable Frequency…………………………………… 53
3.4. Flowchart of the Main Function’s Program for generating 3 phase
sinusoidal PWM signal with variable frequency………………………… 54
4 RESULTS AND DISCUSSION…………………………………………………. 55
4.1. 120 sampling value use by MATLAB………………………………….... 55
4.2. PCPWM Output…………………………………………………………... 59
4.3. ADC……………………………………………………………………….. 62
4.4. Variable Frequency of Three phase PCPWM Signals output…………... 63
5 CONCLUSION AND FUTURE WORKS……………………………………… 66
5.1. Conclusion………………………………………………………………. 66
5.2. Future Works…………………………………………………………….. 66
REFERENCES…………………………………………………………………....... 67
viii

APPENDIX
A PROGRAM FOR PIC18F4431 MICROCONTROLLER………………………. 69
B PROGRAM FOR GENERATING 120 SAMPLING VALUE OF SINE WAVE
BY MATLAB………………………………………………………………….. 95
C PROGRAM FOR GENERATING SAW TOOTH BY MATLAB…………….. 96
ix

LIST OF TABLES
Table Page
2.1 Minimum PWM Frequency……………………………………. 29
3.1 Auto-Conversion Sequence Configurations…………………… 50
x

LIST OF FIGURES
Figure Page
1.1 Block Diagram of PIC18F4431 Microcontroller Voltage
Source Inverter………………………………………………… 2
2.1 Natural sampling PWM generation…………………………….. 7
2.2 Symmetrical and asymmetrical regular sampled PWM……….. 9
2.3 Generation of PWM waveform using regular symmetric
sampling………………………………………………………. 10
2.4 3rd harmonic injection modulation…………………………. 13
2.5 Block diagram of PIC18F4431 Microcontroller…………….. 15
2.6 Power Control PWM Module Block Diagram………………… 18
2.7 PWM Module Block Diagram, One Output pair,
Complementary Mode………………………………………… 19
2.8 PWM Module Block Diagram, One Output Pair, Independent
Mode…………………………………………………………… 19
2.9 PWM Time Base Block Diagram…………………………… 23
2.10 PWM Period Buffer Updates in Free Running Count Mode…. 31
2.11 Duty Cycle Comparison………………………………………. 33
2.12 Edge-Aligned PWM……………………………………………. 34
2.13 Typical Load for Complementary PWM Outputs……………… 35
2.14 Dead Time Control Unit Block Diagram for One PWM Output
Pair…………………………………………………………… 36
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2.15 Dead Time Insertion for Complementary PWM……………… 37
3.1 A/D Block Diagram…………………………………………… 41
3.2 A/D Result Justification………………………………………. 52
4.1 The sine wave of 120 sampling value from MATLAB……….. 55
4.2 The output of sine wave from MATLAB……………………. 58
4.3 How the sine waves are sampled by MATLAB……………… 58
4.4 Figure of saw tooth generation ……………………………….. 59
4.5 Simulation result of PWM signal which have also a dead time. 60
4.6 Pin diagram of the Microcontroller………………………….. 60
4.7 Figure of the PWM signal in PC base Oscilloscope…………… 61
4.8 Figure of ADC result’s for Test………………………………. 62
4.9 The output of the variable frequency of Three phase PCPWM
Signals…………………………………………………………. 63
4.10 Ch2-PWM0 and Ch1-PWM2………………………………… 64
4.11 Ch2-PWM4 and Ch1-PWM2……………………………….... 64
4.12 Single phase Independent and complementary mode……… 64
4.13 PWM2-PWM3………………………………………………… 65
xii

CHAPTER 1
GENERAL INTRODUCTION
1.1. Overview
In many Instant Power Supply (IPS) or Uninterrupted Power Supply (UPS) use
microcontroller for creating Sinusoidal Pulse Width Modulation signal (SPWM)
which will not impact any other communication device and which is following IEEE
rules. Variable Frequency (VF) control using Sine PWM is implemented using for
Voltage Source Inverter controlled by PIC18F4431 microcontroller. Its popularity is
mainly due to its easy implementation and minimum online computational
requirements [8]. The SPWM (Sine PWM) is algorithm is unable to fully utilize the
available DC bus supply voltage to the Voltage Source Inverter (VSI). The generated
line-to-line voltage is less than 90% of VDC in the linear operating region. And this
algorithm gives more Total Harmonic Distortion due to the use of Sine PWM [7], [8],
[12].
The state of the art in motor control provides an adjustable voltage and frequency
to the terminals of the motor through a pulse width modulated voltage source inverter
drive. As the Power devices change switching states, a dead time exists. Although is
short, it causes deviations from the desired fundamental output voltage. While each
deviation does not appreciably affect the fundamental voltage, the accumulated
deviations result in reduced fundamental output voltage, distorted machine currents,
and torque pulsations. To compensate for the dead time in PWM signals, the industry
2

has investigated this problem and has tried various methods of correction. And also in
PIC18F4431 have Dead time generator module [6].
Induction motors are the most widely used motors for appliances, industrial
control, and automation; hence, they are often called the workhorse of the motion
industry. They are robust, reliable, and durable. When power is supplied to an
induction motor at the recommended specifications, it runs at its rated speed.
However, many applications need variable speed operations. For example, mechanical
gear systems were used to obtain variable speed. These electronics not only control
the motor’s speed but can improve the motor’s dynamic and steady state
characteristics. In addition, electronics can reduce the system’s average power
consumption and noise generation of the motor. Variable Frequency (V/F) control can
be implemented by using low cost PIC18F4431 microcontroller, rather than using
costly digital signal processors (DSPs) [10]. In Figure 1. 1. showing that the block
diagram of PIC18F4431 Microcontroller Voltage Source Inverter. This will be
implemented.
Figure 1. 1: Block Diagram of PIC18F4431 Microcontroller Voltage Source
Inverter [8].
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1.2. Background
Before 2009, In Bangladesh for generation PWM signal uses the Microcontroller
of PIC16F877A. But in PIC16F877A the generation of 3 phase PWM signal is very
difficult because there are only three Capture/Compare/PWM modules. For this
reason one is to goes for comparing the value of TIMER2 and what will be the highest
value of TIMER2, and second, third comparing is going for compare the value of
TIMER2 and the other sinusoidal sampling value. For this reason, In PIC16F877A
microcontroller can generate only 2 phase PWM signals. But in the means time world
is going so fast. In 2004, the Microchip released the PIC18F4431 microcontroller for
controlling 3-phase AC Induction motors which were fulfilling our objectives of the
research. In PIC18F4431 microcontroller have Capture/Compare/PWM modules and
also Power Control Pulse Width Modulation (PCPWM) Module. In
Capture/Compare/PWM module can generate only 2 PWM signals but in PCPWM
module can generate 8 PWM signals. And our objective is to generate 3 phase PWM
signal for controlling the AC Induction Motor. For controlling speed of the AC
Induction Motor we can make the electric vehicle. And also if we want to control the
3-phase AC Induction Motor we need 3-phase Inverter Bridge. So, if we want to make
the 3-phase Inverter Bridge we need 6 MOSFETs. For 6 MOSFETS we need 6 PWM
pulses. So, we can easily generate the 6 PWM signals using by single microcontroller
which is really a lost and this microcontroller have good efficiency.
1.3. Objective
The main objective of the project is to generate the 3-phase Sinusoidal PWM
(Pulse Width Modulation) signal with variable frequency by using low cost
microcontroller.
4

1.4. Outline of Project
This project divided in to three main chapters. In the second chapter the
theoretical background of the PWM and PCPWM (Power Controlled PWM) module
for PIC18F4431 microcontroller. And how can we generate the PWM signal and
Dead time.
In the second chapter have HSADC (High Speed Analog-to-Digital
Conversion) module and the process of conversion Analog to Digital signal. And the
next chapter has results and discussion of our project work. In that chapter we have
showed that how can we generate 120 sampling value of Sinusoidal wave using by
MATLAB software and Simulation result of PWM (Pulse Width Modulation) signal
by MPLAB IDE(Integrated Development Environment) v 8.20 software. And Also I
have showed that the practical result which I have taken from storage oscilloscope.
And the last chapter is conclusion and future works.

CHAPTER 2
SINUSOIDAL PWM AND HARWARE DESCRIPTION OF THE
PWM MODULE OF PIC18F4431
2.1. Introduction
In recent year almost all the power-electronics products are microprocessor
controlled. The main advantage of using microprocessor is that it reduces the complex
control hardware where the control functions can be changed as many times as it is
required without extra hardware. Furthermore, it offers the possibility of improved
reliability and flexibility.
In this work, a 40-pin microcontroller (PIC18F4431) is used for the generation
the 3-phase PWM pulses and implementation of the controller strategy. The hardware
specifications show that this MICRO single–chip microcontroller is more than
sufficient to fulfill the requirements of generating three phases PWM signal. The
regular sampling PWM strategy is implemented digitally.
2.2. PWM
In power electronics, pulse width modulation (PWM) is an operation
performed on “raw” voltage and current waveforms to shape their spectra in a way
beneficial to the application under consideration. Spectra shaping typically mean the
creation of a “dead band” between wanted and unwanted spectral components. For a
given switching frequency it is desirable that the band be as wide as possible.
However, in addition to the importance of spectra shaping, the main advantage of

6

pulse width modulation is that it allows linear amplitude control of the output voltage
and current of the inverter.
The PWM has several disadvantages. It attenuates the unwanted fundamental
component of the PWM waveform. Higher switching frequency causes greater losses
and stresses on the associated switching devices and therefore reduces the life time of
those devices. However, advantages of PWM outweigh the respective disadvantages;
a considerable research effort has gone into minimize those disadvantages. As a result
several specific PWM techniques have been developed. Three of them related to this
work are discussed in the following sections [9].
2.2.1. Natural Sampling PWM
The principle of generation a PWM pattern using this method is illustrated in
Figure 2. 1.
7

Figure 2. 1: Natural sampling PWM generation [9].
A triangular carrier is compared to the sinusoidal modulating wave to determine the
switching instants. The points of intersection of these two waves determine the instant
of switching. Although this process appears to be simple, the mathematical
representation of the pulse width only can be solved using Bessel function series or
numerical techniques.
Natural sampling can only be readily implemented using analogue methods.
Modulation index and modulation ratio can be express as follows:

8

Equation2. 1:
Amplitude of the carrier wave Vp carrier

Modulation index = =
Amplitude of the mod ulating wave Vp mod
Equation2. 2:
Carrier frequency f
Modulation ratio = = c
Modulating frequency f m
Where, Vp carrier and V p mod represent the amplitudes, f c and f m represents the
frequencies of carrier wave and modulating wave respectively [9].
2.2.2. Regular Sampling PWM
Regular sample PWM inverter control was first proposed in 1975. It is recognized to
have certain advantages when implemented using digital or microprocessor technique.
Two types of modulation, ‘symmetric’ and ‘asymmetric’ are possible. They are
shown in Figure 2. 2. In asymmetric modulation, the leading and trailing edges of
each pulse are determined using two samples of the modulating wave, and therefore
each edge is modulated by a different amount. In symmetrical modulation, only one
sample is used to determine the pulse width, and therefore both edges of the pulse
modulated equally. The generation of single pulse, using the symmetric regular-
sampling process, is illustrated in Figure 2. 2.

9

Figure 2. 2: Symmetrical and asymmetrical regular sampled PWM[9].
Symmetrical sampling
Asymmetrical sampling
The symmetrical PWM technique, which has been implemented in this work,
is explained in Figure 2. 3. In this process, the amplitude of the modulating signal a
at the sampling instant T1 is stored by a sampled-and-hold circuit (operated at the
carrier frequency), and is maintained at a constant level during the inter-sampled

10

period T1 and T4 until the next sample is taken. This produces a sampled-hold or
amplitude modulated version of the modulating signal b , which, when compared with
the carrier signal c , defines the point of intersection used to determine the switching
instants T2 and T3 of the width modulated pulse d . As a result of this process, the
modulating wave has constant amplitude while each sample is being taken.
Figure 2. 3: Generation of PWM waveform using regular symmetric sampling
[9]
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Consequently the widths of the pulses are proportional to the amplitude of the
modulating wave at uniformly placed sampling times. It is therefore an important
characteristic of regular sampling that the sampling positions and sampled values can
be defined unambiguously, such that the pulses produced are predictable both in
width and position. It should be noted that this is not the case in the natural-sample
process. Because of this ability to define precisely the pulse configuration, it is now
possible to derive a simple trigonometric function to calculate the pulse widths. This
is described in appendix A. With reference to Figure 2. 3, if M represents the
modulation index and ω m represents the angular frequency, then width of a pulse t wp
at time instant T1 may be defined as [9]:
Equation2. 3:
t pw =
T
{1 + M sin (ω m T1 )}
2
2.2.3. Harmonic injection PWM (HPWM) technique
This improved PWM technique using 3rd harmonic injection is explained with the aid
of Figure 2. 4. The main feature of an improved PWM technique includes the
derivation of switching points, the resulting AC and DC term gains, the frequency
spectra, the harmonic distortion, and finally, the degree of difficulty of hardware
implementation of the technique (HIPWM) is better than that of the original
sinusoidal PWM technique. In the third harmonic injection method the modulating
signal is generated by injection third harmonics to the fundamental sine wave as
shown in Figure 2. 4. This results in flat-topped waveform of the modulating wave

12

and reduces the amount of over modulation. The analytical expression of the
modulating signal is given as:
Equation2. 4:
v r = 1.15 sin ωt + 0.19 sin(3ωt )s
This equation shows that 17 percent third harmonic component is added to the
original sine reference wave. An improved result is obtained by injecting additional
9th harmonics of the fundamental in the respective modulating waveform. The
resulting flat-topped waveform again allows over-modulation; improving even
furthers the frequency spectra of the AC term and DC term waveforms. The analytical
expression of the modulating signal is given as:
Equation2. 5:
v r = 1.15 sin ωt + 0.27 sin 3ωt − 0.029 sin 9ωt

13

Figure 2. 4: 3rd harmonic injection modulation[9].
It should be noted that the injection of 3rd and 9th harmonics will not affect the quality
of the output voltage, because the output of the three-phase inverter does not contain
14

triplen harmonics as shown in Appendix A. The hardware implementation of this
technique is as simple as the original sinusoidal PWM technique [9].
2.3. Microchip PIC18F4431 Microcontroller
The PWM generation and the control strategy is performed by a microcontroller, the
PIC18F4431 from Microchip [6]. The block diagram that describes the main features
of the chip is shown in Figure 2. 1. On chip peripherals such as Timers, High Speed
Analogue to Digital Converter (HSADC), PCPWM module (Power Control PWM
module) and CCP module (Capture/Compare/PWM module) make the interfacing
task much easier and more reliable.

15

Figure 2. 5: Block diagram of PIC18F4431 Microcontroller [6].
The main features of PIC18F4431 and on-chip peripherals are given as follows [6]:
• Operating Frequency is DC – 40 MHz.
• Program Memory is 16384 bytes.

16

• Program Memory 8192 Instructions.
• Data Memory is 768 bytes.
• Data EEPROM Memory is 256 bytes.
• 34 Interrupt sources.
• Pots A, B, C, D, and E are I/O ports.
• 4 Timers.
• 2 Capture/Compare/PWM modules.
• 8 channels of 14-bit Power Control PWM.
• 1QEI or 3× IC Motion Feedback module (Input Capture/Quadrature Encoder
Interface).
• SSP Enhanced USART Serial Communications.
• 9 Input Channels of 10-bit High-Speed Analog-to-Digital Converter module.
• POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST),
MCLR (optional), WDT are Resets (and Delays).
• Programmable Low-voltage Detection.
• Programmable Brown-out Reset option.
• 75 Instructions set.
• 40-pin DIP, 44-pin TQFP and 44-pin QFN are packages.
2.4. Generation Method of Sinusoidal PWM Waveform
2.4.1. PCPWM Module
PCPWM Module means Power Control PWM module. The Power Control PWM
module simplifies the task of generating multiple, synchronized pulse width
modulated (PWM) outputs for use in the control of motor controllers and power
17

conversion applications. In particular, the following power and motion control
applications are supported by the PWM module [6]:
• Three-phase and Single-phase AC Induction Motors [4]
• Switched Reluctance Motors
• Brushless DC (BLDC) Motors
• Uninterruptable Power Supplies (UPS)
• Multiple DC Brush Motors
The PWM module has the following features:
• Up to eight PWM I/O pins with four duty cycle generators. Pins can be paired
to get a complete half-bridge control.
• Up to 14-bit resolution, depending upon the PWM period.
• “On-the-fly” PWM frequency changes.
• Edge- and center-aligned Output modes.
• Single-pulse Generation mode.
• Programmable dead time control between paired PWMs.
• Interrupt support for asymmetrical updates in Center-aligned mode.
• Output override for Electrically Commutated Motor (ECM) operation; for
example, BLDC.
• Special Event comparator for scheduling other peripheral events.
• PWM outputs disable feature sets PWM outputs to their inactive state when in
Debug mode.
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The Power Control PWM module supports four PWM generators and eight channels
on PIC18F4431 devices. A simplified block diagram of the module is shown in Figure
2. 6. Figure 2. 7 and Figure 2. 8 show how the module hardware is configured for
each PWM output pair for the complementary and independent output modes.
Figure 2. 6: Power Control PWM Module Block Diagram [6].

19

Figure 2. 7: PWM Module Block Diagram, One Output pair, Complementary
Mode1
Figure 2. 8: PWM Module Block Diagram, One Output Pair, Independent Mode
This module contains four duty-cycle generators, numbered 0 through 3. The module
has eight PWM output pins, numbered 0 through 7. The eight PWM outputs are

1
In the complementary mode, the even channel cannot be forced active by a fault or override event
when the odd channel is active. The even channel is always the complement of the odd channel and is
inactive, with dead time inserted, before the odd channel is driven to its active state.
20

grouped into output pairs of even and odd numbered outputs. In complementary
modes, the even PWM pins must always be the complement of the corresponding odd
PWM pin. For example, PWM0 will be the complement of PWM1, PWM2 will be the
complement of PWM3, and so on. The dead time generator inserts an “off” period
called “dead time” between the going off of one pin to the going on of the
complementary pin of the paired pins. This is to prevent damage to the power
switching devices that will be connected to the PWM output pins.
The time base for the PWM module is provided by its own 12-bit timer, which also
incorporates selectable prescaler and postscaler options [6].
2.4.1.1. Control Registers
The operation of the PWM module is controlled by a total of 22 registers. Eight of
these are used to configure the features of the module:
• PWM Timer Control register 0 (PTCON0)
• PWM Timer Control register 1 (PTCON1)
• PWM Control register 0 (PWMCON0)
• PWM Control register 1 (PWMCON1)
• Dead Time Control register (DTCON)
• Output Override Control register (OVDCOND)
• Output State register (OVDCONS)
• Fault Configuration register (FLTCONFIG)
There are also 14 registers that are configured as seven register pairs of 16 bits. These
are used for the configuration values of specific features. They are:
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• PWM Time Base Registers (PTMRH and PTMRL)
• PWM Period Registers (PTPERH and PTPERL)
• PWM Special Event Compare Registers (SEVTCMPH and SEVTCMPL)
• PWM Duty Cycle #0 Registers (PDC0H and PDC0L)
All of these register pairs are double-buffered [6].
2.4.1.2. Module Functionality
The PWM module supports several modes of operation that are beneficial for specific
power and motor control applications. Each mode of operation is described in
subsequent sections.
The PWM module is composed of several functional blocks. The operation of each is
explained separately in relation to the several modes of operation [6]:
• PWM Time Base
• PWM Time Base Interrupts
• PWM Period
• PWM Duty Cycle
• Dead Time Generators
• PWM Output Overrides
• PWM Fault Inputs
• PWM Special Event Trigger

22

2.4.1.3. PWM Time Base
The PWM time base is provided by a 12-bit timer with prescaler and postscaler
functions. A simplified block diagram of the PWM time base is shown in Figure 2. 9.
The PWM time base is configured through the PTCON0 and PTCON1 registers. The
time base is enabled or disabled by respectively setting or clearing the PTEN bit in the
PTCON1 register.2
The PWM time base can be for four different modes of operation:
• Free Running mode
• Single-shot mode
• Continuous Up/Down Count mode
• Continuous Up/Down Count mode with interrupts for double updates
These four modes are selected by the PTMOD1:PTMOD0 bits in the PTCON0
register. The Free Running mode produces edge-aligned PWM generation. The
up/down counting modes produce centre-aligned PWM generation. The Single-shot
mode allows the PWM module to support pulse control of certain electronically
commutated motors (ECMs) and produces edge-aligned operation [6].

2
The PTMR register pair (PTMRL:PTMRH) is not cleared when the PTEN bit is cleared in software.
23

Figure 2. 9: PWM Time Base Block Diagram [6].
PTCON0: PWM Timer Control Register 0
R/W R/W R/W R/W R/W R/W R/W R/W
PTOPS3 PTOPS2 PTOPS1 PTOPS0 PTCKPS1 PTCKPS0 PTMOD1 PTMOD0
bit 7 bit 0
bit 7-4 PTOPS3:PTOPS0: PWM Time Base Output Postscale Select bits
0000 =1:1 Postscale
0001 =1:2 Postscale

24

.
1111 =1:16 Postscale
bit 3-2 PTCKPS1: PTCKPS0: PWM Time Base Input Clock Prescale Select bits
Fosc
00 =PWM time base input clock is (1:1 prescale)
4
Fosc
16
Fosc
64
Fosc
256
bit 1-0 PTMOD1:PTMOD0: PWM Time Base Mode Select bits
11 =PWM time base operates in a Continuous Up/Down mode with interrupts
for double PWM updates.
10 =PWM time base operates in a Continuous Up/Down Counting mode.
01 =PWM time base configured for Single-shot mode.
00 =PWM time base operates in a Free Running mode
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = bit is set ‘0’ = bit is x = bit is unknown
cleared
25

PTCON1: PWM Timer Control Register 1
R/W R U U U U U U
PTEN PTDIR - - - - - -
bit 7 bit 0
bit 7 PTEN: PWM Time Base Timer Enable bit
1 = PWM time base is ON
0 = PWM time base is OFF
bit 6 PTDIR: PWM Time Base Count Direction Status bit
1 = PWM time base counts down.
0 = PWM time base counts up.
bit 5-0 Unimplemented: Read as ‘0’.
Legend:
-n = Value at ‘1’ = bit is set ‘0’ = bit is x = bit is unknown
POR cleared
PWMCON0: PWM Control Register 0
U R/W R/W R/W R/W R/W R/W R/W
- PWMEN2 PWMEN1 PWMEN0 PMOD3 PMOD2 PMOD1 PMOD0
bit 7 bit 0
bit 7 Unimplemented: Read as ‘0’.
bit 6-4 PWMEN2: PWMEN0: PWM Module Enable bits
111 =All odd PWM I/O pins enabled for PWM output.
110 =PWM1, PWM3 pins enabled for PWM output.

26

101 =All PWM I/O pins enabled for PWM output.
100 =PWM0, PWM1, PWM2, PWM3, PWM4 and PWM5 pins enabled for
PWM output.
011 =PWM0, PWM1, PWM2 and PWM3 I/O pins enabled for PWM output.
010 =PWM0 and PWM1 pins enabled for PWM output.
001 =PWM1 pin is enabled for PWM output.
000 =PWM module disabled. All PWM I/O pins are general purpose I/O.
bit 3-0 PMOD3:PMOD0: PWM Output Pair Mode bits
For PMOD0:
1 = PWM I/O pin pair (PWM0, PWM1) is in the Independent mode.
0 = PWM I/O pin pair (PWM0, PWM1) is in the Complementary mode.
For PMOD1:
For PMOD2:
For PMOD3:
0 = PWM I/O pin pair (PWM6, PWM7) is in the Complementary mode.34
Legend:

3
Reset condition of PWMEN bits depends on PWMPIN device configuration bit.
4
When PWMEN:PWMEN0 = 101 then PWM[7:0] outputs are enabled. When PWMEN:PWMEN0 =
111 then PWM outputs 1, 3, 5 and 7 are enabled.
27

-n = Value at POR ‘1’ = bit is set ‘0’ = bit is cleared x = bit is unknown
PWMCON1: PWM Control Register 1
R/W R/W R/W R/W R/W U R/W R/W
SEVOPS3 SEVOPS2 SEVOPS1 SEVOPS0 SEVTDIR - UDIS OSYNC
bit 7 bit 0
bit 7-4 SEVOPS3: SEVOPS0: PWM Special Event Trigger Output Postscale Select
bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
1111 =1:16 Postscale
bit 3 SEVTDIR: Special Event Trigger Time Base Direction bit
1 =A special event trigger will occur when the PWM time base is counting
downwards.
0 =A special event trigger will occur when the PWM time base is counting
upwards.
bit 2 Unimplemented: Read as ‘0’.
bit 1 UDIS: PWM Update Disable bit
1 = Updates from duty cycle and period buffer registers are disabled.
0 = Updates from duty cycle and period buffer registers are enabled.
bit 0 OSYNC: PWM Output Override Synchronization bit

28

1 = Output overrides via the OVDCON register are synchronized to the
PWM time base.
0 = Output overrides via the OVDCON register are asynchronous.
Legend:
-n = Value at POR ‘1’ = bit is set ‘0’ = bit is x = bit is unknown
cleared
2.4.1.4. Free Running Mode
In the Free Running mode, the PWM time base (PTMRL and PTMRH) will be
begin counting upwards until the value in the Time Base Period Register, PTPER
(PTPER and PTPERH), is matched. The PTMR registers will be reset on the
following input clock edge and the time base will continue counting upwards as long
as the PTEN bit remains set [6].
2.4.1.5. PWM Time Base Prescaler
Fosc
The input clock to PTMR ( ) has prescaler options of 1:1, 1:4, 1:16 or 1:64.
4
These are selected by control bits PTCKPS<1:0> in the PTCON0 register. The
prescaler counter is cleared when any of the following occurs:
• Write to the PTMR register
• Write to the PTCON (PTCON0 or PTCON1) register
• Any device Reset5

5
The PTMR register is not cleared when PTCON is written.
29

Table.2. 1 shows the minimum PWM frequencies that can be generated with the
PWM time base and the prescaler. An operating frequency of 40 MHz ( FCYC = 10
MHz) and PTPER = 0 × FFF is assumed in the table. The PWM module must be
capable of generating PWM signals at the line frequency (50 Hz or 60 Hz) for certain
power control applications [6].
Table.2. 1: Minimum PWM Frequency
Minimum PWM Frequencies vs. Prescaler Value for FCYC = 10 MIPS, (PTPER =
0FFFh)
Prescale PWM Frequency Edge- PWM Frequency Center-
aligned aligned
1:1 2441 Hz 1221 Hz
1:4 610 Hz 305 Hz
1:16 153 Hz 76 Hz
1:64 38 Hz 19 Hz
2.4.1.6. PWM Time Base Postscaler
The match output of PTMR can optionally be post-scaled through a 4-bit post-
scaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to
generate an interrupt. The postscaler counter is cleared when any of the following
occurs:
• Write to the PTMR register
• Write to the PTCON register
• Any device Reset

30

The PTMR register is not cleared when PTCON is written [6].
2.4.1.7. PWM Time Base Interrupts
The PWM timer can generate interrupts based on the modes of operation
selected by PTMOD<1:0> bits and the postscaler bits (PTOPS<3:0>) [6].
2.4.1.8. Interrupts in Free Running Mode
When the PWM time base is in the Free Running mode (PTMOD<1:0> =00),
an interrupt event is generated each time a match with the PTPER register occurs. The
PTMR register is reset to zero in the following clock edge.
Using a postscaler selection other than 1:1 will reduce the frequency of
interrupt events [6].
2.4.1.9. PWM Period
The PWM period is defined by the PTPER register pair (PTPERL and
PTPERH). The PWM period has 12-bit resolution by combining 4 LSBs of PTPERH
and 8-bits of PTPERL. PTPER is a double-buffered register used to set the counting
period for the PWM time base.
The PTPER buffer contents are loaded into the PTPER register at the following times:
• Free Running and Single-shot: when the PTMR register is reset to zero after a
match with the PTPER register.
Figure 2. 10 indicate the times when the contents of the PTPER buffer are loaded into
the actual PTPER register.

31

Figure 2. 10: PWM Period Buffer Updates in Free Running Count Mode [6].
The PWM period can be calculated from the following formulas:
Equation2. 6: PWM Period for Free Running Mode
TPWM =
(PTPER + 1)
Fosc /( PTMRPS / 4)
(PTPER + 1) × PTMRPS
TPWM =
Fosc / 4
Equation2. 7: The PWM frequency
1
PWM frequency =
PWM period
The maximum resolution (in bits) for a given device oscillator and PWM frequency
can be determined from the following formula [6]:
Equation2. 8: PWM Resolution
⎛F /4⎞
log⎜⎜ osc ⎟⎟
Re solution = ⎝ FPWM ⎠
log(2 )
32

2.4.1.10. PWM Duty Cycle
PWM duty cycle is defined by PDCx (PDCxL and PDCxH) registers. There
are a total of 4 PWM Duty Cycle registers for 4 pairs of PWM channels. The Duty
Cycle registers have 14-bit resolution by combining 6 LSbs of PDCxH with the 8 bits
of PDCxL. PDCx is a double-buffered register used to set the counting period for the
PWM time base [6].
2.4.1.11. PWM Duty Cycle Registers
There are four 14-bit special function registers used to specify duty cycle values
for the PWM module:
• PDC0 (PDC0L and PDC0H)
The value in each Duty Cycle register determines the amount of time that the
PWM output is in the active state. The upper 12 bits of PDCn hold the actual duty
cycle value from PTMRH/L<11:0>, while the lower 2 bits control which internal Q-
clock the duty cycle match occurs. This 2-bit value is decoded form the Q-clocks as
shown in Figure 2. 11 (when the prescaler is 1:1 (PTCKPS = 00)).6

6
When prescaler is not 1:1 (PTCKPS 00), the duty cycle match occurs at Q1 clock of the instruction
cycle when the PTMR and PDC match occurs.
33

Figure 2. 11: Duty Cycle Comparison [6].
Each compare unit has logic that allows override of the PWM signals. This logic also
ensures that the PWM signals will complement each other (with dead time insertion)
in Complementary mode [6].
2.4.1.12. Duty Cycle Register Buffers
The four PWM Duty Cycle registers are double-buffered to allow glitches
updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer
register that is accessible by the user and a second Duty Cycle register that holds the
actual compare value used in the present PWM period.
In edge-aligned PWM output mode, a new duty cycle value will be updated
whenever a PTMR match with the PTPER register occurs and PTMR is reset as
shown in Figure 2. 12. Also the contents of the duty cycle buffers are automatically
loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0)
[6].
34

Figure 2. 12: Edge-Aligned PWM [6].
2.4.1.13. Complementary PWM Operation
The Complementary mode of PWM operation is useful to drive one or more
power switches in half bridge configuration as shown in Figure 2. 13. This inverter
topology is typical is typical for a 3-phase induction motor, brushless DC motor or a
3-phase Uninterruptable Power Supply (UPS) control applications. Each upper/lower
power switch pair is fed by a complementary PWM signal. Dead time may be
optionally inserted during device switching where both outputs are inactive for a short
period. In Complementary mode, the duty cycle comparison units are assigned to the
PWM outputs as follows:
• PDC0 register controls PWM1/PWM0 outputs

35

PWM1/3/5/7 are the main PWMs that are controlled by the PDC registers and
PWM0/2/4/6 are the complemented outputs. When using the PWMs to control the
half bridge, the odd number PWMs can be used to control the upper power switch and
the even numbered PWMs for the lower switches [6].
Figure 2. 13: Typical Load for Complementary PWM Outputs [6].
The Complementary mode is selected for each PWM I/O pin by clearing the
appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to
Complementary mode by default upon all kinds of device resets [6].
2.4.1.14. Dead Time Generators
In power inverter applications where the PWMs are used in complementary
mode to control the upper and lower switches of a half-bridge, a dead time insertion is
highly recommended. The dead time insertion keeps both outputs in inactive state for
a brief time. This avoids any overlap in the switching during the state change of the
power devices due to TON and TOFF characteristics [6].
Because the power output devices cannot switch instantaneously, some
amount of time must be provided between the turn-off event of one PWM output in a
36

complementary pair and the turn-on event of the other transistor. The PWM module
allows dead time to be programmed [6]. For a result it reduces a cost and complex
circuit. In previously for creating dead time it take time and cost but for PIC18F4431
reduces the complexity, cost and weightless.
Each complementary output pair for the PWM module has a 6-bit down
counter used to produce the dead time insertion. As shown in Figure 2. 14, each dead
time unit has a rising and falling edge detector connected to the duty cycle
comparison output. The dead time is loaded into the timer on the detected PWM edge
event. Depending on whether the edge is rising or falling, one of the transitions on the
complementary outputs is delayed until the timer counts down to zero. A timing
diagram indicating the dead time insertion for one pair of PWM outputs is in Figure 2.
15.
Figure 2. 14: Dead Time Control Unit Block Diagram for One PWM Output Pair
[6].
37

Figure 2. 15: Dead Time Insertion for Complementary PWM [6].
DTCON – Dead Time Control Register
DTPS1 DTPS0 DT5 DT4 DT3 DT2 DT1 DT0
bit 7 bit 0
bit 7-6 DTPS1:DTPS0: Dead Time Unit A Prescale Select bits
Fosc
11 =Clock source for Dead Time Unit is .
16
Fosc
10 = Clock source for Dead Time Unit is .
8
Fosc
4
Fosc
2
bit 5-0 DT5: DT0: Unsigned 6-bit dead time value bits for Dead Time Unit.
Legend:
The actual dead time is calculated from the DTCON register as follows [6]:
38

Equation2. 9: Actual dead time
Dead time =Dead time value/( Fosc /prescaler)

CHAPTER 3
PWM IMPLEMENTATION USING VARIABLE FREQUENCY
3.1. Introduction
During the past two decades, the rapid evolution of digital integrated circuit
technologies has led to ever more sophisticated signal processing systems. These
systems operated on a wide variety of continuous-time signals including speech,
medical imaging, sonar, radar, electronic warfare, instrumentation, consumer
electronics, and telecommunications (terrestrial and satellite). One of the keys to the
success of these systems has been the advance in analog-to-digital converters
(ADC’s) which converter the continuous-time signals to discrete-time, binary-coded
form. As an example, in the telecommunications arena, advances in software radio
development have provided impetus for ADC performance improvement, especially
for sampling rates of approximately 100 million samples per second (Ms/s) [6].
HSADC means (High Speed Analog to Digital Conversion). But in PIC18F4431 has
high Speed 10-bit Analog to Digital Conversion Compatibility. It has Up to 9
channels; Simultaneous two-channel sampling; 1, 2 or 4 selected channels which has
sequential sampling; Auto conversion capability; 4-word FIFO with selectable
interrupt frequency; Selectable external conversion triggers and programmable
acquisition time [4]. This microcontroller can give us our expected result.
40

3.2. Generation Method of ADC
HSADC features lend themselves to many applications including motor
control, sensor interfacing, data acquisition and process control. In many cases, these
features will reduce the software overhead associated with standard A/D modules.
The module has 9 registers:
• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control Register 0 (ADCON0)
• A/D Channel Select Register (ADCHS)
• Analog I/O Select Register 0 (ANSEL0)
• Analog I/O Select Register 1 (ANSEL1)
The A/D channels are grouped into four sets of 2 or 3 channels. AN0, AN4 and
AN8 are in Group A, AN1 and AN5 are in Group B, AN2 and AN6 are in Group C
and AN3 and AN7 are in Group D. The selected channel in each group is selected by
configuring the A/D Channel Select Register, ADCHS.
The analog voltage reference is software selectable to either the device’s positive
and negative analog supply voltage (AVDD and AVSS), or the voltage level on the
RA3/AN3/VREF+/CAP2/QEA and RA2/AN2/VREF-/CAP1/INDX, or some

41

combination of supply and external sources. Register ADCON1 controls the voltage
reference settings [6].
Figure 3. 1: A/D Block Diagram [6].
Each port associated with the A/D converter can individually be configured as
an analog input or digital I/O using the ANSEL0 and ANSEL1 registers. The
ADRESH and ADRESL registers contain the value in the result buffer pointed to by
ADPNT<1:0> (ADCON1<1:0>). The result buffer is a 4-deep circular buffer that has
an empty status bit, BEMT (ADCON1<3>, and an overflow status bit BOVFL
(ADCON1<2>) [6].

42

3.2.1. HSADC Module
ADCON0: A/D Control Register 0
U U R/W R/W R/W R/W R/W R/W
- - ACONV ACSCH ACMOD1 ACMOD0 GO/ ADON
bit 7 bit 0
bit 7-6 Unimplemented: Read as ‘0’
bit 5 ACONV: Auto-Conversion Continuous Loop or Single-shot Mode Select bit
1 = Continuous Loop mode Enabled
0 = Single-shot mode Enabled
bit 4 ACSCH: Auto-Conversion Single or Multi-Channel mode bit
1 = Multi-Channel mode Enabled, Single Channel mode Disabled
0 = Single Channel mode Enabled, Multi-Channel mode Disabled
bit 3-2 ACMOD: Auto-Conversion mode Sequence Select bits
If ACSCH = 1:
00 = Sequential Mode1 (SEQM1). Two samples are taken in sequence:
1st sample: Group A
2nd sample: Group B
01 = Sequential Mode2 (SEQM2). Four samples are taken in sequence:
1st sample: Group A
2nd sample: Group B
3rd sample: Group C
4th sample: Group D
10 = Simultaneous Mode1 (STNM1). Two samples are taken simultaneously:
1st sample: Group A and Group B

43

11 = Simultaneous Mode2 (STNM2). Two samples are taken simultaneously:
1st sample: Group A and Group B
2nd sample: Group C and Group D
If ACSCH = 0, Auto-Conversion Single Channel Sequence mode enabled:
00 = Single Ch Mode1 (SCM1). Group A is taken and converted
01 = Single Ch Mode2 (SCM2). Group B is taken and converted
10 = Single Ch Mode3 (SCM3). Group C is taken and converted
11 = Single Ch Mode4 (SCM4). Group D is taken and converted
bit 1 GO/DONE: A/D Conversion Status bit
1= A/D Conversion cycle in progress. Setting this bit starts the A/D conversion
cycle. If Auto-Conversion Single-shot mode is enabled (ACONV = 0), this bit is
automatically cleared by hardware when the A/D conversion (single or multi-
channel depending ACMOD settings) has completed. If Auto-Conversion
Continuous Loop mode is enabled (ACONV = 1), this bit remains set after the
user/trigger has set it (continuous conversions). If may be cleared manually by the
user to stop the conversions.
0 = A/D conversion or multiple conversions completed/not in progress
bit 0 ADON: A/D On bit
1 = A/D converter module is enabled (after brief power-up delay, starts continuous
sampling)
0 = A/D converter module is disabled
Legend:

44

R/W R/W U R/W R/W R/W R/W R/W
VCFG1 VCFG0 - FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0
bit 7 bit 0
bit 7-6 VCFG<1:0>: A/D VREF+ and A/D VREF− Source Selection bits
00 = VREF+ = AVDD , VREF− = AVss , (AN2 and AN3 are Analog inputs or
Digital I/O)
01 = VREF+ = External VREF+ , VREF− = AVss , (AN2 is an Analog input or
Digital I/O)
10 = VREF+ = AVDD , VREF− = External VREF− , (AN3 is an Analog input or
Digital I/O)
11 = VREF+ =External VREF− , VREF− =External VREF−
bit 5 Unimplemented: Read as ‘0’
bit 4 FIFOEN: FIFO Buffer Enable bit
1 = FIFO is enabled
0 = FIFO is disabled
bit 3 BFEMT: Buffer Empty bit
1 = FIFO is empty
0= FIFO is not empty (at least one of four locations has unread A/D result data)
bit 2 BFOVFL: Buffer Overflow bit
1= A/D result has overwritten a buffer location that has unread data
0 = A/D result has not overflowed
bit 1-0 ADPNT<1:0>: Buffer Read Pointer Locations bits
Designates the location to be read next.

45

00 = Buffer address 0
Legend:
VCFG1 VCFG0 - FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0
bit 7 bit 0
bit 7 ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
bit 6-3 ACQT<3:0>: A/D Acquisition Time Select bits
0000 = No Delay (Conversion starts when Go/DONE is set)
0001 = 2 TAD
0010 = 4 TAD
0011 = 6 TAD
0100 = 8 TAD
0101 = 10 TAD
0110 = 12 TAD
0111 = 16 TAD
1000 = 20 TAD
1001 = 24 TAD

46

1010 = 28 TAD
1011 = 32 TAD
1100 = 36 TAD
1101 = 40 TAD
1110 = 48 TAD
1111 = 64 TAD
bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
011 = FRC/4
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
111 = FRC (Internal A/D RC Oscillator)123
Legend:
ADRS1 ADRS0 - SSRC4 SSRC3 SSRC2 SSRC1 SSRC0
bit 7 bit 0
bit 7-6 ADRS<1:0>: A/D Result Buffer Depth Interrupt Select Control bits for

1
IF the A/D clock source is selected as RC, a time of TCY is added before sampling/ conversions starts.
2
Due to an increase frequency of the internal A/D RC oscillator, FRC/4 provides clock frequencies
compatible with previous A/D modules.
3
In sequential mode TACQ should be 12 TAD or greater.

47

Continuous Loop mode. The ADRS bits are ignored in Single-shot mode.
00 = Interrupt is generated when each word is written to the buffer
01 = Interrupt is generated when the 2nd & 4th words are written to the buffer
10 = Interrupt is generated when the 4th word is written to the buffer
11 = Unimplemented
bit 5 Unimplemented: Read as ‘0’
bit 4-0 SSRCx<4:0>: A/D Trigger Source Select bits
00000 = All triggers disabled
xxxx1 = External interrupt RC3/INT0 starts A/D sequence
xxx1x = Timer5 starts A/D sequence
xx1xx = Input Capture 1 (IC1) starts A/D sequence
x1xxx = CCP2 compare match starts A/D sequence
1xxxx = Power Control PWM module rising edge starts A/D sequence4
Legend:
ADCHS: A/D Channel Select Register
GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0
bit 7 bit 0
bit 7-6 GDSEL1:GDSEL0: Group D Select bits
S/H-2 positive input
00 = AN3

4
SSRCx<4:0> bits can be set such that any of the triggers will be start conversion (e.g. SSRCx<4:0> =
00101, will trigger the A/D conversion sequence when RC3/INT0 or Input Capture 1 event occurs).

48

01 = AN7
1x = Reserved
bit 5-4 GBSEL1:GBSEL0: Group B Select bits
00 = AN1
01 = AN5
1x = Reserved
bit 3-2 GCSEL1:GCSEL0: Group C Select bits
00 = AN2
01 = AN6
1x = Reserved
bit 1-0 GASEL1:GASEL0: Group A Select bits
00 = AN0
01 = AN4
10 = AN8
11 = Reserved
Legend:

49

ANSEL0: Analog Select Register 0
ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0
bit 7-0 ANS<7:0>: Analog Input Function Select bits
Correspond to pins AN<7:0>
1 = Analog Input
0 = Digital I/O5
Legend:
ANSEL1: Analog Select Register 1
U U U U U U U R/W
- - - - - - - ANS8
bit 7 bit 0
bit 15-9 Unimplemented: Read as ‘0’
bit 8 ANS<7:0>: Analog Input Function Select bit
1 = Analog Input
0 = Digital I/O6

5
Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should
be set for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to
the ANx pins (e.g., ANS0 = AN0, ANS1 = AN1, etc.) Unused ANSx bits are to be read as ‘0’.
6
Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should
be set for an input and cleared for an output (analog or digital). The ANSx bits directly correspond to
the ANx pins (e.g., ANS8 = AN8, ANS9 = AN9, etc.) Unused ANSx bits are to be read as ‘0’.

50

Legend:
3.2.2. Configuring the A/D converter
The A/D converter has two types of conversion, two modes of operation and
eight different sequencing modes. These features are controlled by the ACONV bit
(ADCON0<5>), ADCSH bit (ADCON0<4>) and ACMOD<1:0> bits
(ADCON0<3:2>). In addition, the A/D channels are divided into four groups as
defined in the ADCHS register. Table 3. 1 shows the sequence configurations as
controlled by ACSCH and ACMOD<1:0>.
Table 3. 1: Auto-Conversion Sequence Configurations
Mode ACSCH ACMOD Description
Multi-Channel Sequential Mode1 1 00 Grouped A and B
(SEQM1) are sampled and
converted
sequentially
Multi-Channel Sequential Mode2 1 01 Group A,B, C and
(SEQM2) D are sampled and
converted
sequentially
Multi-Channel Simultaneous Mode1 1 10 Group A and B are
(STNM1) sampled
simultaneously and

51

converted
sequentially
Multi-Channel Simultaneous Mode2 1 11 Group A and B are
(STNM2) sampled
simultaneously and
converted
sequentially. Then,
Group C and D are
sampled
simultaneously,
and then converted
sequentially.
Single Channel Mode1 (SCM1) 0 00 Group A is
sampled and
converted
Single Channel Mode2 (SCM2) 0 01 Group B is sampled
and converted
Single Channel Mode3 (SCM3) 0 10 Group C is sampled
and converted
Single Channel Mode4 (SCM4) 0 11 Group D is
sampled and
converted

52

3.2.3. A/D Result Register
The ADRESH:ADRESL register pair is the location where the 10-bit A/D
result is loaded at the completion of the A/D conversion. The register pair is 16-bits
wide. The A/D module gives the flexibility to left- or right-justify the 10-bit result in
the 16-bit result register. The A/D Format Select bit (ADFM) controls this
justification [6].
ADRESH ADRESL
Left-Justified 9 2 1 0 UNUSED
ADFM = 0
Right-Justified UNUSED 9 8 7 0
ADFM = 1
Figure 3. 2: A/D Result Justification [7].

53

3.3. Overview Flowchart of the Program in Generating 3 phase Sinusoidal
PWM Signal with Variable Frequency

54

3.4. Flowchart of the Main Function’s Program for generating 3 phase
sinusoidal PWM signal with variable frequency

CHAPTER 4
RESULTS AND DISCUSSION
4.1. 120 sampling value use by MATLAB
Here we have defined the value of the sine wave sampling value. It is difficult
to calculate the 120 sine wave sampling value. So, measured that sine wave sampling
value by
Equation 4. 1: equation of sine wave
y = A + A sin x
Here x is the time and A is the Amplitude.
For example, when x=0 and A = 100 then,
y = 100 + 100 sin 0 = 100 + 100 × 0 = 100 + 0 = 100 .
Figure 4. 1: The sine wave of 120 sampling value from MATLAB

56

y=
Columns 1 through 9
100.0000 105.2775 110.5404 115.7738 120.9633 126.0943 131.1527 136.1242
140.9950
Columns 10 through 18
145.7515 150.3806 154.8692 159.2049 163.3755 167.3696 171.1758 174.7837
178.1831
181.3647 184.3194 187.0392 189.5163 191.7440 193.7159 195.4267 196.8714
198.0462
198.9477 199.5734 199.9216 199.9913 199.7823 199.2952 198.5313 197.4928
196.1826
194.6043 192.7623 190.6617 188.3085 185.7092 182.8709 179.8017 176.5101
173.0052
169.2968 165.3953 161.3116 157.0569 152.6432 148.0828 143.3884 138.5730
133.6501

57

128.6335 123.5370 118.3750 113.1617 107.9117 102.6397 97.3603 92.0883
86.8383
81.6250 76.4630 71.3665 66.3499 61.4270 56.6116 51.9172 47.3568
42.9431
38.6884 34.6047 30.7032 26.9948 23.4899 20.1983 17.1291 14.2908
11.6915
9.3383 7.2377 5.3957 3.8174 2.5072 1.4687 0.7048 0.2177 0.0087
0.0784 0.4266 1.0523 1.9538 3.1286 4.5733 6.2841 8.2560 10.4837
12.9608 15.6806 18.6353 21.8169 25.2163 28.8242 32.6304 36.6245
40.7951
45.1308 49.6194 54.2485 59.0050 63.8758 68.8473 73.9057 79.0367
84.2262

58

89.4596 94.7225 100.0000
200
data1
180
160
140
120
100
80
60
40
20
0
0 1 2 3 4 5 6 7
Figure 4. 2: The output of sine wave from MATLAB
200
180
160
140
120
100
80
60
40
20
0
0 20 40 60 80 100 120
Figure 4. 3: How the sine waves are sampled by MATLAB.

59

200
180
160
140
120
100
80
60
40
20
0
0 1 2 3 4 5 6 7
Figure 4. 4: Figure of saw tooth generation
In Figure 4. 5 showing the generation of saw tooth. When sine wave and saw
tooth wave compare the width of PWM signal is changing. And the pick value of saw
tooth wave depending on the ADC value. For this reason variable frequency of the
PWM signal is generating by this process.
4.2. PCPWM Output
Here this output is the simulation of 3 phase PWM signal. And there is also
have dead time.

60

Figure 4. 5: Simulation result of PWM signal which have also a dead time.
In this figure we got that simulation result from MPLAB IDE v8.20. In before
we used MPLAB IDE v.6.20 but there were not any option for visualize the
waveform. We can see that waveform by logic analyzer.
Figure 4. 6: Pin diagram of the Microcontroller

61

In Figure 4. 6 is the pin diagram of the microcontroller 33 to 38 number of pins will
give the output of PWM and AN0 or 2 number pin is the Analog input which is
varying the frequency.
Figure 4.7: Figure of the PWM signal in PC base Oscilloscope

62

4.3. ADC
Figure 4. 8: Figure of ADC result’s for Test
In Figure 4. 2, we are showing that in our project board we are testing the
ADC signal by varying the variable resistance. And depending on the value of
resistance changes the position of the lightening the LED’s.

63

4.4. Variable Frequency of Three phase PCPWM Signals output
Figure 4. 9: The output of the variable frequency of Three phase PCPWM
Signals
In Figure 4. 5 we showing the software of SoftView. For observation of our
waveform we used new digital oscilloscope. This oscilloscope model name and
number is “Ez Digital Oscilloscope DS-1100 100MHz”. By this oscilloscope we can
observe only two signals. That means there were only channel. And we observe that
by changing the variable resistance the ADC is output is changing. We observer by
LED’s output and also correspondingly changing the PWM width, Period and
Frequency of the value in Figure 4. 5 +WIDTH, –WIDTH, PERIOD, FREQ.

64

Figure 4. 10: Ch2-PWM0 and Ch1-PWM2
Figure 4. 11: Ch2-PWM4 and Ch1-PWM2
Figure 4. 12: Single phase Independent and complementary mode

65

In Figure 4.10 showing that Independent mode and complementary mode of
the PWM signals and also there have some dead time. In Channel 2 have 1 delay.
This is dead time.
Figure 4. 13: PWM2-PWM3

CHAPTER 5
CONCLUSION AND FUTURE WORKS
5.1. Conclusion
In this work, a three phase PWM signal with variable frequency has been
implemented in PIC18F4431 microcontroller. Several outstanding features of the
developed PCPWM (Power Control Pulse Width Modulation) are highlighted as
follows:
1. HSADC (High speed ADC) module determine the pick value of the saw tooth.
2. By generating the Sinusoidal three phase PWM signal in variable frequency,
there have better harmonic.
3. Both PWM signal and Dead time control circuits can be implemented in a
single board microcontroller, which makes the system reliable, compact and
low cost.
The laboratory test results confirm that the 3 phase sinusoidal PWM signal
generating with dead time.
5.2. Future Works
Our low cost Micro Controller based three phases PWM signals could be used
in electrical vehicle application. Therefore further works could be done on control the
speed of motor.
REFERENCES
[1] (n.d.). Retrieved from http://www.tech-faq.com/pulse-width-modulation.shtml
[2] 2.6., I. X. (n.d.). Retrieved from
http://ieeexplore.ieee.org/Xplore/defdeny.jsp?url=http%3A%2F%2Fieeexplore.
ieee.org%2Fstamp%2Fstamp.jsp%3Ftp%3D%26isnumber%3D573%26arnumb
er%3D15183&denyReason=-131&arnumber=15183&productsMatched=null
[3] A.M. Hava, R. K. (1997). A High Performance Generalized Discontinuous
PWM Algorithm.
[4] Burroughs, J. (2004). Controlling 3-Phase AC Induction Motors Using the
PIC18F4431. Microchip Technology Inc.
[5] Kerkman, D. L. Pulse Based Dead Time Compensator for PWM Voltage
Inverters.
[6] MICROCHIP. (2003). PIC18F2331/2431/4331/4431 Data Sheet. Michrochip
Techonology Inc.
[7] Muhammad Ali Mazidi, R. D. (2008). PIC Microcontroller and Embedded
Systems using Assembly and C for PIC18. Dorling Kindersley (India) Pvt. Ltd.
[8] Parekh, R. (2005). VF Control of 3-Phase Induction Motor Using Space Vector
Modulation. Microchip Technology Inc.
[9] Salim, K. M. (June, 1999). Development of Power Conditioner Unit (PCU) For
Fuel Cell. Master's Thesis.

68

[10] Walden, R. H. (April 1999). Analog-to-Digital Converter Survey and
Analysis. IEEE Journal on Selected Areas in Communications , Vol. 17, No. 4,
P.539.
[11] Yedamale, P. (2002). Speed Control of 3-Phase Induction Motor Using PIC18
Microcontrollers. Microchip Technology Inc.
[12] Yosihiro Konishi, N. B. (2000). A Novel Three-Phase Current-Fed ZCS-PWM
Converter Incorporating a Single Resonant DC Link Soft Communication
Snubber. Electrical Engineering in Japan , Vol. 132, No.3.

APPENDIX A
PROGRAM FOR PIC18F4431 MICROCONTROLLER
;***********************************************************************
;EEE 498: Senior Project
;Name: S. M. Mohaiminul Islam
;ID# 0520145
;Major: Electrical & Electronics Engineering
;School of Engineering and Computer Science
;Independent University, Bangladesh
;************************************************************************
include <p18f4431.inc>
include <3im_vf.inc>
__CONFIG _CONFIG1H, 0x02 ;_OSC_HS_1H

&_FCMEN_OFF_1H&_IESO_OFF_1H
__CONFIG _CONFIG2L, 0x01 ;_PWRTEN_ON_2L & _BOREN_ON_2L &

_BORV_20_2L
__CONFIG _CONFIG2H, 0x20 ;_WDTEN_OFF_2H
__CONFIG _CONFIG3L, 0x38 ;0x24 ;_PWMPIN_OFF_3L & _LPOL_LOW_3L &

_HPOL_LOW_3L & _GPTREN_ON_3L
__CONFIG _CONFIG3H, 0x99 ;_FLTAMX_RC1_3H & _PWM4MX_RB5_3H
__CONFIG _CONFIG4L, 0x80
__CONFIG _CONFIG5L, 0x0F
__CONFIG _CONFIG5H, 0xC0
__CONFIG _CONFIG6L, 0x07
__CONFIG _CONFIG6H, 0xE0

70

__CONFIG _CONFIG7L, 0x0F
__CONFIG _CONFIG7H, 0x40
;********************Label Defination**********************
c4 equ 0x24;
c5 equ 0x25;
;For PCPWM
counter1 equ 0x008; for 1st phase: Counting the sine wave
sampling value
counter2 equ 0x009; for 2nd phase: Counting the sine wave
sampling value
counter3 equ 0x00A; for 3rd phase: Counting the sine wave
sampling value
;********************Program Start**************************
org 0x000; Reset Vector
goto Start;
org 0x008; Interrupt Vector
goto ISR_HIGH; High priority ISR at 0x0008
org 0x018; Interrupt Vector
goto ISR_LOW; Low priority ISR at 0x018
;**************************************************************************
*****
;**************************************************************************
*****
; INITIALIZATION

71

;**************************************************************************
*****
;**************************************************************************
*****
Start
call clearall;
call INIT_PORTC; Use for ADC will show 2 bits Digital output
call INIT_PORTD; Use for ADC will show 8 bits Digital output
call INIT_PORTB; Use for PCPWM output
call INIT_IC1;
call INIT_HSADC;
call INIT_PCPWM;
call INIT_INTERRUPTS;
call MAIN;
;**************************************************************************
*****
;**************************************************************************
*****
; 120 sampling value for SINE

WAVE TABLE
;**************************************************************************
*****
;**************************************************************************
*****
SINE_WAVE
addwf PCL,1;

72

retlw D'100'; for Sampling number 1

73


74


75


76


77

retfie; return from subroutine
;**************************************************************************
*****
;**************************************************************************
*****
;Clearing the user defined memory cell and initialize the value of user defined memory cell
;**************************************************************************
*****
;**************************************************************************
*****
clearall
;for PCPWM
clrf counter1; Initialize the 0 degree phase sine wave value
clrf INTCON;
movlw .40;
movwf counter2; Initialize the 120 degree phase sine wave

value
movlw .80;

78

movwf counter3; Initialize the 240 degree phase sine wave
value
;for ADC
clrf ADRESH;
clrf ADRESL;
clrf ADCON0;
clrf STATUS;
clrf c4; Use for ADC output
clrf c5; Use for ADC output
return;
;**************************************************************************
*****
;Initialize PORTD
;**************************************************************************
*****
INIT_PORTD
clrf PORTD
clrf LATD;
clrf TRISD; By clearing TRISB, PORTB will give us

output
clrf PORTD; Using for output port.
return;
;**************************************************************************
*****
;Initialize PORTC

79

;**************************************************************************
*****
INIT_PORTC
clrf PORTC;
clrf LATC;
clrf TRISC; Declare port C as output
clrf PORTC;
return;
;**************************************************************************
*****
;Initialize PORTB
;**************************************************************************
*****
INIT_PORTB
bcf INTCON2,7; PORTB Pull-up Enable bit. PORTB pull-ups

are enabled by individual port latch values
clrf PORTB
clrf LATB;
clrf TRISB; By clearing TRISB, PORTB will give us

output
clrf PORTB; Using for output port.
return;
;**************************************************************************
*****
;Initialize IC1

80

;**************************************************************************
*****
INIT_IC1
clrf QEICON ; Clear QEICON to make sure that

QEI mode is disabled.
movlw b'01001000' ;Configure CAP1CON such that:
movwf CAP1CON ; a)Timer5 resets on capture event
; b)Capture on every CAPx

input state change
bsf TRISA, 2 ; Make TRISA pin corresponding to

IC1 (INDX signal from encoder)an input
movlw b'00000001' ; T5CON is configured such that:
movwf T5CON ; a) Special event reset is disabled
; b) Continuous count mode

is enabled
; c) Timer5 input clock

prescaler is 1:1
; e) Timer5 is enabled
movlw b'00000010' ; Digital filter is configured
movwf DFLTCON ; a) INDX filter disabled
; b) noise filter clock divider

= 1:4
return

81

;**************************************************************************
*****
;Initialize High-Speed ADC
;**************************************************************************
*****
INIT_HSADC
movlw b'00010000' ; ADCON1 is configured such that:
movwf ADCON1 ; a) Vref+ and Vref- are Avdd and

Avss, respectively.
; b) The FIFO buffer is

enabled
movwf ADCON2 ; a) The A/D result is right justified

(so remember to read ADRESH before reading ADRESL)
; b) The A/D acquisition

time is set to No Delay (Conversion starts immediately when GO/DONE is set), as required
for sequential conversion.
; c) The A/D conversion

clock is set to Fosc/2.
movwf ADCON3 ; a) An interrupt is generated on

every 2nd and 4th write to the FIFO buffer.
; b) Power Control PWM

module raising edge starts A/D sequence.

82

movlw b'00000100' ; ADCHS is configured such that:
movwf ADCHS ; a) Group A signal is AN0, Variable

Frequency reference
movlw b'00000100' ; ANSEL2 is configured such that:
movwf ANSEL0 ; a) AN2 is analog input pin.
movlw b'00000100' ; b) Corresponding bits of TRISA are also

set to inputs.
movwf TRISA
movwf ADCON0 ; a) Single-shot mode is enabled
; b) Single-channel mode is
enabled
; c) Group A signal is
sampled (speed ref on development board)
; d) The ADC is turned on.
return
;**************************************************************************
*****
;Initialize PCPWM
;**************************************************************************
*****
INIT_PCPWM
movlw 0xFF

83

movwf PTPERL ;PWM Time Base RegisterL decimal
value will 255
movlw 0x00
movwf PTPERH ;PWM Time Base RegisterL decimal

value will 0
movlw b'01000000' ; PWMCON0 is configured such that:
movwf PWMCON0 ;a) PWM0, PWM1, PWM2, PWM3,

PWM4, and PWM5 are enabled for output.
; b) All PWM I/O pairs are

set to complimentary mode
movlw b'00000001' ;PWMCON1 is configured such that:
movwf PWMCON1 ; a) Special event trigger post-scaler

is set to 1:1
; b) Special event trigger

occurs when time-base is counting upwards
; c) Updates from duty cycle

and period buffer registers are enabled.
; d) Output overrides via

OVDCON are synchronous to the PWM timebase.
movlw b'00001010' ;1us deadtime instead of 2us
movwf DTCON ;DTCON is configured such that:

84

; a) Clock source for dead-
time is Fosc/2.
; b) Dead time = Dead time

value / (Fosc/2) = 2uS.
movlw b'11111111' ;OVDCOND is configured such that there is

no output override.
movwf OVDCOND
movlw b'11111111' ;OVDCONS is configured such that all

PWM outputs are 1 (inactive) upon power-up.
movwf OVDCONS
movlw 0x00 ;SEVTCMPL and SEVTCMPH are clear.
movwf SEVTCMPL
movlw 0x00
movwf SEVTCMPH
call PWM_DEAUTY_CYCLE1;
bsf PTCON1, PTEN ;PTEN bit in the PTCON1 is set to

enable the PWM time base.
bcf PTCON1,6; ;PWM time base counts up.

85

movlw b'00000000' ; PTCON0 is configured such that:
movwf PTCON0 ; a) Postscale value is 1:1
; b) PWM time base input is

Fosc/4
; c) PWM time base mode is

free-running for edge-aligned operation
movlw b'00000000' ;Fault A and FaultB are disabled in

catastrophic mode.
movwf FLTCONFIG ; a) Enable fault condition on break-point for

use with ICD2
; b) Enable FaultA in cycle-

by-cycle mode
; c) Enable FaultB in cycle-

by-cycle mode
; d) Fault A and Fault B

disable PWM channels 0 to 5
return;
;**************************************************************************
*****
;Initialize interrupts
;**************************************************************************
*****
INIT_INTERRUPTS

86

; for ADC
bsf PIE1, ADIE ;Peripheral Interrupt

Enable Register1 has bit 6 is: ADIE= A/D Converter Interrupt Enable bit.
;Enbales the
A/D interrupt
bcf IPR1, ADIP ;Peripheral Interrupt

Priority Register1 has bit 6 is: ADIP= A/D Converter Interrupt Priority bit.
;Low
priority bit.
bsf PIE2, CCP2IE ;Peripheral Interrupt Enable

Register2 has bit 0 is: CCP2IE= CCP2 Interrupt Enable bit.
;Enables
CCP2 Interrupt
bcf PIR2, CCP2IF ;Peripheral Interrupt

Request (Flag) Register2 has bit 0 is: CCP2IF= CCP2 Interrupt Flag bit.
bsf IPR2,CCP2IP ;CCP2 Interrupt

Priority bit is High Priority
;for PCPWM
bcf INTCON,RBIE ;Disable the RB Port

Change Interrupt RB7:RB4 pins
bcf INTCON,RBIF ;None of the

RB7:RB4 pins have changed state

87

bsf PIE3, PTIE ;PWM Time Base
Interrupt Enable bit
bcf IPR3, PTIP ;PWM Time Base

Interrupt Priority Base is High Priority.
bcf PIR3,PTIF ;PWM Time Base

matched the value in PTPER register. Interrupt is issued according to the postscaller settings.
PTIF must be cleared in software.
bcf INTCON2,0;
;for IC1
bcf IPR3, IC1IP ;IC1(Input

Capture1) Interrupt Priority bit is Low.
bsf PIE3, IC1IE ;IC1(Input

Capture1) interrupt enabled
bcf PIR3, IC1IF ;IC1 Interrupt Flag

bit
bsf RCON,IPEN ;Interrupt Priority

Enable bit
bsf INTCON,GIEL ;Enable low priority

interrupts
bsf INTCON,GIEH ;Enable high

priority interrupts
return

88

;**************************************************************************
*****
;High priority interrupt service routine
;**************************************************************************
*****
ISR_HIGH
bcf PIR3,PTIF ;PWM Time Base

Interrupt bit
;PWM Time
Base has not matched the value in PTPER register.
bsf PTCON1,PTEN ;PWM Time Base

matched the value in PTPER register. Interrupt is issued according to the postscaller settings.
PTIF must be cleared in software.
bcf INTCON,RBIF ;RB Port Change

Interrupt Flag bit
bcf INTCON2,0;
RETFIE FAST

89

;**************************************************************************
*****
;Low priority interrupt service routine
;**************************************************************************
*****
ISR_LOW
btfss PIR1, ADIF ;A/D Converter Flag bit.

A/D Conversion completed or not?
goto MAIN;
call RESULT_ADC
RETFIE FAST
MAIN
btfss PIR3, IC1IF ;TMR5 value was captured

by the active edge on CAP1 input or not?
call ISR_HIGH;
nop;
call ENABLE_ADC;
goto MAIN;
ENABLE_ADC
bsf ADCON0,1 ;A/D Conversion

Status bit. GO/DONE bit.

90

call ISR_LOW;
return;
RESULT_ADC
movf ADRESH,0;
movwf c4;
movf ADRESL,0;
movwf c5;
movf c4,0;
movwf PORTC;
movwf PTPERH;
movf c5,0;
movwf PORTD;
movwf PTPERL;
bcf PIR1, ADIF ;Peripheral Interrupt

Request (Flag) Register1 has bit 6 is: ADIF: A/D Converter Interrupt Flag bit.
;The A/D
conversion is not complete.
bcf PIR2, CCP2IF
bcf PIR3, IC1IF
bsf ADCON0, 0;

91

; bsf ADCON0, 1;
return;
PWM_DEAUTY_CYCLE1
movf counter1,0; move the content of the memory to w
call SINE_WAVE;
movwf PDC0L;

is set to 1:1



incf counter1,1;
movf counter1,0;
xorlw .120;
btfss STATUS,Z;
return;
clrf counter1;

92

return;
PWM_DEAUTY_CYCLE2
call SINE_WAVE;
movwf PDC1L;

is set to 1:1



incf counter2,1;
movf counter2,0;
xorlw .120;
btfss STATUS,Z;
return;
clrf counter2;

93

return;
PWM_DEAUTY_CYCLE3
call SINE_WAVE;
movwf PDC2L;

is set to 1:1



incf counter3,1;
movf counter3,0;
xorlw .120;
btfss STATUS,Z;
return;
clrf counter3;

94

return;
;*************************** END of the Program********************
END
;*******************************************************************

95

APPENDIX B
PROGRAM FOR GENERATING 120 SAMPLING VALUE OF SINE
WAVE BY MATLAB
x=0:(2*pi/119):(2*pi);
y=100+(100*sin(x))
plot(x,y)
stem(y)

96

APPENDIX C
PROGRAM FOR GENERATING SAW TOOTH BY MATLAB
t = [0:pi/50:2*pi];
x = 101+(101*sawtooth(t));
plot(t,x)

Generate 3-Phase Sinusoidal PWM Signal with Variable Frequency

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GENERATION OF 3 PHASE SINUSOIDAL PWM SIGNAL WITH VARIABLE

FREQUENCY BY USING LOW COST MICROCONTROLLER

A Senior Project Report Presented in Partial Fulfillment

INDEPENDENT UNIVERSITY, BANGLADESH

GENERATION OF 3 PHASE SINUSOIDAL PWM SIGNAL WITH VARIABLE

has been approved

Dr. Khosru M. Salim

Modulation) signal with variable frequency by using low cost microcontroller.

PIC18F4431 microcontroller is used for generating three phase sinusoidal PWM

other three signals are in complementary mode.

We wish to thank my supervisor Dr. Khosru Mohammad Salim for his

discussions among us about this work.

support to carry out this project.

Md. Abdul Malek, for their cooperation and interest.

1.4. Outline of Project……………………………………………………….... 4

2 SINUSOIDAL PWM AND HARWARE DESCRIPTION OF THE PWM

2.2.1. Natural Sampling PWM……………………………………… 6

2.2.2. Regular Sampling PWM…………………………………….... 8

2.2.3. Harmonic injection PWM (HPWM) technique……………… 11

2.3. Microchip PIC18F4431 Microcontroller………………………............... 14

2.4.1. PCPWM Module………………………………………………. 16

2.4.1.1. Control Registers…………………………………... 20

2.4.1.2. Module Functionality……………………………… 21

2.4.1.3. PWM Time Base…………………………………... 22

2.4.1.4. Free Running Mode………………………………... 28

2.4.1.5. PWM Time Base Prescaler………………………… 28

2.4.1.6. PWM Time Base Postscaler……………………….. 29

2.4.1.7. PWM Time Base Interrupts……………………….. 30

2.4.1.8. Interrupts in Free Running Mode………………….. 30

2.4.1.9. PWM Period……………………………………….. 30

2.4.1.10. PWM Duty Cycle………………………………….. 32

2.4.1.11. PWM Duty Cycle Registers……………………….. 32

2.4.1.12. Duty Cycle Register Buffers………………………. 33

2.4.1.13. Complementary PWM Operation………………….. 34

2.4.1.14. Dead Time Generators…………………………….. 35

3 PWM IMPLEMENTATION USING VARIABLE FREQUENCY……………. 39

3.2. Generation Method of ADC…………………………………………….. 40

3.2.1. HSADC Module………………………………………………….. 42

3.2.2. Configuring the A/D converter…………………………………... 50

3.2.3. A/D Result Register……………………………………………... 52

3.3. Overview Flowchart of the Program in Generating 3 phase Sinusoidal

PWM Signal with Variable Frequency…………………………………… 53

3.4. Flowchart of the Main Function’s Program for generating 3 phase

sinusoidal PWM signal with variable frequency………………………… 54

4 RESULTS AND DISCUSSION…………………………………………………. 55

4.1. 120 sampling value use by MATLAB………………………………….... 55

4.2. PCPWM Output…………………………………………………………... 59

4.4. Variable Frequency of Three phase PCPWM Signals output…………... 63

5 CONCLUSION AND FUTURE WORKS……………………………………… 66

5.2. Future Works…………………………………………………………….. 66

A PROGRAM FOR PIC18F4431 MICROCONTROLLER………………………. 69

B PROGRAM FOR GENERATING 120 SAMPLING VALUE OF SINE WAVE

C PROGRAM FOR GENERATING SAW TOOTH BY MATLAB…………….. 96

2.1 Minimum PWM Frequency……………………………………. 29

3.1 Auto-Conversion Sequence Configurations…………………… 50

1.1 Block Diagram of PIC18F4431 Microcontroller Voltage

2.1 Natural sampling PWM generation…………………………….. 7

2.2 Symmetrical and asymmetrical regular sampled PWM……….. 9

2.3 Generation of PWM waveform using regular symmetric

2.4 3rd harmonic injection modulation…………………………. 13

2.5 Block diagram of PIC18F4431 Microcontroller…………….. 15

2.6 Power Control PWM Module Block Diagram………………… 18

2.7 PWM Module Block Diagram, One Output pair,