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Gate Sizing - FinFETs Vs 32nm Bulk MOSFETs W by L
Gate Sizing - FinFETs Vs 32nm Bulk MOSFETs W by L
Ckt Norm.
Delay
Norm.
Area
Norm.
Ptotal
%Pdyn %Psc Norm.
Pstandby
% Wmin 5. CONCLUSION
alu2 4.66 5.144 0.251 49.5 50.5 311.456 45.8 This paper provides the first detailed comparison of finFET and
C1908 4.59 8.880 0.443 43.5 56.5 476.622 30.7 32nm bulk circuits. In addition, the paper shows how to use ther-
s9234.1 4.53 3.870 0.210 57.2 42.8 205.723 54.5 mal information to guide circuit optimization problems. We inves-
dsip 4.19 2.003 0.147 65.7 34.3 259.779 91.7 tigated how finFET sizing, independent-gate biasing, and fin width
s15850.1 4.16 2.425 0.173 67.6 32.4 143.812 85.8 can be used to achieve performance at minimum dynamic power.
mm30a 4.60 26.914 0.973 40.6 59.4 1,241.383 68.2 Our results show that finFETs outperform 32nm bulk devices and
C432 4.61 5.818 0.278 47.4 52.6 351.615 34.3
s298 4.33 2.686 0.191 62.5 37.5 138.022 58.2
encourage further research into more efficient heuristic finFET siz-
t481 4.47 2.421 0.154 57.2 42.8 169.044 78.3 ing techniques and further detailed experiments.
C3540 4.63 3.992 0.221 50.5 49.5 234.704 49.7
s1196 4.51 4.066 0.224 52.6 47.4 241.516 47.4
6. ACKNOWLEDGMENTS
Avg. 4.48 6.2 0.3 54.03 45.97 343.06 58.6
We would like to thank Fadi Aloul for sharing his SAT solver.
Table 2: 32nm active power optimization.
7. REFERENCES
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