IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. I, NO. 1.
JANUARY 1992
High-Performance Current Control Techniques for
Applications to Multilevel High-Power Voltage
Source Inverters
Mario Marchesoni, Member, IEEE
Abstract-A multilevel approach seems to be best suited to
facing many problems arising from the use of high-power con-
verters. New current control strategies have been developed in
order to attain an adequate switching optimization, excellent
dynamic responses, and high accuracy in steady-state opera-
tion. The advantages of using several accessible dc potentials
have been fully exploited. The related control schemes and the
results obtained by digital simulations are presented and dis-
cussed.
I. INTRODUCTION
T HE PAST few years have witnessed considerable ad-
vances in power semiconductor technology, which
currently allows the development of new and hitherto un-
imaginable applications. For instance, highest power
GTO’s (gate turn-off thyristors) have now a blocking ca-
pability of 4500 V and can switch off currents up to 2500-
3000 A. These components make it possible to realize
high-power VSI’s (voltage source inverters) that do not
need any active or passive components for forced com-
mutations. Such devices can handle powers up to several
megavolt amperes, but their switching frequency is lim-
ited to a few hundred hertz. Newly developed semicon-
ductor devices like IGBT’s (insulated gate bipolar tran-
sistors) and SIT’S (static induction transistors and
thyristors) can reach higher switching frequencies at
lower, but always considerable, power levels.
However, when adopting traditional inverter topolo-
gies, very high powers cannot be obtained unless prob-
lematic series/parallel combinations of semiconductor de-
vices are used, which further lower the highest possible
switching frequencies. This is one of the reasons why, up
to now, high-power converters have often been designed
and used for applications that did not require too high dy-
namic performances. For instance, in the case of an ac
motor drive using the field orientation scheme, it is well
known that the assumption of ideally impressed stator
currents would offer substantial advantages in that it would
eliminate stator dynamics from the system equations.
This hypothesis turns out to be well verified when using
Manuscript received November 14, 1989; revised April 26, 1991. This
work was supported by the Italian Ministry of Education.
The author is with the Electrical Engineering Department, University of
Genoa, 16145 Genoa, Italy.
IEEE Log Number 9105019.
0885-8993/92$03.00 0 1992 IEEE
189
VSI’s with high-performance current control techniques.
If a high-dynamics response is required, the load current
should be fed back and compared directly with the alter-
nating reference value by means of hysteresis compara-
tors [l], [ 2 ] . But such functioning is not consistent with
low switching frequencies, especially near zero speed,
when the motor counter emf is particularly low: a few
commutations imply too high harmonic contents, which
usually result in pulsating torques and losses that are un-
acceptable at high power levels. By using different in-
verter layouts based on a multilevel structure, the power
level can be raised, and high-dynamics current control
strategies can be applied, even in the megavolt-ampere
range. In this way, ac motor drives with excellent dy-
namic responses can be realized, which can be profitably
employed, for example, in rolling-mill applications [3].
Of course, other applications areas exist where the use
of current controlled VSI’s is particularly suitable. In nu-
clear fusion experiments, for instance, high-power in-
verters are gaining wide use. The author has cooperated
to the design of a nonconventional power converter, which
has been studied to compensate for the instabilities that
may occur when the plasma parameters approach the lim-
its reached thus far [4]. Such a converter acts as a quasi-
linear current amplifier and can deliver a peak power of
3.6 MVA with a bandwidth ranging from dc values up to
10 kHz using IGBT’s as semiconductor devices. High-
dynamics requirements have been met by adopting a suit-
able control strategy, which can be utilized only for the
specific load considered in [4], however.
Further studies have shown that it is possible to opti-
mize and extend this technique to any structure of multi-
level inverter. This paper presents and analyzes the sev-
eral current control strategies that have been developed to
fully exploit the advantages of using various accessible dc
potentials. Results of digital simulations, performed using
the general-purpose program electromagnetic transients
program (EMTP) [ 5 ] , [ 6 ] ,are reported and discussed.
11. MULTILEVEL INVERTER STRUCTURES
Some generalized structures of multilevel inverters have
been described in the technical literature [ 7 ] . Fig. 1 shows
the so-called NPC (neutral point clamped) inverter [8],
[9] for single-phase applications; this structure is usually
I90
S7
I 4
Fig. 1. The NPC inverter.
defined as a three-state inverter (due to its three accessible
dc potentials) and makes it possible to obtain a five-level
output voltage. A conventional single-phase H-bridge in-
verter allows at most four ( 2 x 2) different switching
states, whereas the NPC inverter allows nine (3 X 3);
consequently, better modulations can be obtained. Ob-
viously, there are more switching states that produce the
same output voltage level, as shown in Table I (the turn
of a switch is assumed to occur at logic level “ 1 , ” the
turn off at logic level “0”). Only switches S 1 , S,, S2, and
S8 can be driven independently of each other, whereas Ss,
S3, S6, and S4 are driven in a complementary way. In any
possible switching configuration, each semiconductor de-
vice has to block, at most, a voltage equal to half the dc
link one, if every branch of the NPC inverter is controlled
in such a way as to avoid sudden variations from -E to
+ E (with respect to neutral point 0), and vice versa. In
this way, besides obtaining a lower harmonic content,
there is no need to turn off two switches simultaneously
while turning on the other two. As a matter of fact, the
inverter presented in Fig. 1 is made up of series-con-
nected components, but a correct static voltage balance
can be obtained more easily than a good dynamic balance.
It is also worth noting that the switching configurations
with both the upper and lower switches of a bridge branch
turned on are not suitable in that the output voltage would
depend on the direction of the load current, and either of
the intermediate switches (S, or Ss, for the first branch)
would have to block the full dc-link voltage.
Another solution consists in the series connection of
single-phase H-bridge inverters, each made up of four
solid-state devices. Fig. 2 shows the related basic struc-
tural arrangement, which also represents a part of the non-
conventional power converter described in [4],utilizing
IGBT’s as semiconductor devices. For this reason,
IGBT’s are also included in the structures displayed in
Figs. 1 and 2 ; obviously, this choice is not a prerequisite,
as any inverter is designed according to the specifications
required by the application considered. Fig. 2 also shows
the power supply and points out the need for dc sources
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7. NO. I . JANUARY 1992
SE
TABLE I
RELATIONSHIPS
BETWEEN NPC OUTPUT VOLTAGES AND SWITCHING STATES
Switches
output S , and S7 and Sz and Ss and
Voltages Not S5 Not S3 Not S6 Not S4
+2E
+E
+E
0
0
0
-E
-E
-2E
isolated from one another, obtained by using a two-sec-
ondary transformer. A series connection of two H-bridge
inverters provides a five-level output voltage; in this case,
16 (2 X 2 x 2 x 2) different switching configurations are
possible, as shown in Table 11.
Which of the two structures presented in Figs. 1 and 2,
respectively, is to be preferred? A comparison can be
made only if five voltage levels are sufficient for the spe-
cific load considered. In this case, the NPC inverter must
use four more diodes, two more power capacitors, and
suitable networks to achieve a correct static balance of the
DC-link voltage between the series-connected devices and
a correct voltage sharing between the capacitors. Instead,
the series connected H-bridge inverters require dc sources
isolated from one another, and this may be a very expen-
sive feature. Finally, in the latter case, the possibility of
using 16 (instead of 9) different switching configurations
allows a better optimization of the control strategies, as
will be explained later on. If there are more than five re-
quired levels, the latter structure turns out to be surely
preferable in that it can easily be extended to the genera-
+
tion of (2n l)-level voltage waveforms, by series con-
necting n H-bridge inverters; such extension is much more
difficult in the case shown in Fig. 1.
MARCHESONI: HIGH-PERFORMANCE CURRENT CONTROL TECHNIQUES 191

LOAD

Fig. 2. Series connection of H-bridge inverters.

TABLE I1 work at an infinite switching frequency, exhibits an ex-

RELATIONSHIPS
BETWEEN SERIES-CONNECTED H-BRIDGES
OUTPUT
VOLTAGES STATES
A N D SWITCHING
tremely restrictive parameter, namely, the minimum lock-
out time, which is the minimum duration of the conduc-
output S , and S, and Ss and S5 and tion intervals that the semiconductor must observe in order
Voltages Not S3 Not S2 Not S, Not S, to ensure a proper functioning of the snubber networks.
+2E 1 1 1 1 The minimum lockout time may be considerable in the
+E 0 1 1 1 case of GTO devices. Switching required by control sys-
+E 1 0 1 1 tem might then occur, in specific situations, with such a
+E 1 1 0 1
+E 1 1 1 0 delay that it could notably degrade the system perfor-
0 0 1 1 0 mances. Let us consider a variable impedance load (e.g.,
0 0 0 1 1 an induction motor). Under low-impedance conditions
0 1 0 0 1
0 1 1 0 0 (i.e., near zero speed), the load current can strictly follow
0 0 1 0 1 the current reference only at high switching frequencies,
0 1 0 1 0 especially if the value of the imposed current reference is
-E 0 1 0 0
-E 0 0 1 0 low. But the minimum lockout time does not allow the
-E 0 0 0 1 use of high switching frequencies; in general it slows
-E 1 0 0 0 down the system responses, particularly in the case of
- 2E 0 0 0 0
current reference sudden variations, which may occur in
applications related to nuclear fusion experiments [4].
111. DEVELOPMENT OF A HIGH-PERFORMANCE An optimized modulation strategy can face the problem
MULTILEVEL MODULATION in an adequate way. If the load impedance is low, if the
We henceforth consider a series connection of two H- converter is able to deliver multilevel voltage waveforms,
bridge inverters, which provides five-level voltage wave- and, above all, if the control logic is “intelligent”
forms; such a structure allows an immediate extension of enough, the load will have to be fed only by the lowest
the developed current control techniques to a series con- levels, i.e., levels +E and 0, in the present case. Table
nection of n H-bridge inverters. The starting point toward I1 shows that there are four switching configurations that
the design of an adequate current control strategy could produce voltage levels *E, and six switching configura-
be the following: according to the difference between the tions that produce voltage level 0. If the switching se-
instantaneous load current value and its reference value, quences are optimized in such a way that the commuta-
a control system should suggest what is the most suitable tions of a given semiconductor device are separated by as
voltage level required. Then it could perform a direct and long time intervals as possible (thanks to the possibility
univocal connection between the required level and one of choosing from among the various alternative configu-
of the 16 switching configurations available. However, in rations), then the problem arising from the minimum
this way, only 5 switching configurations would be uti- lockout time will be minimized.
lized, and this would not be convenient for two precise
reasons. A . Optimized Cyclic Use of the Switches
First, the semiconductor devices would be employed in All the simulation results presented in the paper have
an asymmetrical way, hence their thermal problems and been obtained by using the general purpose program
wear would be asymmetrical, too. Second, it is well EMTP [5], [6]. The structure of the converter utilized is
known that a real component, besides being unable to the one shown in Fig. 2; the dc sources obtained via rec-
192 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. I , NO. I. JANUARY 1992

0
1 1 1 1 1 1 , 1 1 1 1 1 1 1 ~ ~ ~ ~ ~ ~ ~
'2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00
TIME c s l *io-2

tification and filtering have been assumed to be equal to
E z 700 V, and switches have been assumed to be two
parallel-connected IGBT's (main rated values: V,,, =
1000 V, I, = 200 A). The minimum lockout time and the
switching delays have been taken into account in the
models implemented, and the load has been assumed to
be always ohmic-inductive, at several power factors.
Fig. 3 shows the first approach to the problem: a hys-
teresis band of amplitude 26,, has been created around the
current reference. If we define the current error as E = Zref
- Zload, the following conditions are observed by the com-
mon two-level bang-bang controllers:
1) If E > ah, set the voltage to the upper level.
2) If E < -6h, set the voltage to the lower level.
This approach can be extended to a multilevel VSI, as
follows:
1) If E > 6 h , increase the voltage by one level.
2) If E < - A h , decrease the voltage by one level.
In Fig. 3(a), increments are marked with circles and
decrements with triangles; 3(b) gives the related output
voltage.
An optimized cyclic use of the switches has been stud-
ied in order to space out temporally their commutations
as much as possible. Table I1 points out that four switches,
S I , S4, Sg, and S5, are all characterized by a peculiar prop-
erty. Let us denote the possible output voltages by num-
bers, as follows:
1) Level '-2E: number 0
2) Level -E: number 1
3) Level 0: number 2
4) Level +E: number 3
5) Level +2E: number 4
The number related to each voltage level can be ob-
tained by adding up the logic levels of the four switches
considered, which have all the same effect on the con-
verter output voltage; this operation makes it possible to
synthesize the optimized control strategy in a simple way.
MARCHESONI: HIGH-PERFORMANCE CURRENT CONTROL TECHNIQUES 193

t
Fig. 4. Schematic converter representation.

XONOSTABLE RING COUNTER

+ MOD 4
+ MULTIVIBRATOR urn On Switch 5

/
2
INITIALIZATION
Triggerable from
Leading Edge Pulses \.
M‘

Off Switch
Off Switch
Off Switch
Off Switch
I U - (----

PULSES AND

PULSES AND

PULSES AND

PULSES AND

Fig. 5. Control system (A) block diagram with switching optimization

Fig. 4 shows a very schematic representation of the con-
verter structure where only the switches that give a posi-
tive contribute to the output voltage, S I , S4, S8, and S5,
are displayed. The converter can be regarded as a clock
with two pointers, A (“turn-off pointer”) and B (“turn-
on pointer”). The switches after pointer A (clockwise)
and before pointer B must be considered turned on, the
other turned off. Every time the voltage level must rise,
control system should cause the pointer B to advance
(c.w.) by a 90” position and to turn on the surpassed
switch; every time the voltage level must go down, con-
trol system should cause the pointer A to advance (c.w.)
by a 90” position and to turn off the surpassed switch.
Pointer A always pursues pointer B. Fig. 4 refers to a case
where output voltage level is 0 (number 2) and Fig. 5
shows the block diagram of the control system (A) that
allows the optimized cyclic use of the switches; in partic-
ular, the rise and fall inhibits can be noted, which cause
the pointer B(A) to stop when the output voltage is at its
maximum (minimum) value 2E ( - 2 E ) , independently
from the circuit inputs.
This current control technique seems to be very inter-
1 94 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7. NO. 1 , JANUARY 1992

0
0
f

0
N
f

"
<
Y O

C O
Z m
a
W

E 0
3 O

Ud
04 1

209
*
0
N

0
s 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
c 10 0.04 0.08 0.12 0.16 0.20 0.24 0.28 4.32 0.56 0.40
TIME C s l *lo-'
(a)
0

(b)
Fig. 6. Loss of control in multilevel modulation

esting, but it does not lead to a reliable and robust oper-
ation under realistic conditions, as noise may affect the
synchronization between converter pointers and switch
states. Moreover, under certain load conditions, some
instabilities may occur, which make the system very un-
reliable. Fig. 6(a) gives the load current in the case of
instabilities (the dashed line indicates the alternating ref-
erence value); the system is controlled by means of the
scheme presented in Fig. 5. At the instant t G 7 ms, the
load current becomes higher than its reference plus ah, so
the control system decreases the output voltage by one
level, as shown in Fig. 6(b). But this decrease is not suf-
ficient to make the current enter the hysteresis band again,
so the control is lost. This phenomenon takes place es-
pecially on the falling side of the absolute value of the
reference wave [ 101 and can be enhanced by the semicon-
ductors' minimum lockout times and by the switching de-
lays. In the simulation presented in Fig. 6, the minimum
lockout time is assumed to be equal to 40 ps, which is a
typical value for high-frequency GTO's; moreover, it is
assumed that = 3 A, R = 2 Q,L = 10 mH, and that
the current reference is a sine with a peak value equal to
300 A and a frequency equal to 50 LL(as in all the sim-
ulations reported in the following).
A possible modification to the control system (A) is il-
lustrated in Fig. 7, which shows a slightly altered part of
the scheme in Fig. 5 . In this way, when the load current
is outside the hysteresis band, the voltage-controlled os-
cillators periodically increase or decrease the output volt-
age by one level, according to a suitably fixed period. So
the system does not lose control, and the waveforms
shown in Fig. 8 can be obtained, under the same condi-
tions as for the test presented in Fig. 6. It is very difficult
to distinguish between the load current and its alternating
reference (dashed line in Fig. 8(a)). All the components
operate at the same switching frequency, with very simi-
lar duty cycles to the one given in Fig. 8(d), which shows
the firing pulses related to switch 1. A comparison be-
tween the average switching frequency of a single device
(about 600 Hz) and the average current ripple frequency
(which, from the current error given in Fig. 8(c), can be
estimated to be equal to about 2 150 Hz) further points out
the advantages of the optimized control technique.
Fig. 9 presents other simulation results, obtained under
MARCHESONI: HIGH-PERFORMANCE CURRENT CONTROL TECHNIQUES

/
Triggerable from
vco
'ref E y'

Leading Edge Pulses \

,
vco
\

4-
bh
-
4+ -
-* MONOSTABLE
bMULTIVIBRATOR

Fig. 7 . Control system (A) stabilization.

-
Y)

'2100 ' 2.;0 ' 2.;0 ' 2.d0 ' 2.80 3.00
1 I I
3.20
I
3.40
I 1 1
3.60
' "
3.80
'
4.00
TIME C s l
(b)
Fig. 8. Waveforms obtained by imposing a sine current reference with a
peak value equal to 300 A.
196 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. I, NO. I , JANUARY 1992

I]
0
0

00

0
0

0
1 1 I I T I 1 I I
3.40

SC

0
i . . -
2.
1
-
3.00

Fig. 8. (Continued.)
r
3.60 3.1
. l
4.00

0
0
1 1 1 1 1 1 1 1 1 1 1 1 1 ~ ~ ~ ~ Q 1
‘2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00
TIME [SI
(a)
Fig. 9. Waveforms obtained by imposing a sine current reference with a
peak value equal to 150 A.
MARCHESONI: HIGH-PERFORMANCE CURRENT CONTROL TECHNIQUES

-.
c 0-
27
0-

, I I I I V ! 1 ~ 1 ' " " ' " '

, I

' 3.20 3.40 3.60 3.80 4.00

TIME C s l *lo+

Y
-

'r

1 3.60 1
2.1 3.' 1 3.40 I 4 . 10
T 1E [ * I

(d)
Fig. 9 . (Continued.)
198 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. I, NO. 1, JANUARY 1992

r l -

r r r l l r l l l l l l l l l
‘2!00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00
TIME C s l *lo-’

(a)

~
c ~ , , , , , , , , , , , , , , , ~ , , , ,
‘2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00
TIME C s l *lo-’
(b)
. Fig. 10. Multilevel modulation (B).

the same load conditions but imposing a current reference
of halved amplitude. If the rms value of the current re-
quired is lower (the load being the same), the rms value
of the voltage must also be lower. Fig. 9(b) shows that
the control technique is self-adapting in an automatic and
natural way; therefore, the converter feeds the load by
using the lowest voltage levels only ( + E and 0). The re-
sults shown exhibit the high-performance behavior of the
whole system, but it is worth noting that the parameters
of the VCO’s displayed in Fig. 7 are very difficult to set
for variable frequency applications.
E. Improvements in Robustness and Reliability
A very robust control system can be realized if the re-
lated most important choices are not entrusted to sequen-
tial digital elements, such as counters and flipflops, which
may change their state in consequence of noise or other
disturbances. In the present case, a right choice of the
most suitable voltage level must be made, even at the sac-
rifice of switching optimization. This objective will surely
be obtained if the following control strategy is adopted:
three bands of amplitude 26 must be created and centered
on the current reference (as shown in Fig. 10(a)), in such
a way as to subdivide the surface I-t into five different
regions, i.e., as many as the possible voltage levels. De-
pending on the region where the load current is, the con-
verter must feed the load at a well-defined voltage level
as illustrated in Fig. 10. Moreover, suitable hysteresis
bands must be created and centered on the boundaries of
the various bands of amplitude 26 in order to avoid infinite
switching frequencies. Fig. 10 presents a simulation re-
sult obtained by using large 6 values, which aid in better
.
understanding the control strategy. Actually, 6 can as-
sume very low values, resulting in a minimum harmonic
distortion, which on the contrary mainly depends on the
amplitude 8h of the hysteresis bands created. On the other
hand, 6 cannot be too low as switching delays may cause
the loss of multilevel modulation. Fig. 11 shows the sim-
ple block diagram of the scheme on which this strategy
(B) is based: the combinatorial network utilizes the four
MARCHESONI: HIGH-PERFORMANCE CURRENT CONTROL TECHNIQUES
+ @I:
.r *I.
Fig. 1 1 . The robust and reliable control system (B) block diagram.
logic variables, xI,x2, x3, and x,, in an obvious way,
which yet does not permit the optimized cyclic use of the
switches. This control scheme can be modified, however,
and switching optimization can be achieved in another,
more reliable, way.
As previously pointed out, the most suitable voltage
level must be selected by the control system without the
use of sequential digital. elements; this choice must be
based only on the states of the logic variables xl,x2, x3,
and x4. Switching optimization can be reached by a sec-
ond step, using the scheme depicted in Fig. 12. The sche-
matic representation of the converter as a clock with two
pointers still applies, but only pointer A is made to move
through transitions of the logic variables x,. If we define
N I as the number already associated with every voltage
level, and @A and OB as the angular positions of pointers
A and B, then we can easily derive OB as expressed by
(l), where N , represents the required voltage level, and
angular displacements are assumed to be positive if clock-
wise.
@B = OA + NI X 90”. (1)
Fig. 12 shows that pointer A moves only when the out-
put voltage has to be decreased, according to its own
function of “turn-off pointer.” All the performances pre-
viously described can then be obtained by suitably pro-
gramming the read-only memory, as shown in Table 111.
Fig. 13 gives the results obtained by means of the im-
proved control scheme, during the same test as considered
in Fig. 8, by assuming 6 = 1 A < 6,, = 3 A. The load
current and the output voltage waveforms are very close
to those shown in Fig. 8; only the current error, given in
Fig. 13(c) on enlarged scale, points out the different con-
x2 COMBINATORIAL
NETWORK
FIRING PULSES
and F
x3 w
LOCK OUT
CIRCUITS
trol technique adopted. The current error resulting from
the present control strategy is larger than the one given in
Fig. 8(c). Nevertheless, an accurate harmonic analysis has
demonstrated that the THD (total harmonic distortion)
values of the current and voltage waveforms are definitely
comparable in the two cases. The only drawback lies in
the fact that the fundamental harmonic of the load current
in Fig. 13(a) is slightly lower (II = 298.22 A) than the
value required (IIRf= 300 A), whereas in the first case
(Fig. 8(a)) it is I, =
300.35 A. It is worth emphasizing
that both schemes A and B allow the same switching op-
timization; the latter is then to be preferred in that it ex-
hibits higher robustness and reliability.
C. Further Rejinements
The average value of the current error given in Fig.
13(c) approaches zero only if fundamental periods are
considered. It has already been pointed out that this does
not increase the THD value and that it only causes a de-
crease in the fundamental harmonic component. This
problem may become a severe one if more than five volt-
age levels are to be employed, in which a case a non-
negligible phase lag between the load current and its ref-
erence may occur, as shown in Fig. lO(a), where the re-
sults yielded by the use of too large 6 values are similar
to those obtainable by utilizing more voltage levels. The
solution to the problem has been reached by creating a
dummy current reference, according to the scheme pre-
sented in Fig. 14. In fact, from Fig. 10 it appears evident
that the load current always slides on the dashed lines that
represent IEf + m6, where m can be f 1 or 3. If the
sliding motions occurred exactly on the current reference,
~

200 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7, NO. 1, JANUARY 1992

Triggerable from
Trailing Edge Pulses
I

x1 -- MONOSTABLE
MULTIVIBRATOR

x2 MONOSTABLE
7
MULTIVIBRATOR

COUNTER
MOD 4

x3 -
7
MONOSTABLE
MULTIVIBRATOR y1 y2

x4 -- MONOSTABLE
MULTIVIBRATOR

+
* ROM LOCK OUT
CIRCUITS
.
’
FIRING PULSES

TABLE I11 the current error would be close to the smaller one given
ROM PROGRAMMING
in Fig. 8(c) and the control system would not be affected
ROM ROM by the aforementioned drawbacks. Therefore, a dummy
Input output current reference must be created, Z i f = Zref - m6; in this
way, the load current will always slide on the required
YI Y2 XI 12 13 x4 SI s4 ss s5 curve (2).
0 0 0 0 0 0 0 0 0 0
+ m6 + m6
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
:
0
-2E
Zif = - m6 = ZEf.
The right value of m can easily be determined; in fact,
(2)

0 0 1 0 0 0 0 1 0 0 one can notice that when the load current continually in-
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0 ; -E
tersects the curve ,Z +
m6 (see Figs. 10, l l ) , a contin-
1 1 1 0 0 0 1 0 0 0 uous switching of only one of the logic variables x,occurs
0 0 1 1 0 0 0 1 1 0
with the biunivocal correspondence i m. The scheme
0 1 1 1 0 0 0 0 1 1 presented in Fig. 14 shows how it is possible to utilize
1 0 1 1 0 0 1 0 0 1 O the continuous switching of x,in order to identify the right
1 1 1 1 0 0 1 1 0 0 value of m ; the right dummy current reference Z i f can
0 0 1 1 1 0 0 1 1 1 then be created, which will provide a suitable solution to
0 1 1 1 1 0 1 0 1 1
1 0 1 1 1 0 1 1 0 1 E any problem.
1 1 1 1 1 0 1 1 1 0 Figure 15 gives the simulation results obtained by per-
0 0 1 1 1 1 1 1 1 1 forming the above correction under the same load condi-
0 1 1 1 1 1 1 1 1 1 tions as used in the previous tests. Fig. 15(a) shows the
1 0 1 1 1 1 1 1 1 1 load current, ZEf and Zif on a very large scale. From Fig.
1 1 1 1 1 1 1 1 1 1
15(c), which presents the output voltage in a whole fun-
MARCHESONI: HIGH-PERFORMANCE CURRENT CONTROL TECHNIQUES 20 I

I
1 1 , 1 1 1 , 1 1 1 1 1 1 1 1 1 1 1 1 1 1
'2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00
TIME C s l *IO-?
(b)

J I I I I J I I I I I I I I I I
0 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00
TIME C s l
(C)
Fig. 13. Waveforms obtained by using control system (B)

damental period, one can notice that, just before the in- tween the voltage levels 0 and +E. This results in a con-
stant t = 39.6 ms (at which the time window in Fig. 15(a) tinuous switching of the logic variable x 3 , which causes
and (b) begins), a continuous commutation occurs be- the current reference correction to become m6 = -1 A
 202 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7. NO. I , JANUARY 1992

Tr iggerable from
both Leading and
Trailing Edge Pulses
1
I +3b

x1 MONOSTABLE
MULTIVIBRATOR ' S1

FF 1
Q1'

-
Q1 +b
- r-L-
x2 MONOSTABLE -S2 4 2 ' 2 I
MULTIVIBRATOR FF2
-
R2 Q2

I I I I I
MONOSTABLE
MULTIVIBRATOR

MONOSTABLE
MULTIVIBRATOR

Fig. 14. Dummy current reference generation in control system (B).

0
9-

0
?-
Y)

" -
C O
-9
y1-
c-
Z '
W -
E

010
30

0
In
, I l l
'39.60 39.64 39.68 39.72 39.76 39.80 39.84 39.88 39.92 39.96 40.00
TIME c s i
(a)
Fig. 15. Waveforms obtained by introducing the current reference correc
tions in control system (B).

(hence m = - 1, as 6 = 1 A), consistently with the scheme
depicted in Fig. 14. The current reference correction m6
is shown in Fig. 15(b), where one can see that, at the
instant t = 39.6 ms, it takes on the expected value. Sub-
sequently, the load requires a continuous commutation
between the voltage levels +E and +2E; due to such
commutation, the load current (with no corrections) would
slide on the curve Zref - 36. But the continuous switching
of x4 makes it possible to identify the right value of m6
(Fig. 15(b)) and then to create the most suitable dummy
current reference, as shown in Fig. 15(a). As a conse-
quence, the load current begins to slide on the curve Z$
- 36, which, in this case, corresponds exactly to the cur-
rent reference ZRf.
The beneficial effects of the foregoing correction are
illustrated in Fig. 15(d), which gives the current error in
a fundamental period: it can be seen the difference be-
tween this figure and Fig. 13(c), which gives the current
MARCHESONI: HIGH-PERFORMANCE CURRENT CONTROL TECHNIQUES

0-
Y)

-0
4 9-
U"

-
z -
0

39.60 39.64 39.68 39.72 39.76 39.80 39.84 39.88 39.92 39.96 40.00
TIME C s l

(b)
0

I
I ! , , , , , , , ~1 1 I I 1 I I I I
'2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3.60 3.80 4.00
TIME C S J
(C)

......................
c

2.00 2.20 2.40 2.60 2.80 3.00 3.20 3.40 3,60 5.80 4.00
TIME [SI *lo-'

(d)
Fig. 15. (Conrinued.)

error for the same test but with no corrections. In the last distinguished from the waveforms presented in Figs. 8(a)
considered case, the average value of the current error and 13(a); qnyway, its fundamental harmonic is Z, E
approaches zero even when current ripple periods are con- 300.52 A, whereas the THD value is comparable to those
sidered. The load current is not shown, as it cannot be calculated for the other cases.
204 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 7. NO. I , JANUARY 1992
IV. CONCLUSIONS
Several high-performance current control techniques
have been developed for applications to multilevel high-
power VSI’s. The logical sequence of the design choices
had been described, resulting in a very robust and reliable
control system that allows an adequate switching optimi-
zation, excellent dynamic responses, and high accuracy
in steady-state operation. The advantages of using various
accessible dc potentials have been fully exploited. The
validity of the proposed schemes has been confirmed by
digital simulations, which refer to the generation of five-
level voltage waveforms; however, the current control
strategies developed can easily be extended to any mul-
tilevel inverter structure, even in the case of n-level volt-
age waveforms and three-phase systems.
REFERENCES
[ l ] A. Kernick, D. L. Stechschulte, and D. W Shireman, “Static in-
verter with synchronous output waveform synthesized by time-opti-
mal-response feedback,” IEEE Trans. IECI, vol. IECI-24, no 4, pp.
297-305, Nov 1977.
[2] D. M. Brod and D. W. Novotny, “Current control of VSI-PWM
inverters, ” IEEE Industry Applications Society Annu. Meeting Conf.
Rec., Chicago, IL, Sept./Oct. 1984, pp. 418-425.
[3] M Boussak, G A. Capolino, M. Marchesoni, M. Mazzucchelli, and
P. Pozzobon, “Vector control method in high power dnves for in-
dustrial applications,” Proc. Int. Con& on Electrical Machines, Pisa,
Italy, vol. 1, Sept. 1988, pp. 349-354
[4] M Marchesoni, M. Mazzucchelli, and S. Tenconi, “A nonconven-
tional power converter for plasma stabilization,” IEEE Trans. Power
Electron., vol. 5, no 2, pp. 212-219, Apnl 1990.
[5] EMTP User’s Manual, Bonneville Power Administration, Portland,
OR, June 1984.
[6] EMTP User’s Book, Bonneville Power Administration, Portland, OR,
June 1984.
[7] P. M. Bhagwat and V. R. Stefanovic, “Generalized structure of a
multilevel PWM inverter,” IEEE Trans. Industry Applicarions, vol.
IA-19, no. 6, pp. 1057-1069, Nov./Dec. 1983.
[8] A. Nabae, I. Takahashi, and H. Akagi, “A new neutral-point clamped
PWM inverter,” IEEE Trans. Industry Applications, vol. IA-17, no.
5, pp. 518-523, Sept./Oct. 1981.
[9] J. Holtz, S . Stadtfeld, and P. Lammert, “An economic very high
power PWM inverter for induction motor drives,” European Power
Electronics Conf. Rec., Brussels, Belgium, Oct. 1985, pp. 3.75-3.80.
[lo] R. G . Palaniappan and J. Vithayathil, “A control strategy for refer-
ence wave adaptive current generation,” IEEE Trans. IECI, vol.
IECI-27, no. 2, pp. 92-96, May 1980.
Mario Marchesoni (M’89) was born in Genoa,
Italy, on June 15, 1959. He received the B.S E.E.
degree in electncal engineenng cum laude in 1986
and the Ph.D. degree in electncal engineenng in
the area of power electronics in 1990 both from
the University of Genoa.
After graduation he began his research activity
in the Electncal Engineering Department of the
University of Genoa. He is presently working as
a consultant in the aforementioned department and
his research interests are mainly centered on power
electronics, rotating machinery, and automatic control, particularly refer-
nng to high-power converters, robotics, and electric vehicle propulsion.
He has published more than 30 papers in these fields.