PD - 95485A

IRF1407PbF
Typical Applications
l Industrial Motor Drive
HEXFET® Power MOSFET
D
Benefits
VDSS = 75V
l Advanced Process Technology
l Ultra Low On-Resistance
l Dynamic dv/dt Rating RDS(on) = 0.0078Ω
G
l 175°C Operating Temperature
l Fast Switching ID = 130A†
l Repetitive Avalanche Allowed up to Tjmax S

Description
This Stripe Planar design of HEXFET® Power MOSFETs
utilizes the lastest processing techniques to achieve
extremely low on-resistance per silicon area. Additional
features of this HEXFET power MOSFET are a 175°C
junction operating temperature, fast switching speed and
improved repetitive avalanche rating. These benefits
combine to make this design an extremely efficient and
reliable device for use in a wide variety of applications. TO-220AB

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 130†
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 92† A
IDM Pulsed Drain Current  520
PD @TC = 25°C Power Dissipation 330 W
Linear Derating Factor 2.2 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 390 mJ
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy‡ mJ
dv/dt Peak Diode Recovery dv/dt ƒ 4.6 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting Torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.45
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62

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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 75 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.09 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.0078 Ω VGS = 10V, ID = 78A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 74 ––– ––– S VDS = 25V, ID = 78A
––– ––– 20 VDS = 75V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 60V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 160 250 ID = 78A
Qgs Gate-to-Source Charge ––– 35 52 nC VDS = 60V
Qgd Gate-to-Drain ("Miller") Charge ––– 54 81 VGS = 10V„
td(on) Turn-On Delay Time ––– 11 ––– VDD = 38V
tr Rise Time ––– 150 ––– ID = 78A
ns
td(off) Turn-Off Delay Time ––– 150 ––– RG = 2.5Ω
tf Fall Time ––– 140 ––– VGS = 10V „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package G

LS Internal Source Inductance ––– 7.5 –––

and center of die contact S

Ciss Input Capacitance ––– 5600 ––– VGS = 0V

Coss Output Capacitance ––– 890 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 190 ––– ƒ = 1.0KHz, See Fig. 5
Coss Output Capacitance ––– 5800 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0KHz
Coss Output Capacitance ––– 560 ––– VGS = 0V, VDS = 60V, ƒ = 1.0KHz
Coss eff. Effective Output Capacitance … ––– 1100 ––– VGS = 0V, VDS = 0V to 60V
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 130†

(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 520

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 78A, VGS = 0V „
trr Reverse Recovery Time ––– 110 170 ns TJ = 25°C, IF = 78A
Qrr Reverse RecoveryCharge ––– 390 590 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by … Coss eff. is a fixed capacitance that gives the same charging time
max. junction temperature. (See fig. 11).
as Coss while VDS is rising from 0 to 80% VDSS .
‚ Starting TJ = 25°C, L = 0.13mH
† Calculated continuous current based on maximum allowable
RG = 25Ω, IAS = 78A. (See Figure 12).
junction temperature. Package limitation current is 75A.
ƒ ISD ≤ 78A, di/dt ≤ 320A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C ‡ Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
„ Pulse width ≤ 400µs; duty cycle ≤ 2%. avalanche performance.

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1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
100 5.0V 100 5.0V
BOTTOM 4.5V BOTTOM 4.5V
4.5V
4.5V

10 10

20µs PULSE WIDTH 20µs PULSE WIDTH

Tj = 25°C Tj = 175°C
1 1
0.1 1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000.00 3.0
I D = 130A

T J = 25°C
ID, Drain-to-Source Current (Α)

2.5
TJ = 175°C
RDS(on) , Drain-to-Source On Resistance

2.0
(Normalized)

100.00 1.5

1.0

0.5
VDS = 15V
20µs PULSE WIDTH V GS = 10V
10.00 0.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
3.0 5.0 7.0 9.0 11.0 13.0
TJ, Junction Temperature ( °C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

vs. Temperature
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100000 15
VGS = 0V, f = 1 MHZ ID = 78A
VDS = 60V
Ciss = Cgs + Cgd, Cds SHORTED VDS = 37V
Crss = Cgd VDS = 15V
12
Coss = Cds + Cgd

VGS , Gate-to-Source Voltage (V)

C, Capacitance(pF)

10000
Ciss 9

6
Coss
1000

3
Crss

100 0
0 40 80 120 160 200
1 10 100
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.00 10000

OPERATION IN THIS AREA

ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

T J = 175°C LIMITED BY R DS(on)

100.00 1000

10.00 100
T J = 25°C 100µsec

1.00 10 1msec
Tc = 25°C
VGS = 0V Tj = 175°C
10msec
Single Pulse
0.10 1
0.0 1.0 2.0 3.0 1 10 100 1000
VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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140
RD
LIMITED BY PACKAGE VDS
120
VGS
D.U.T.
100
RG
+
-VDD
I D , Drain Current (A)

80
10V
Pulse Width ≤ 1 µs
60 Duty Factor ≤ 0.1 %

40 Fig 10a. Switching Time Test Circuit

20 VDS
90%
0
25 50 75 100 125 150 175

TC , Case Temperature ( °C)

10%
VGS
Fig 9. Maximum Drain Current vs.
td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

D = 0.50
(Z thJC)

0.1 0.20

0.10
Thermal Response

0.05
SINGLE PULSE
0.02 (THERMAL RESPONSE)
0.01 P DM

0.01
t1

t2

Notes:
1. Duty factor D = t1 / t 2
2. Peak T J = P DM x Z thJC +TC
0.001
0.00001 0.0001 0.001 0.01 0.1 1

t1, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF1407PbF

650
15V
ID
TOP 32A
55A
L DRIVER 520 BOTTOM 78A
VDS

EAS , Single Pulse Avalanche Energy (mJ)

RG D.U.T + 390
V
- DD
IAS A
20V
tp 0.01Ω
260

Fig 12a. Unclamped Inductive Test Circuit

V(BR)DSS
130
tp

0
25 50 75 100 125 150 175
Starting T , Junction
J Temperature ( °C)

I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
vs. Drain Current
QG

10 V
QGS QGD 3.5
VGS(th) Gate threshold Voltage (V)

VG
3.0

Charge ID = 250µA

Fig 13a. Basic Gate Charge Waveform 2.5

Current Regulator
Same Type as D.U.T.

50KΩ
2.0
12V .2µF
.3µF

+
V
D.U.T. - DS
1.5
VGS -75 -50 -25 0 25 50 75 100 125 150 175 200
3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage vs. Temperature
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1000

Duty Cycle = Single Pulse

Allowed avalanche Current vs

Avalanche Current (A)

100 0.01 avalanche pulsewidth, tav

assuming ∆ Tj = 25°C due to
avalanche losses

0.05

10
0.10

1
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 15. Typical Avalanche Current vs.Pulsewidth

400 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
ID = 78A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

300 temperature far in excess of Tjmax. This is validated for

every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
200 3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
100
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0
tav = Average time in avalanche.
25 50 75 100 125 150 175
D = Duty cycle in avalanche = t av ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3·BV·Zth]
vs. Temperature EAS (AR) = PD (ave)·tav
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IRF1407PbF

Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T* • Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• ISD controlled by Duty Factor "D" V DD
-
• D.U.T. - Device Under Test
V GS

* Reverse Polarity of D.U.T for P-Channel

Driver Gate Drive

P.W.
Period D=
P.W. Period

[VGS=10V ] ***

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
[VDD]
Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% [ISD]

*** VGS = 5.0V for Logic Level and 3V Drive Devices

Fig 17. For N-channel HEXFET® power MOSFETs

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TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

TO-220AB Part Marking Information

EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789 INT ERNAT IONAL PART NUMBER
ASS EMBLED ON WW 19, 2000 RECT IF IER
IN T HE ASS EMBLY LINE "C" LOGO
DAT E CODE
Note: "P" in assembly line position YEAR 0 = 2000
AS SEMBLY
indicates "Lead - Free" LOT CODE WEEK 19
LINE C

TO-220 package is not recommended for Surface Mount Application.

Notes:
1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.07/2010
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