Reg. No. Reg. No.

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY SRM INSTITUTE OF SCIENCE AND TECHNOLOGY
CYCLE TEST – I Feb-2019 CYCLE TEST – I Feb-2019
VI Semester – Electronics& Communication Engineering VI Semester – Electronics& Communication Engineering
15EC327E – ASIC Design 15EC327E – ASIC Design
Duration: 45 Mins Max. Marks: 25 Duration: 45 Mins Max. Marks: 25
PART – A (5 X 1 = 5 Marks) PART – A (5 X 1 = 5 Marks)
Answer ALL Questions Answer ALL Questions
1. Which design style has the shortest time to market 1. Which design style has the shortest time to market
a.Full custom b. Standard Cell c. Gate array d. FPGA a.Full custom b. Standard Cell c. Gate array d. FPGA
2. OAI221 CMOS logic cell has how many transistor 2. OAI221 CMOS logic cell has how many transistor
a. 10 b.12 c.14 d.8 a. 10 b.12 c.14 d.8
3. Which design style has the longest manufacturing lead time 3. Which design style has the longest manufacturing lead time
a.Full custom b. Standard Cell c. Gate array d. a.Full custom b. Standard Cell c. Gate array d.
FPGA FPGA
4. Advantage of TG when compared to PT 4. Advantage of TG when compared to PT
a)less no. of Transistor b)Faster c)Easy to design d)passes a)less no. of Transistor b)Faster c)Easy to design d)passes
good 0 & 1 good 0 & 1
5. NMOS acts as ………….device 5. NMOS acts as ………….device
a)Pull up b)pull down c)pull back d)pull side a)Pull up b)pull down c)pull back d)pull side

PART – B (2 X 4 = 8 Marks) PART – B (2 X 4 = 8 Marks)

Answer ANY TWO questions Answer ANY TWO questions
6. Realize 2i/p XNOR and XOR using transmission gate. 6. Realize 2i/p XNOR and XOR using transmission gate.
7. Elucidate Photolithographic process. 7. Elucidate Photolithographic process.
8. List some of the Design rules followed while drawing layouts 8. List some of the Design rules followed while drawing layouts

PART – C (1 X 12 = 12 Marks) PART – C (1 X 12 = 12 Marks)

Answer ALL questions Answer ALL questions
9. a. Compare Full custom ASIC design style with Semicustom 9. a. Compare Full custom ASIC design style with Semicustom
ASIC style ASIC style
OR OR
b. Implement D latch and FF using Transmission gates b. Implement D latch and FF using Transmission gates