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TRAINERS
Since
23
Years

PHASE LOCK LOOP

MODEL-PLLDM100

More
than
2000 SIGMA TRAINERS
Trainers AHMEDABAD (INDIA)
 INTRODUCTION

This trainer has been designed with a view to provide practical and experimental knowledge of Phase Lock
Loop.

FEATURES

The schematic circuit diagram printed on P.C.B. for all terminals, switches, components and power
Supplies.
All ICs provided on sockets and possible to replace without opening the trainer board.
All Ics are visible from top and the pin extensions are available around ICs with diagrams.
All terminals (2 mm sockets) soldered properly to avoid loose connections.

SPECIFICATIONS

1. Power supply requirement : 230V AC, 50 Hz.

2. Built in IC based regulated Power supply : +5V and -5V DC/200 mA.
3. Following parts provided on Single PCB with connecting terminals.
PLL IC 565 - 1 No.
4. Variable Resistor and Capacitors.
5. Standard Accessories :
1. A User Manual.

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 CHAPTER-1

THEORY OF PHASE LOCK LOOP

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 EXPERIMENT - 1

AIM: To demonstrate the operation of Phase Lock Loop.

PROCEDURE:
(See Connection diagram CN1)

1. Connect Digital frequency counter at the VCO O/P connector.

Vary C1 and R1 to adjust VCO Frequency 12 KHz.

This is free running frequency of PLL.

2. Connect sine wave signal form external function generator at input terminals. Connect CRO Channel-1

at input terminals. Keep amplitude at 10Vpp.

3. Connect CRO Channel-2 at VCO output. Trigger CRO by channel-1.

4. Now vary frequency of input sinewave generator form 8 KHz to 16 KHz.

5. Note down the instant frequency when input and output signals locked. This will be 12KHz. Now vary

input frequency signal on both side of 12 KHz. The signals remain locked for some range. Then signals

become unlock. Note down these frequencies. The difference between these frequencies is capture range.

6. Also note that once signals are locked, both signals remain locked for some range. This is lock range.

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(Connection diagram CN1)