8 BIT RIPPLE CARRY ADDER

DATAFLOW
module s8bitrca(input [7:0]A, B, input Cin, output [7:0]S, output Cout);

wire c;

s4bitrca r1(A[3:0], B[3:0], Cin, S[3:0], c);

s4bitrca r2(A[7:4], B[7:4], c, S[7:4], Cout);

endmodule

module s4bitrca(input[3:0] A, B, input cin, output [3:0]sum, cout

);

wire c[2:0];

full_adder p(A[0], B[0], cin, sum[0], c[0]);

full_adder q(A[1], B[1], c[0], sum[1], c[1]);

full_adder r(A[2], B[2], c[1], sum[2], c[2]);

full_adder s(A[3], B[3], c[2], sum[3], cout);

endmodule

module full_adder(

input A,

input B,

input C,

output s,

output carry

);

assign s=A^B^C;

assign carry=(A&B)|(A^B)&C;

endmodule
SCHEMATIC

SIMULATION