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A low phase noise voltage controlled ring oscillator using subharmonic injection
locking mechanism in 90nm CMOS process

Conference Paper · January 2014

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 1st International Conference On Microelectronics, Circuits and Systems-Micro’2014

A Low Phase Noise Voltage Controlled Ring

Oscillator Using Sub- harmonic Injection
Locking Mechanism in 90nm CMOS Process
Sweta Padma Dash1, Subir Maity2, Sushanta.K.Mandal3,Subhrajyoti Das4,Adyasha Rath5
1,2,3,4,5
School of Electronics Engineering
KIIT University, Bhubhaneswar
1
swetapadmadsh@gmail.com,2skmaityfet@kiitac.in,3skmandalfet@kiit.ac.in,
4
subhrajyoti@live.in,5adyasharath.1690@gmail,com

Abstract—A low-phase-noise voltage controlled ring
oscillator (VCO) with subharmonic injection locking is
proposed in this work. The proposed VCO is implemented
in 90nm complementary metal oxide semiconductor
(CMOS) process technology and simulation is done on
Cadence Spectre environment. The VCO achieves a wide
operating frequency range from 2.4 GHz to 5.4 GHz at 1-V
supply voltage. The phase noise of -122.3 dBc /Hz at 1-
MHz-offest frequency was obtained at 445 MHz input
injection pulse with on time of 33.4 ps. The proposed VCO
consumes 2.47 mW power from 1-V supply at output
frequency of 5.34 GHz.
Keywords— Phase noise, ring oscillator, transition period,
subharmonic injection locking, voltage -controlled
oscillator
I. INTRODUCTION
Modern transceivers for wireless communication
contain low noise amplifier, power amplifier, mixers,
filters and phase-locked loops(PLL)[3]. Designing
voltage-controlled ring oscillators (VCOs) for wireless
communication is always desirable but most challenging
because of their requirement high-frequency operation
with low phase-noise and small power consumption[1].
LC VCOs are typically utilized in wireless transceivers
due to their good phase noise performance [2]. However,
some disadvantages are there in LC VCO. The
frequency tuning range of LC VCOs is relatively low,
which further decreases with the supply voltage.
Furthermore, the phase noise performance of the
oscillators highly depends on the quality factor of on-
chip spiral inductors, so extra processing steps are done
for which LC VCOs occupy a large chip area,
regardless of scaling [3]. On the other hand, a wide
tuning range is offered by ring VCOs and occupies a
small chip area, and their power consumption
substantially decreases with scaling [8]. It improves
both the cost and the yield of the ring VCOs.
Owing to these attributes, ring VCOs are a popular
candidate for implementation in scaled CMOS.
Unfortunately, because of their low quality factor they
exhibit poor phase noise performance. Thus, the phase
noise of ring VCOs is the key issue compared to LC
VCOs. Nevertheless the low phase-noise ring VCO can
be obtained if some noise-suppression mechanism can
be applied [10]- [11].
This paper concerns a method to lower phase noise by
injection locking mechanism method. The delay cell
used here uses the method that by reducing the output
voltage swing and increasing channel thermal noise of
the transistor the phase noise of the ring oscillator can
be improved by maximizing the output voltage swing
and minimizing the amount of noise injected during
output voltage transitions [12]. However, the noise
performance of the design in [12] is limited by the delay
cells, which inject a substantial amount of noise during
the transition periods of the VCO. In this work an
injection locking mechanism is used to improve the
phase-noise of the ring VCO.
The rest of the paper is organized as follows. Section II
describes about the design consideration and
implementations of oscillators. Section III describes
the subharmonic injection locking technique. Section IV
presents the structure and the operation principles of the
proposed VCO .Section V gives the measurement
results and discusses the performance of the proposed
VCO in comparison with other ring VCOs in
accordance with technology development. Finally,
conclusions are provided in Section VI.
II. . DESIGN CONSIDERATION AND
IMPLEMENTATION
A. Qualitative Analysis On Delay Cell Of VCRO
A qualitative analysis of delay cell of ring VCO is
essential for estimation of output frequency of VCO and
also relationship between control voltage and output
frequency. A single delay cell can be analyzed using
half circuit approach. Fig . 1 shows the schematic of the
delay cell proposed by Hajimiri .
Assuming non-saturation region of the delay cell
operation of transistor PM0 and PM3 on resistance can
be written as:
RPM0,PM3=1/[µp.Cox.(W/L)PM0,PM3(0-Vdd-Vtp)] (1)
 1st International Conference On Microelectronics, Circuits and Systems-Micro’2014
Similarly if PM1 transistor operates in non-saturation
region it acts as a nonlinear resistor whose resistance
can be controlled by control voltage input Vctrl and
resistance of PM1 can be written as:
RPM1=1/[µp.Cox.(W/L)PM1(Vctrl-Vdd-Vtp)]
Where Vtp is the threshold voltage of PMOS ,Vdd is the
supply voltage , µp is surface hole mobility in PMOS
transistor, Cox is gate oxide capacitance per unit area,
W and L denotes effective channel width and channel
length of each MOS transistor.
So total equivalent resistance in pull up path can be
written as:
Rpull-up=(RPM0+RPM1)||RPM3
Similarly assuming non-saturation region operation of
NMOS transistor resistance in pull down path i.e.
resistance of NMOS transistor NM0 can be written as:
Rpull-down=RNM0=1/[µn.Cox.(W/L)NM0(Vdd-Vtn)]
Low to high propagation delay and high to low
propagation delay are given by equation (5) and (6)
respectively,
τplh∞Rpull-up.CL (5)
τphl∞Rpull-down.CL
Where CL is the equivalent parasitic node capacitance
present in output node of each delay cell
So from equation (5) & (6) delay in each stage is
proportional to (τphl+ τplh).
So, oscillation frequency of VCO is given by:
fosc ∞1/N.(τphl+ τplh)
Where N is the number of delay cell stages in Ring
VCO.
Fig..1. Delay cell of VCRO
From above equation it is clear that if control voltage
(Vctrl) increases then PM1 transistor becomes less
conductive i.e. its resistance increases. So overall
resistance in pull up path increases hence output
frequency decreases. So, it is concluded that when
control voltage is zero then transistor PM1 in fully on
and its resistance value is minimum and at that
(2) condition output frequency becomes maximum.
B. Phase Noise In Ring oscillators
A practical oscillator output can be written as:
Vout (t) = A(t).Vout (t)=A(t) .f [ (t)+ ] (8)
where the f function is periodic in 2 and and A(t)
are the model fluctuations in amplitude and phase due
(3) to external and internal noise sources.
The phase noise of the ring oscillator is affected by
many reasons. Phase noise due to White noise occurs
due to tail current noise, another one is phase noise
occurs due to flicker noise which fluctuates at a rate
lower than the oscillation frequency. Flicker noise
(4) depends upon the delay stage in a concerted manner
which accumulates into a large variance in phase.
According to Hajimiri et al. [12] the phase noise of the
ring oscillator is affected due to the white noise current
source. And this source is formed by injecting the
amount of noise during transition period of the oscillator
output signal and due to single sideband phase noise
(6) spectrum which is given by[12].
(9)
where, is the rms value of the impulse sensitivity
function . is the single -side band power spectral
(7)
density of noise current source and is the frequency
offset from the carrier.
III. SUBHARMONIC INJECTION LOCKING
TECHNIQUE
The circuit is oscillated at free-running frequency
without injection of any signal thus, the output signal
frequency is . However, when the signal is
injected as input to the circuit[10] , is shifted and
locked to thus becomes . This
phenomenon is called injection locking, and frequency
locking condition is given by-
(10)
(11)
where is the injection-signal frequency -locking
range of the circuit, N is the subharmonic number. Q is
 1st International Conference On Microelectronics, Circuits and Systems-Micro’2014

the quality factor. is the current injected into the

delay cell and is the tail current of the VCO
oscillation.

According to Lee, et al (2012)," the injection-locking

mode which is to be used in VCOs will be fundamental
or subharmonic locking in which reference signal is
injected i.e. which is equal to or lower than the VCO
output frequency [11] .In general integral
subharmonic locking, the subharmonic ratio
and is given by , where n = 2,3,4...."[11].
Fig. 2.shows the operation of subharmonic injection
locking in a time domain model [10]. As compared to
an ideal VCO the phase error of an free- running VCO
will be increased randomly, owing to thermal and
flicker noise. When injection pulses are given they lock
with the VCO output. The output signal edge [4] is
forced to shift back to right position in every by
the injection pulses, so the phase error no longer Fig. 3. Proposed delay cell
accumulates. The output edge i.e. reset to every ,
and therefore, phase noise can be reduced. Fig .4.shows the four stages of the proposed delay cell .
In this delay cell phase noise is improved by reducing
the total current noise injected during the transition
period [12]. But better phase noise and a wide tuning
range can be obtained by injection locking technique
[11]-[12]. The disadvantage of the delay cell is that due
to the limitation in current swing we are getting a
narrow tuning range. By subharmonic injection locking
technique pulses with narrow width are injected into the
proposed delay cell switching NM2. The reference
pulses amplitude is rail- to- rail.

Fig.2. Using Injection signals phase corrections are made

IV. PROPOSED LOW NOISE RING VCO DESIGN

Fig. 3. shows the topology of the proposed VCO.

An NMOs input pair NM0 and NM1 is used in order to
achieve high operating frequency with low power
dissipation. The cross-coupled PMOS transistors PM3 Fig . 4. Four stages of proposed delay cell
and PM2, the PMOS input transistors PM0 and PM4,
TABLE I
and the PMOS control transistors PM1 and PM5 are DESIGN PARAMETERS OT THE VCRO
adopted to change the oscillation frequency by varying
NM0,NM1 NM2 PM1,PM5 PM3,PM2 PM0,PM4
the control voltage Vcon [12].
W/L 34 1 17 25 42

Generally in the commonly-used ring VCOs delay cells

with a pMOS resistive load, the range of the control
voltage (Vcon) that has a reasonable sensitivity which is
limited to 0 V to the pMOS threshold voltage (Vth). In
order to achieve subharmonic injection locking, nMOS
switch is connected in the proposed delay cell as shown
in Fig.3 at the differential output node.
Fig.5 shows the conventional injection locking
technique. This technique is usually used in designing
wide - tuning- range VCOs. Here multiplied frequency
signal can be achieved as to the reference frequency
when = as high oscillation harmonics lock the
superharmonics of reference signals. From (11) it is
seen that locking range of injection signal is decided by
the reference signals power of Nth superharmonic
which is as follows [9] :
 1st International Conference On Microelectronics, Circuits and Systems-Micro’2014

(12)

where Q represents the quality factor , is the

output frequency , is the Nth harmonic power of
the reference signal and is the output power of
oscillator.

The Nth Fourier spectrum of a pulse is given by

(13)

where D is the duty cycle of pulses , A is the pulse
amplitude. From this equations, short pulses are
generated to achieve wide frequency range.
V. MEASURMENT RESULTS
The proposed ring VCO is implemented in a 90nm
CMOS technology using EDA tool in Cadence Spectre
Fig.7. Phase noise characteristic curve of free running VCO
In the later, 445 MHz injection pulses with a width of
33.6ps were injected using a pulse generator. Locking
range is represented by step width which is shown in (2),
becomes narrower in the oscillation frequency region.
Fig.8 shows that as the control voltage increases the
output frequency decreases. Fig. 9 shows the frequency
spectra of VCO outputs at centre frequency =5.34
GHz.

Fig.5. Pulser with XOR gate

simulator in Virtuoso ADL environment. Fig.7.shows

the oscillation frequency range which is measured from
2.4 GHz to 5.4 GHz over a control voltage from 0.8 to 0
V. The range was measured under a 1.0 V supply
condition.

Fig.8. control voltage VS frequency

Fig.6. Transient analysis of VCRO

Fig.6. shows the initial transient condition of the free

running condition VCO. When a 445 MHz injection
pulse with a width of 33.6 ps was applied, the f - v
characteristics shape becomes stepped with half of the
injection, because of the injection locking mechanism.
Fig.6. shows the performance of phase noise of the free
running VCO at output frequency of = 5.34 GHz and
a value of -103 dBc/Hz was obtained.
Fig .9. output frequency spectrum of VCO at =5.34 GHz
With injection of reference signal of = 445 MHz a
phase noise of -122.3 dBc/Hz was generated at 1-MHz
offset frequency. Fig.10. shows the phase noise curve of
injection locked VCO which is measured using Cadence
PSS analysis.
 1st International Conference On Microelectronics, Circuits and Systems-Micro’2014

Table III shows a comparison and performance

summary with different CMOS ring oscillator. The
phase noise was improved by 20dB compared with the
former. In order to provide better comparison with other
works at different centre frequencies and power
consumption, a Figure-of-Merit (FoM) [13], as defined
here which is as follows:

Where is the phase noise , fo is the oscillation

frequency at the offset frequency of foff and p is the
power consumption of he ring VCO. The proposed
injection locked ring VCO shows a low phase-noise
performance, wide frequency tuning range and with a
smallest power consumption.
The ring oscillator is implemented in 90nm N-well Fig. 10 . Phase noise curve with injection pulse at 1MHz offset
single-poly metal CMOS technology. Fig. 11 shows the frequency
layout of the ring voltage controlled oscillator with
injection pulse. The delay stages of oscillator core are Table III describes about the comparison between
placed close as possible for minimization of parasitic layout and post layout simulations.
Capacitance of interconnection.

TABLE II

PERFORMANCE COMPARISION BETWEEN PROPOSED AND OTHER VCRO

Ref. This work [11] [12] [13] [8]

CMOS(nm) 90 65 65 180 180

VCO ring ring ring ring ring

Power supply (v) 1 1 1 1 1.8

#
FTR (GHz) 2.4-5.4 3.96-7.39 485.7-1011.6 0.479 -4.09 5.16-5.93
(MHz)

(GHz) 5.34 6.34 645 MHz 4.09 5.79

Power(mW) 2.47 12 10 13 80

Offset(MHz) 1 1 1 1 1
Phase noise
(dBc/Hz) -122.3 -113 -110.8 -93.3 -99.5
*
FOM
-193 -178 -157 -154 -156
#
FTR= Frequency Tuning Range, *FOM = Figure of Merit
 1st International Conference On Microelectronics, Circuits and Systems-Micro’2014

In the post layout simulations it is seen that power achieve suitable noise performance for a local oscillator
consumption becomes less as compared to pre layout and wideband transceivers.
but there
is a decrease in the value of phase noise by the value of
-100 dBc/Hz.
REFERENCES
TABLE II
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September 1996.
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33, no. 2, pp. 179–194, February 1998.
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