DIGITAL ELECTRONICS

OUTLINE

 Boolean Algebra
 Karnaugh Map
 Logic Gates
 Numbers system
 Combinational Circuits
 Sequential Circuits
 Timing Fundamental

Self-Study 1- LOGIC EXPRESSION AND NUMBER SYSTEM

 Boolean Algebra
 Theorems (Distribution, Consensus, DE Morgan’s)
HANDS ON
 Simplify SOP expression and implement by using minimum no of
inputs/
 Dual and complement
 Karnaugh Map (K-Map)
 K-Map
 Implicant, Prime Implicant, Essential prime Implicant
 Logic Gates
 Basic gates (NOT, AND, OR)
 Universal gates (NOR, NAND)
 Exclusive OR (EX-OR), Exclusive NOR (EX-NOR)
HANDS ON
 Implement EX-OR and EX-NOR gates with minimum universal gates.
 Implement All Gates using Universal gates.
 Number System
 Conversion (Binary , Decimal, Octal, Hexa-decimal)
 Complements(1’s Complement, 2’s complement)
HANDS ON
 Implement 1’s complement and 2’s complement circuits.
 Code Conversion (BCD to Excess-3, Binary to Grey, Grey to Binary )
HANDS ON
 Implement BCD to Excesss-3 and Binary to Grey Circuit.
 Tutorial-I (Problems based on Boolean algebra, K-Map, number system and
logic gates)

Self-Study 2: COMBINATIONAL CIRCUITS

 Combinational Circuits
  Half adder, Half subtractor
 Full adder, Full subtractor
 FA using HA
 FS using HS
 Adder and Subtractor using Universal Gates
HANDS ON
 Implement Full Adder with the minimum no of Half Adder.
 Implement Full Subtractor with minimum no of Half Subtractor.
 Parallel adder & Subtractor
HANDS On
 Implement 4-bit parallel adder.
 Multiplexer (MUX)/Demultiplexer (DE-MUX)
HANDS ON
 Implement 8:1 mux with minimum no of 2:1 de mux.
 Implement 1:8 mux with minimum no of 1:2 de mux.
 Implement adder and Subtractor using MUX 2:1
 Encoder 8:3 /Decoder 3:8with enable
 Implement 3:8 Decoder using 2:4 decoder and 8: 3 Encoder using 4:2
Encoder
HANDS ON
 Implement Full Adder Using decoder with active high outputs.
 Implement 1’s and 2’s complement circuit.
 COMPARATOR
 Tutorial-II (Problems based on Mux, Demux, Encoder, Decoder, Half
Adder/Subtractor, Full Adder/Subtractor)
 Multiplier CKT

Self-Study 3: SEQUENTIAL CIRCUITS AND HANDS ON

 Sequential Circuits
 Clock (Trigger)
 Latch
 Flip Flops & Excitation Table
HANDS ON
 Implement Flip-Flops ie SR to JK to MS JK-DFF-TFF (Conversion )
 Registers
HANDS ON
 Implement SISO, SIPO , PISO and PIPO register by using D-flip flop.
 Counters (Asynchronous/synchronous/Mod /Even/Odd/Sequence
Detector/Ripple Counter/Johnson Counter/Up & Down )
 Clock div/2 , Div/4 & Div/3 or Div/5 Ckt
 33% AND 50 % Duty cycle counter
 Mod point 5 counter design
HANDS ON
  Implement BCD counter by using D-flip flop.
 Tutorial-II (problems based on register, flip flop and counters)
 FSM – ,Moore and Melay ,Overflow and Non Overflow , Sequence Detector