CO-3

80286
Introduction & Architecture
80286 ARCHITECTURE
80286 Architecture consists of four separate processing units:

1) Address Unit (AU)

2) Bus Unit (BU)

3) Instruction Unit (IU)

4) Execution Unit (EU)

 80286
Register Organization
 80286
Memory Access in GDT & LDT
STRUCTURE OF GLOBAL DESCRIPTOR
LOCAL AND GLOBAL DESCRIPTORS
CALCULATION OF MAXIMUM ACCESSIBLE VIRTUAL MEMORY
• Global Descriptors are 8K and Local Descriptors are 8K in number.

• Total no. of Descriptors = 8K + 8K = 16K

• There can be 16K Segments.

• Since each segment can have a maximum size of 64KB,

MAXIMUM ACCESSIBLE VIRTUAL MEMORY = 16K x 64KB = 1GB

ACCESS RIGHTS BYTE
DATA TYPES SUPPORTED BY 80286
 80386
Introduction & Architecture
Introduction : 80386
-----------------------------------------------------------------------------------------------------------------
• MMU supports paging, virtual memory and 4-level protection.

• Using paging, 80386 organizes the available physical memory into pages
of 4kB each.

• 8 debug registers (DR0-DR7) for hardware debugging and control.

• Has on-chip address translation queue.

• 2 versions: 80386DX & 80386SX (16-bit D’bus, 24-bit A’bus, low power &
low cost).

• 80386DXà132 pin IC in PGA packageà20MHz & 33MHz versions.

 80386
Register Organization
 80386
Operating Modes
80386: Real Address Mode

• 80386 can address 1MB of Physical Memory using A0-A19.

• Paging Unit is disabled in this mode à Real Address = Physical Address.

• Segments in this mode can be read, written or executed à no protection.

• IVT of 80386 is allocated 1kB space from 00000H to 0003FFH.

48
 80386
Memory Access in Virtual Mode
Stores DBA
Structure of 80386 Segment Descriptor
 80486
Introduction