Computer Organization and Architecture

15EM2001
COMPUTER ORGANIZATION AND ARCHITECTURE
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED 1
Introduction to RISC
Since the development of the stored program computer around
1950, there are few innovations in the area of computer organization
and architecture. Some of the major developments are:
• The Family Concept (1964)
• Microprogrammed Control Unit (1951)
• Cache Memory (1968)
• Pipelining
• Multiple Processor
The computer designers intend to reduce this gap (i.e., semantic and
high level programming languages) and include large instruction set,
more addressing mode and various HLL statements implemented in
hardware.
As a result the instruction set becomes complex. Such complex

instruction sets are intended to:
• Ease the task of the compiler writer.
• Improve execution efficiency, because complex sequences of operations
can be implemented in microcode.
• Provide support for even more complex and sophisticated HLLs.
Complex Instruction Set Computer (CISC).
The instruction execution characteristics involves the following

aspects of computation:
• Operation Performed
• Operand Used
• Execution sequencing
Reduced Instruction Set Computer (RISC).
• A large number of general purpose registers, or the use

of compiler technology to optimize register usage.
• A limited and simple instruction set.
• An emphasis on optimizing the instruction pipeline
Characteristics of some CISCs, RISCs and Superscalar
Processors:
6
© 2016 KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED
Comparison of RISC & CISC
Characteristics of Reduced Instruction Set Architecture (RISC)
Certain common characteristics are :
1. One instruction per cycle.

2. Register–to–register operations.
3. Simple addressing modes.
4. Simple instruction formats.
Design Issues of RISC
1. The use of a large register file:
Two basic approaches are possible, one is based on

software and the other on hardware.
• The software approach
• The hardware approach
Design Issues of RISC (Cont’d…..)
2. Register Window:
The use of a large set of registers should decrease the need to
access memory. The design task is to organize the registers in such a
way that this goal is realized.
Thus the variables that are used in a program can be categorized as
follows :
• Global variables
• Local variables
• Passed parameters
• Returned variable
2. Register Window: (Cont’d….)
The register window is divided into three fixed-size areas.

• Parameter registers: hold parameters passed down from the procedure that
called the current procedure and hold results to be passed back up.
• Local registers are used for local variables.
• Temporary registers are used to exchange parameters and results with the
next lower level (procedure called by current procedure)
2. Register Window: (Cont’d….)
Overlapping Register Windows
3. Compiler based Register Optimization:
To optimize the use of registers, the approach taken is as follows:
• Each program quantity that is a candidate for residing in a register is assigned
to a symbolic or virtual register.
• The compiler then maps the unlimited number of symbolic registers into a
fixed number of real registers.
• Symbolic registers whose usage does not overlap can share the same real
register.
• If in a particular portion of the program, there are more quantities to deal

with than real registers, then some of the quantities are assigned to the
memory
© 2016 location.
KL University – The contents of this presentation are an intellectual and copyrighted property of KL University. ALL RIGHTS RESERVED
13
3. Compiler based Register Optimization: (Cont’d….)
The technique most commonly used in RISC compiler is known as
graph colouring.
14
Large Register file versus cache
Parallel processing
• Parallel processing may occur in the instruction stream, in the data
stream, or in both. Flynn's classification divides computers into four
major groups as follows:
1. Single instruction stream, single data stream (SISD)
2. Single instruction stream, multiple data stream (SIMD)
3. Multiple instruction stream, single data stream (MISD)
4. Multiple instruction stream, multiple data stream (MIMD)
Introduction to pipelining
Pipelining is a technique of decomposing a sequential process into sub-
operations, with each sub-process being executed in a special dedicated
segment that operates concurrently with all other segments.
Conventional Sequential Execution
Pipelined Execution
Introduction to pipelining: (Cont’d…..)
Example of pipelining
18
Decomposition of the instruction execution:

• Fetch Instruction (FI)
• Decode Instruction (DI)
• Calculate Operand (CO)
• Fetch Operands(FO)
• Execute Instruction (EI)
• Write Operand(WO)
Timing Diagram for Instruction Pipeline Operation 20

Four Stage Pipeline
F: Fetch, Read the instruction from the memory
D: Decode, decode the instruction and fetch the source operand (S)
O: Operate, perform the operation
W: Write, store the result in the destination location.
Timing diagram for 4- stage instruction pipeline 21

Instruction Execution in a Four Stage Pipeline
Flow-chart
22
Design Issues of Pipeline
The cycle time of an instruction pipeline is the time needed to advance a set of instructions
one stage through the pipeline. The cycle time can be determined as:
Where,
= time delay of the circuitry in the ith stage of the pipeline

= maximum stage delay (delay through stage which experiences the largest delay)
= number of stages in the instruction pipeline
= time delay of a latch, needed to advance signals and data from one stage to the next
Design Issues of Pipeline: (Cont’d….)
• Let Tk,n be the total time required for a pipeline with k stages to
execute n instructions. Then,
• A total of k cycles are required to complete the execution of the first

instruction, and the remaining n-1 instructions require n-1 cycles.
• consider a processor with equivalent functions but no pipeline, and

assume that the instruction cycle time is
Design Issues of Pipeline: (Cont’d….)
The speedup factor for the instruction pipeline compared to execution

without the pipeline is defined as
Pipeline Hazards
• A pipeline hazard occurs when the pipeline, or some portion of the
pipeline, must stall because conditions do not permit continued
execution. Such a pipeline stall is also referred to as a pipeline bubble.
• There are three types of hazards:
1. Resource Hazards or Structural Hazards

2. Data Hazards
3. Control Hazards or Branch Hazards
Resource Hazards
Example of Resource Hazard
Data Hazards
1. Read after write (RAW), or true dependency
2. Write after read (RAW), or anti-dependency
3. Write after write (RAW), or output dependency.
Example of Data Hazard
Control Hazards
Dealing with Branches
1. Multiple streams
2. Pre-fetch branch target
3. Loop buffer
4. Branch prediction
5. Delayed branch
Control Hazards
The Effect of a Conditional Branch on Instruction Pipeline Operation 30

Arithmetic Pipeline
31
Floating point adder
Numerical Example:
Attached Array Processor
An attached array processor is an auxiliary processor attached to a

general-purpose computer. It is intended to improve the performance of
the host computer in specific task.
Attached array processor with host computer

SIMD array processor
An Single Input Multi Data (SIMD) array processor is a computer with
multiple processing units operating in parallel.
SIMD array processor organization

Vector Processing
The following are representative application areas where vector processing is of the utmost
importance.
1. Long-range weather forecasting
2. Petroleum explorations
3. Seismic data analysis
4. Medical diagnosis
5. Aerodynamics and space flight simulations
6. Artificial intelligence and expert systems
7. Mapping the human genome
8. Image processing
Instruction level parallelism
General Superscalar Organization
Fundamental limitations to parallelism
• True data dependency
• Procedural dependency
• Resource conflicts
• Output dependency
• Anti-dependency

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15EM2001

COMPUTER ORGANIZATION AND ARCHITECTURE

As a result the instruction set becomes complex. Such complex

The instruction execution characteristics involves the following

• A large number of general purpose registers, or the use

Certain common characteristics are :

1. One instruction per cycle.

1. The use of a large register file:

Two basic approaches are possible, one is based on

• The hardware approach

2. Register Window: (Cont’d….)

The register window is divided into three fixed-size areas.

2. Register Window: (Cont’d….)

Overlapping Register Windows

• If in a particular portion of the program, there are more quantities to deal

Conventional Sequential Execution

Decomposition of the instruction execution:

Timing Diagram for Instruction Pipeline Operation 20

O: Operate, perform the operation

W: Write, store the result in the destination location.

Timing diagram for 4- stage instruction pipeline 21

= time delay of the circuitry in the ith stage of the pipeline

• A total of k cycles are required to complete the execution of the first

• consider a processor with equivalent functions but no pipeline, and

The speedup factor for the instruction pipeline compared to execution

• There are three types of hazards:

1. Resource Hazards or Structural Hazards

Example of Resource Hazard

1. Read after write (RAW), or true dependency

2. Write after read (RAW), or anti-dependency

3. Write after write (RAW), or output dependency.

Example of Data Hazard

The Effect of a Conditional Branch on Instruction Pipeline Operation 30

An attached array processor is an auxiliary processor attached to a

Attached array processor with host computer

SIMD array processor organization

General Superscalar Organization

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