Microprocessors and Microcontrollers – 11EC311

Architectural Model of 8086

Microprocessor based System

Data Bus
CPU
General-
Serial
Purpose RAM ROM I/O Timer COM
Micro- Port
Port
processor
Address Bus

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Microcontroller based System

CPU RAM ROM

A single chip
Serial
I/O Port COM
Timer
Port

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Microprocessor vs Microcontroller

Microprocessor Microcontroller
CPU is stand-alone, RAM, ROM, CPU, RAM, ROM, I/O and timer
I/O, timer are separate are all on a single chip
Designer can decide on the Fixed amount of on-chip ROM,
amount of ROM, RAM and I/O RAM, I/O ports
ports.
Expensive Cheap
Used in Computers Used by Application Specific
Systems
General-purpose Single-purpose
Example ： Intel’s x86, Motorola’s Example ： Motorola’s 6811,
680x0 Intel’s 8051, Zilog’s Z8

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Features of 8086 Microprocessor

●
16-bit Microprocessor
●
Data Bus – 16-bit
●
Address Bus – 20-bit
●
Supports Memory upto 1MB
●
16 Bit Registers
●
2.5 MIPS(Million of Instructions per second)
●
16 Logical Segments (Max 64KB Each)
●
Maximum and Minimum Modes of Operation

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Memory Segmentation

●
Physical Address – 20 Bit (Wont fit in registers !!!)
●
Base Address / Segment Address – 16 Bit
●
Offset Address / Effective Address – 16 Bit
●
Code Segment
●
Data Segment
●
Extra Segment
●
Stack Segment

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Physical Address Calculation

●
Physical Address = Base Address * 16d + Offset Address

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Non-Overlapped vs Overlapped Segment

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Advantages of Segmentation

●
It allows the memory capacity to be 1MB even though the
actual addresses to be handled by instructions are 16-bits
●
It allows use of separate memory areas for program, data
& stack, thus the protection of these is possible.
●
For large programs , it can use multiple segments for
program code, Data & Stack.
●
Program relocation can be very easily done.

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Register Organization

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Register Organization

●
Special Operation of General Registers
AX – Accumulator
–
– BX – Base Register
– CX – Count Register
– DX – Destination Register
●
Segment Registers hold Base Address of Segments
●
Indexed and Pointer Registers are for Storing Offsets for
particular segments
●
Flag Register Holds Status and Control Flags

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Default Segment and Offset Registers

Segment Segment Offset Memory operation

Register Register
Code Segment CS IP Instruction fetch
Stack Segment SS SP,BP Stack operation

Data Segment DS BX/SI/DI General data access

Data Segment DS SI Source string data

access
Extra Segment ES DI Destination string
data access
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Pipelining Model vs Non Pipelining Model

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8086 Architecture

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Components of Architecture

●
BIU – Bus Interface Unit (Fetch)
–Segment Registers – CS,DS,ES,SS
– Instruction Pointers – IP
– Adder
– 6 Byte Prefetch Queue
●
EU – Execution Unit (Execute)
– ALU
– General, Indexed and Pointer Registers
– Flags

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Flag Register of 8086

6 Status Flags
3 Control Flags

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Status Flags

●
Controlled by ALU after execute operation
●
Carry Flag
– 1 : Carry out of MSB
– 0 : No Carry out of MSB
●
Auxillary Carry Flag
– 1 : Carry out of Nibble
– 0 : No Carry out of Nibble
●
Parity Flag
– 1 : Odd Parity (Odd Number of 1's in lower byte)
– 0 : Even Parity

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Status Flags

●
Zero Flag
– 1 : Result of Arithmetic or Logical Operation = 0
– 0 : Non-Zero Result
●
Sign Flag
– 1 : Result is Negative (MSB =1)
– 0 : Result is Positve
●
Overflow Flag
– 1 : Overflow Condition Occured
– 0 : No Overflow

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Control Flags

●
Can be Controlled by user
●
Trap Flag
– 1 : Single Step Mode for Debugging
– 0 : Normal Mode
●
Direction Flag
– 1 : Address Decrement in String Operations
– 0 : Address Increment in String Operations
●
Interrupt Flag
– 1 : Interrupts Enabled
– 0 : Interrupts Disabled

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References

●
https://www.sites.google.com/site/sripathroykoganti/my-forms
●
D.V.Hall “Microprocessor and Interfacing”, 2nd Edition Tata McGraw
Hill Publishing Company,2006.
●
A.K. Ray & K. M Bhurchandi, “Advanced Microprocessors &
peripherals”, Tata Mc Graw Hill Publishing Company 2002.
●
Rajkamal, “Microcontrollers - Architecture, Programming, Interfacing
& System Design”, 2 nd edition, Pearson Education.

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 Thank You

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