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Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LCCC (20) 8.89 mm × 8.89 mm
UC1846
CDIP (16) 6.92 mm × 19.56 mm
PLCC (20) 8.96 mm × 8.96 mm
UC2846, UC3846 SOIC (16) 7.5 mm × 10.3 mm
PDIP (16) 6.35 mm × 19.3 mm
SOIC (16) 7.5 mm × 10.3 mm
UC2847, UC3847
PDIP (16) 6.35 mm × 19.3 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Block Diagram
VIN
15 180Ÿ
.1µF VIN 2W
2 13
VREF VC
.05µF
.5k 1N4245
9 11
RT AOUT 2N4150
68Ÿ UES1402 200µH
.005µF VO
8 1k
CT 4
C/S+
UCX846
3.2k
5 68Ÿ 1k
+E/A BOUT 14 300µF
100µF 2N4150 1N4245
UES1402
3.2k 6
-E/A 3 .5Q
C/S- .05µF
7 COMP 1
CS/SS VREF
68k 1.5k
.0015 SH-DN GND
16 12
1k
3.6k
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 1 8 Application and Implementation ........................ 11
3 Description ............................................................. 1 8.1 Application Information............................................ 11
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 11
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 15
6 Specifications......................................................... 4 10 Layout................................................................... 16
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 16
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 16
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 17
6.4 Thermal Information .................................................. 4 11.1 Related Links ........................................................ 17
6.5 Electrical Characteristics........................................... 5 11.2 Community Resources.......................................... 17
6.6 Typical Characteristics .............................................. 7 11.3 Trademarks ........................................................... 17
7 Detailed Description .............................................. 8 11.4 Electrostatic Discharge Caution ............................ 17
7.1 Overview ................................................................... 8 11.5 Glossary ................................................................ 17
7.2 Functional Block Diagram ......................................... 8 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................... 8 Information ........................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Removed soldering temperature ........................................................................................................................................... 4
J or N, DW Packages
16-Pin CDIP or PDIP, SOIC
Top View
FN or FK Packages
20-Pin PLCC or LCCC
Top View
Pin Functions
PIN
PLCC, LCC I/O DESCRIPTION
DIL, SOIC NO. NAME
NO.
1 2 C/S SS I Current limit/soft-start programming
2 3 VREF O 5.1-V reference voltage output
3 4 C/S – I Current sense comparator inverting input
4 5 C/S + I Current sense comparator non-inverting input
5 7 E/A + I Error amplifier inverting input
6 8 E/A – I Error amplifier inverting input
7 9 COMP I/O Error amplifier output and input to the PWM comparator
8 10 CT I Oscillator frequency programming capacitor pin
9 12 CR I Oscillator frequency programming resistor pin
10 13 Sync I/O Synchronization out from master controller or input of slave controller
11 14 A Out O PWM drive signal output A, Pin11 and P14 are complementary
12 15 GND G All signals are referenced to this node
13 17 VC I Bias supply input for output stage
14 18 B Out O PWM drive signal output B, Pin11 and P14 are complementary
15 19 VIN I Bias supply input
16 20 Shutdown I External shutdown signal input
— 1, 6, 11, 16 N/C
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply Voltage (Pin 15) 40 V
Collector Supply Voltage (Pin 13) 40 V
Output Current, Source or Sink (Pins 11, 14) 500 mA
Analog Inputs (Pins 3, 4, 5, 6, 16) –0.3 +VIN V
Reference Output Current (Pin 2) –30 mA
Sync Output Current (Pin 10) –5 mA
Error Amplifier Output Current (Pin 7) –5 mA
Soft Start Sink Current (Pin 1) 50 mA
Oscillator Charging Current (Pin 9) 5 mA
Power Dissipation at TA = 25°C 1000 mW
Power Dissipation at TC = 25°C 2000 mW
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
(2) Parameter measured at trip point of latch with VPIN 5 = VREF, VPIN 6 = 0 V.
(3) Amplifier gain defined as: G = ΔVPIN7 / ΔVPIN4; VPIN4 = 0 to 1.0 V
Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: UC1846 UC1847 UC2846 UC2847 UC3846 UC3847
UC1846, UC1847, UC2846
UC2847, UC3846, UC3847
SLUS352C – JANUARY 1997 – REVISED DECEMBER 2015 www.ti.com
CL = 1 nF, TJ = 25°C
Fall Time (1) 50 300 50 300 ns
UNDERVOLTAGE LOCKOUT
Start-Up Threshold 7.7 8.0 7.7 8.0 V
Threshold Hysteresis 0.75 0.75 V
TOTAL STANDBY CURRENT
Supply Current 17 21 17 21 mA
Figure 1. Error Amplifier Gain and Phase vs Frequency Figure 2. Error amplifier Open-Logic DC Gain vs Load
Resistance
7 Detailed Description
7.1 Overview
The UCx846/7 family of control devices provides the necessary features to implement off-line or DC-to-DC fixed-
frequency, current-mode control schemes with a minimal external parts count. Internally implemented circuits
include under-voltage lockout featuring start-up current less than 1 mA, a precision reference trimmed for
accuracy at the error amplifier input, logic to insure latched operation, a PWM comparator which also provides
current limit control, and a totem pole output stage designed to source or sink high-peak current. The output
stage, suitable for driving either N-Channel MOSFETs or bipolar transistor switches, is low in the off state.
5.1-V
VIN 15 REFERENCE 2 VREF
REGULATOR
13 VC
SYNC 10 UVLO
LOCKOUT F/F
Q 11 A OUT
RT 9
T
OSC Q UC1846
CT 8 Output Stage
C/S- 3 COMP
X3 +
+ S R UC1847
C/S+ 4 Q Output Inverted
S
0.5 V 14 B OUT
+
0.5 mA
NI 5 12 GND
+
E/A
INV 6 CURRENT LIMIT
1
ADJUST
+ 16 SHUTDOWN
COMP 7 350 mV 6 k:
7.3.2 Oscillator
By implementing the oscillator using all NPN transistors, the UCx846/7 achieves excellent temperature stability
and waveform clarity at frequencies in excess of 1 MHz.
Referring to Figure 4, an external resistor RT is used to generate a constant current into a capacitor CT to
produce a linear sawtooth waveform. Oscillator frequency may be approximated by selecting RT and CT such
that:
2.2
fOSC
R T CT (1)
7.4.2 Shutdown
The shutdown circuit was designed to provide a fast acting general purpose shutdown port for use in
implementing both protection circuitry and remote shutdown functions. The circuit may be divided into an input
section consisting of a comparator with a 350-mV temperature compensated offset, and an output section
consisting of a three transistor latch. Shutdown is accomplished by applying a signal greater than 350 mV to pin
16, causing the output latch to fire, and setting the PWM latch to provide an immediate signal to the outputs.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
15 180Ÿ
.1µF VIN 2W
2 13
VREF VC
.05µF
.5k 1N4245
9 11
RT AOUT 2N4150
68Ÿ UES1402 200µH
.005µF VO
8 1k
CT 4
C/S+
UCX846
3.2k
5 68Ÿ 1k
+E/A BOUT 14 300µF
100µF 2N4150 1N4245
UES1402
3.2k 6
-E/A 3 .5Q
C/S- .05µF
7 COMP 1
CS/SS VREF
68k 1.5k
.0015 SH-DN GND
16 12
1k
3.6k
where
• ID = Oscillator discharge current at 25°C; typically is 7.5. (2)
For large values of RT: τd (μs ) ≈145CT (μF).
Oscillator frequency is approximated by the formula:
2.2
fT (kHz) |
R T (k:) u CT (PF) (3)
R 2 VREF
− 0.5
R1 + R 2
Peak Current (IS) is determined by the formula: IS =
3RS
Figure 8. Pulse by Pulse Current Limiting
Figure 10. Responsive to a Step Load Change of 1 A Figure 11. Switch Current Showing Flux Balance in
UCX846/7
10 Layout
Vin
1 C/S SS SHUTDOWN 16
2 VREF VIN 15
3 C/S- BOUT 14
4 C/S+ VC 13
5 E/A+ GND 12
6 E/A- AOUT 11
7 COMP SYNC 10
8 CT RT 9
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
5962-86806012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
86806012A
UC1846L/
883B
5962-8680601EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8680601EA
UC1846J/883B
UC1846J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 UC1846J
UC1846J883B ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8680601EA
UC1846J/883B
UC1846L883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962-
86806012A
UC1846L/
883B
UC2846DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2846DW
& no Sb/Br)
UC2846DWG4 ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2846DW
& no Sb/Br)
UC2846DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UC2846DW
& no Sb/Br)
UC2846J ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -40 to 85 UC2846J
UC2846N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2846N
& no Sb/Br)
UC2846NG4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 UC2846N
& no Sb/Br)
UC3846DW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3846DW
& no Sb/Br)
UC3846DWTR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3846DW
& no Sb/Br)
UC3846DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR 0 to 70 UC3846DW
& no Sb/Br)
UC3846N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3846N
& no Sb/Br)
UC3846NG4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UC3846N
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 6-May-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-May-2015
Pack Materials-Page 2
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