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ABSTRACT
Input
Software defined radio (SDR) is an exciting merger of digital RF/IF Digitizing DSP Base Band
Front End ADC & DAC Front End Processing
signal processing and wideband radio hardware. The term Antenna
Output
SDR came into more common usage in 1992 by Dr. Joe Feedline
Analog filters Hardware Firmware with Hardware & Software
Mitola, but actually had its beginnings back in 1984 at E- & amplifiers Software Hooks Components
1. INTRODUCTION
we capture 5 to 10 seconds of I/Q signal samples at 2.4 Msps, 1002 MHz. Information found on the Internet confirms that
and then work with those samples after the capture is com- the tested range is somewhere between the two extremes. A
plete. Although the processing is not done in strict real-time, frequency synthesizer inside the R820T generates a local os-
we can listen to the results by playing signals back via the PC cillator (LO) signal which is responsible for down converting
sound system (audio control in an IPython notebook [2]). For the received RF to an intermediate frequency (IF). The tuning
the case of digital modulation, we perform error checking on resolution is 1 Hz, or so it seems from the information avail-
the recovered bits using the fact that the transmitted bits are able on the Internet. Gain control is also provided, both at the
known in advance. An m-sequence generator running on an LNA and at the output via a variable gain amplifier (VGA).
ARM Cortex-M3 device serves as the data source. The first Information on the Realtek chip is not available, unless
exposure to the hardware is a test drive the RTL-SDR dongle you have an nondisclosure agreement (NDA) in place from
using the software app SDR# [3]. Realtek. This leaves the rest of the SDR open to speculation.
In what follows, we first introduce some of the details of It is the RTL2832U where the digital signal processing (DSP)
the RTL-SDR and develop a behavioral level model that ex- takes place, which includes additional filtering and down sam-
plains in a mathematical sense, the inner workings of the de- pling of the IF signal delivered by the R820T. The ADC pro-
vice. The next step is exploring SDR# to get a high level feel duces 8-bit real/inphase (I) and imaginary/quadrature (Q) in-
for SDR. Then it is on to algorithm development using either terleaved sample values, in an unsigned format. When you get
MATLAB or Python code. Several case studies are provided your hands on the samples they are finally converted to signed
that include demodulation of FM and FM-stereo (multiplexed 8-bit values and then to parallel I and Q streams. We describe
FM), and finally demodulating frequency shift keying (FSK). this further when the behavioral level model of the RTL-SDR
The FSK demodulator will include a bit synchronizer so to is presented. Finally the RTL2832U contains a USB interface
account for the fact that the transmit and receiver clocks are that sends samples to the PC.
asynchronous. Concluding remarks, including assessment de- To better understand the functionality of the RTL-SDR we
tails are provided in the final sections. consider the behavioral level model shown in Fig. 4. A model
of this type allows us to focus on the signal processing details
2. OVERVIEW OF THE RTL-SDR USB DONGLE of greatest interest. In this case we are concerned with the
mathematical representation of the signal flow from the input
The RTL-SDR dongle contains two primary chips: (1) the to the output. The model shown is linear if you ignore the
Raphael Micro R820T radio tuner and the Realtek RTL2832U 8-bit ADC, which is denoted by the quantizer function Q[ ].
which contains an 8-bit ADC and USB data pump. The orig-
inal intent of this design was for use as a digital video broad- r [ n ] = r I [ n ] + jr Q [ n ]
RTL-SDR USB Dongle
casting (DVB) receiver. If you look on Amazon you will find 8-Bit
r(t) = s(t) LPF ADC
that most variations of the RTL-SDR are sold with a TV re- + n(t) B ≈ 0.8f s
LNA VGA Q[ ]
Osmocom Drivers
mote and some DVB software. 2 2 2 2
From To
–fs ⁄ 2 0 fs ⁄ 2
Ant. f PC
The basic chip configuration is depicted in the block dia- Gain Control s
– j2πf c t
(maybe automatic
gram of Fig. 3. The tuner chip serves as the radio frequency e or AGC) G
ctrl
(RF) front-end for the SDR. Following a miniature coax con-
nector for the antenna is a low noise amplifier (LNA) provid- 2
= complex signal path
ing a noise figure (NF) of about 3.5 dB. The advertised tuning
range of the R820T is 24 MHz to 1850 MHz. Not shown Fig. 4. A behavioral level model of the RTL-SDR.
in Fig. 3 are the inputs to set the sampling rate fs and the
tuner RF gain. These two SDR attributes will be discussed
more later. A simplified view of the R820T tuner internals A simple model for the input signal, r(t), is that it con-
sists of the desired radio signal s(t) plus background noise
RTL2832U USB n(t), due to the receiver front-end in combination with the
From Interface
Ant. USB to PC antenna. For details on receiver noise modeling see [5]. In
R820T
Tuner ADC Data reality, since the receiver has a very wide bandwidth, there
Noise Pump Interleaved
Figure 24 MHz – 1850 MHz Obtaining Data Sheet 8-bit I&Q
are multiple signals present at the front end. This in fact is
~3.5 dB (advertised range) Requires NDA samples one the big challenges of any SDR, in general. From a mod-
eling standpoint, however, we initially assume just one signal
Fig. 3. The RTL-SDR high level block diagram. is present.
http://rtlsdr.org/ You can apply superposition to study the impact of mul-
tiple signals, as long as any one signal does not overload the
is available on the Internet [4]. We learn from the data sheet
http://www.realtek.com.tw/products/productsView.aspx? radio front end. The gain control on the front end serves to
Langid=1&PNid=22&PFid=35&Level=4&Conn=3&ProdID=257
that the actual RF tuning range is listed as being only 42 to keep the signal processing linear, at the expense of dynamic
http://www.realtek.com.tw/products/productsView.aspx?Langid=1&PNid=22&PFid=35&Level=4&Conn=3&ProdID=257
66
2015 IEEE Signal Processing and Signal Processing Education Workshop (SP/SPE)
e−j2πfc t . This is a behavioral representation of negative where LP represents the LPF filter action. In the frequency
frequency translation by fc Hz. Recall the Fourier transform domain
theorem
R ej2πf /fs ' G · fs · R(f + fc ) · HLP (f ),
F (4)
x(t)ej2πf0 t ⇐⇒ X(f − f0 ) (1)
and consider the spectrum sketches of Fig. 5. By choosing where fs /2 ≤ f ≤ fs /2. We have further assumed that
f0 = −fc , the frequency translation theorem shifts the input HLP (f ) = 0 for |f | > fs /2.
spectrum to the left by fc Hz. A signal of interest centered The final stage is the quantizer. Knowing that only 8-bits
at fc will now be located at 0 Hz following multiplication by are available to represents the real and imaginary parts, means
e−j2πfc t . From a behavioral level standpoint we assume that that significant quantization noise is generated. Using con-
cepts found in [6], we can approximate the quantization noise
Signal of interest spectrum
impact on the noise free r[n] as an additive noise process. The
S ( f ) = FT { s ( t ) } S( f) signal out of the quantizer is the sum signal
shift left shift left
Bs
f r[n] + e[n] = rI [n] + jrQ [n] + eI [n] + jeQ [n] , (5)
–fc 0 fc
– j2πf c t
Filtering Frequency translate to ~0 Hz using s ( t )e = a complex signal where the signals eI [n] and eQ [n] are noise signals approxi-
removes
this Effective RTL-SDR mately uniformly distributed over one quantization interval of
Lowpass Filtering Usable bandwidth ~80% of fs
Q[ ]. The signal-to-quantization ratio of the r[n] signal is [6]
f
–fc fs 0 fs
--- fc
– ---
2 2 Rmax
SNRq = 6.02 · B + 10.8 − 20 log10
67
2015 IEEE Signal Processing and Signal Processing Education Workshop (SP/SPE)
88.7 MHz (KCME in Colorado Springs) To demodulate FM, the complex baseband discriminator has
Standard FM broadcasting
Spectrum plot
2.4 f c Gain Wideband and Narrow
Upper and lower sidebands Msps Band FM Demodulator
from an HD radio source also
broadcast over the same carrier y B1 [ n ] y N1 [ n ]
r(t) LPF
RTL-SDR N1
B1
x I [ n ] + jx Q [ n ] Try N1 = 10
z dis [ n ] z B2 [ n ] z N2 [ n ]
Mono FM
LPF 75μs
Discriminator N2 Deemp z out [ n ]
B2 Filter f s2 = 48ksps
= supplied components Try N2 = 5 for easy audio
playback
Waterfall plot
68
2015 IEEE Signal Processing and Signal Processing Education Workshop (SP/SPE)
20
Power Spectrum in dB
20
19 kHz pilot
4.2. FM Stereo Receiver
L+R
15
at
base-
Here the receiver is more complex as all three components
10
band 38 kHz subcarrier containing described in the previous section must be dealt with. Here
5 the L - R channel information
Power Spectrum in dB
−15
Other subcarriers block, but the student needs to configure it and then test it.
The recovered audio, shown in Fig.11 sounds like stereo.
−20
−25 FM stereo
component signals 4.3. FSK Receiver with Bit Synchronization
−30
0 20 40 60 80 100 120
Frequency (kHz) As a final algorithm design example we implement a fre-
quency shift keyed (FSK) receiver. The FSK transmission
Fig. 9. Spectrum of FM demodulated RTL-SDR capture, originates from a Cortex-M3 microcontroller PN data source
ydis [n] at 92.9 MHz. driving a 70 MHz signal generator. Of special consideration
is the need for a bit synchronizer to properly re-sample the
incoming data bearing waveform [9]. The simple fact is the
baseband audio, 19 kHz pilot, and the double sideband 38 transmit and receive clocks cannot be made synchronous to
kHz subcarrier containing L-R audio. We also see a radio data the point where the clock phase does not cause bit errors. The
system (RDS) signal at 57 kHz, which is digital modulation new portions of the receiver block diagram begin at the output
at 1.1875 kbps. This is used for station information. of the second decimator as shown in Fig.12.
69
2015 IEEE Signal Processing and Signal Processing Education Workshop (SP/SPE)
75μs
z N2M [ n ] zD [ n ]
LPF z B2 [ n ] L
z dis [ n ] + 5 Deemp zL [ n ] Clock
B2 Remove +1 SCCS
L+R + Filter z N2 [ n ] mean Tracking
Output -1 Bit Synch
z B3B4 [ n ] from Data bits
BPF LPF –
R 75μs sign( )
5 Deemp zR [ n ] second
[ B 3, B 4 ] B 2 L-R + Filter decimator Approximate Ns
samples per bit
PLL (type 2) θ[n] m-Seq
B n = 10 Hz
z bits [ n ] Bit Error Bit Error
cos ( ) Coherent 38 kHz Report
ζ = 0.707 for subcarrier demod Must match source Detection
2
= supplied components SR Length, m = 5
Note: θ[n] is the tracked phase
f q = 19 kHz of the 19 kHz pilot signal.
= supplied components
Fig. 12. Final stages of the FSK demodulator with bit synch.
Fig. 10. Enhancing the FM demodulator with stereo demulti-
plexing.
z N2M [ n ]
0
1
496 0 50 100 150 200 250 300 350 400 450
Samples (8 per symbol)
0.5
Left
0
Fig. 13. Recovered 10 kbps FSK.
−0.5
−1
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Clearly different! Time (s) terference from one another was something to consider. In the
1 close proximity of the lab, they could see all transmitting sig-
nals and experimented by jamming each other. They moved
0
on to develop algorithms to demodulate captured signals. The
Right
6. REFERENCES
The testing requirement is to error detect both 1 and 10
[1] http://rtlsdr.org/.
kbps FSK. At 10 kbps the peak deviation is 50 kHz, thus
a very wideband signal. The short segment of the recov- [2] http://ipython.org.
ered data bits, prior to the hard decision device (zN 2M [n]),
[3] http//sdrsharp.com.
is shown in Fig.13. The short 5-bit PN code is evident. The
tracking waveform, not shown here, does its job of keeping [4] http://superkuh.com/rtlsdr.html
the data clock synchronous.
[5] Rodger E. Ziemer and William H. Tranter, Principles of
Communications, 7th ed., John Wiley, New York, 2015.
5. CONCLUDING REMARKS
[6] Alan V. Oppenheim and Ronald W. Schafer, Discrete-
The RTL-SDR dongle opens up a lot of possibilities for ex- Time Signal Processing (3rd Edition), Prentice Hall, New
ploring communications receiver algorithms and DSP imple- Jersey, 2010.
mentation issues. Students participating in the lab experi- [7] http://sdr.osmocom.org/trac/wiki/rtl-sdr
ments were engaged and eager to explore the capabilities of
the device and the SDR# software. As an introduction they [8] Mark Wickert, Signals and Systems for Dummies, Wiley,
listened to NOAA’s weather station, experimented with filter New York, 2013.
bandwidths, and tried to improve reception. Before writing [9] K. Chen and J. Lee, “A Family of Pure Digital Signal Pro-
code to implement a demodulator, they used a function gen- cessing Bit Synchronizers,” IEEE Trans. on Commun.,
erator with internal modulation to create a custom transmitter. Vol. 45, No. 3, March 1997, pp. 289–292.
As the different teams worked, they quickly realized that in-
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