My primary responsibility is to verify the low power intent in the SOC designs.

The device which I am

verifying is the mpu from AMD which performs lower operations as well as high performance.

The Low power verification for this device included to check all the device modes and power
domains are targeted for being turned ON and Off and the system is able to work in all low power
modes. Also we need to check that there are no illegal modes in any kind of device configuration.

We were able to find different type of design defects like missing wrong type of isolation, issues
related to low power protocol of many different IPs including power control logic, flash, sram, core
also issues in macro model designs and integration where the always ON pin of the macro model
was connected to the switchable supply causing the analog model to behave in the incorrect
manner. If this was not found in the early stage then it would have resulted in the catastrophic
issues.

ASIC IP/SoC/Low_Power Verification Engineer

Good working knowledge in Low Power Verification using UPF.

Expertise in RTL Design using Verilog-HDL, Functional Verification. - Worked on Low power
intentdesign (CPF/UPF) - Good experience in RC Synthesis, conformal LEC ,STA, and tools like
Encounter

Good experience in PERL, GLS-Gate level simulation , zero delay simulation.

- Good Knowledge on the complete ASIC design flow.
- Good knowledge in Digital Design and VLSI concepts

Project Title: Automation of Power Intent (PI) and United Power Format (UPF) Generation Flow.
- Capturing Tegra's CPU Power Architecture in Excel Format. Such workbook encapsulates system
level PI. This involved brief understanding of its physical layout, power domains, it's dependency
on each other and major units involved.
- Comparison of clamp values post-flow migration and report them into matched, unmatched or
missing.
- Optimizing clamp flow insertion. Removed redundancy in the intermediate local database in the
flow by slightly altering clamp flow insertion and introducing new local database. The
compression observed ranges up to 50%.
- Analyze VC LP Violations and generate summary reports along with an excel sheet to provide
an overview of the same data in an abstracted colour-coded manner to simplify reviewing of
violations.
- Adding 3rd Party UPF Support in UPF Generation Flow along with error-checking functionality.