For low-power verification, the focus is on ensuring that the design is electrically correct

from a low-power perspective. The flow will verify that the retention and isolation are
complete and correct as specified by the power intent.
Checks at this stage include tests for missing isolation or level shifter cells, checks that state
retention and isolation control signals are driven correctly by domains that remain powered
up, and tests for power control functionality. In later stages of the flow (post placement),
these checks also ensure that gate power pins are hooked to the appropriate power rails,
that the always-on cells are appropriately powered, and that there are no “sneak” paths from
power-down domains back to logic.

Special cells required for Multi-Voltage Design

As discussed in the previous session,  Special cells are required for
implementing a Multi-Voltage design. Today lets discuss about these cells
in brief.

(1) Level Shifter

(2) Isolation Cell
(3) Enable Level Shifter
(4) Retention Flops
(5) AON cells
(6) Power Gating Switches/MTCMOS switch

(1) Level Shifter: Purpose of this cell is to shift the voltage from low to high
as well as high to low. Generally buffer type and Latch type level shifters
are available. In general H2L LS’s are very simple, L2H LS’s are little
complex and are in general larger in size(double height) and have 2 power
pins. There are some placement restrictions for L2H level shifter to handle
noise levels in the design. Level shifters are typically used to convert signal
levels and protect against sneak leakage paths. With great care, level
shifters can be avoided in some cases, but this will become less practicable
on a wider scale.

(2) Isolation Cell: These are special cells required at the interface between
blocks which are shut-down and always on. They clamp the output node to
a known voltage. These cells needs to be placed in an ‘always on’ region
only and the enable signal of the isolation cell needs to be ‘always_on’. In a
nut-shell, an  isolation cell is necessary to isolate floating inputs.

There are 2 types of isolation cells (a) Retain “0” (b) Retain “1”

(3) Enable Level Shifter: This cell is a combination of a Level Shifter and

a Isolation cell.

(4) Retention Flops: These cells are special flops with multiple power
supply. They are typically used as a shadow register to retain its value
even if the block in which its residing is shut-down. All the paths leading to
this register need to be ‘always_on’ and hence special care must be taken
to synthesize/place/route them. In a nut-shell, “When design blocks are
switched off for sleep mode, data in all flip-flops contained within the block
will be lost. If the designer desires to retain state, retention flip-flops must
be used”.

The retention flop has the same structure as a standard master-slave flop.
However, the retention flop has a balloon latch that is connected to true-
Vdd. With the proper series of control signals before sleep, the data in the
flop can be written into the balloon latch. Similarly, when the block comes
out of sleep, the data can be written back into the flip-flop.

(5) AON cells: Generally these are buffers, that remain always powered

irrespective of where they are placed. They can be either special cells or
regular buffers. If special cells are used, they have thier own secondary
power supply and hence can be placed any where in the design. Using
regular buffers as AON cells restricts the placement of these cells in a
specific region.
                                    

Picture above gives an idea about how/why/when they are required. In a

nut-shell, “If data needs to be routed through or from sleep blocks to active
blocks and If the routing distance is excessively long or the driving load is
excessively large, then buffers might be needed to drive the nets. In these
cases, the always-on buffers can be used.”

                                         

(6) Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-

threshold CMOS, where low-Vt gates are used for speed, and high-Vt
gates are used for low leakage. By using high-Vt transistors as header
switches, blocks of cells can be switched off to sleep-mode, such that
leakage power is greatly reduced. MTCMOS switches can be implemented
in various different ways. First, they can be implemented as PMOS
(header) or NMOS (footer) switches. Secondly, their granularity can be
implemented on a cell-level (fine-grain) or on a block-level (coarse-grain).
That is, the switches can be either built into every standard cell, or they can
be used to switch off a large design block of standard cells.

 Depending on the design characteristics, if these cells are readily

available, we can start looking at how to use these cells in successfully
implementing a Multi-Voltage Design.
This post is filed under low power general.