ELE 4550 ASIC Technologies Week 11 Tutorial

FPGA Programming Technology

Static RAM:
This Xilinx SRAM configuration cell is constructed from two cross-coupled inverters and uses a standard CMOS process. The configuration cell drives the gates of other transistors on the chipeither turning pass transistors or transmission gates on to make a connection or off to break a connection. Advantage: Designers can reuse chips. Easy to upgrades. Disadvantage: Need to keep power supplied. Alternatively you can load the configuration data from a permanently programmed memory (typically a flash or PROM ) every time you turn the system on. Larger in size.

Anti-fuse:
An antifuse is the opposite of a regular fusean antifuse is normally an open circuit until you force a programming current through it (about 5 mA). In a polydiffusion antifuse the high current density causes a large power dissipation in a small area, which melts a thin insulating dielectric between polysilicon and diffusion electrodes and forms a thin (about 20 nm in diameter), permanent, and resistive silicon.

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ELE 4550 ASIC Technologies Week 11 Tutorial

PROM: The EPROM cell is almost as small as an antifuse. An EPROM transistor looks like a normal MOS transistor except it has a second, floating, gate. Applying a programming voltage V PP (usually greater than 12 V) to the drain of the n- channel EPROM transistor programs the EPROM cell. A high electric field causes electrons flowing toward the drain to move so fast they jump across the insulating gate oxide where they are trapped on the bottom, floating gate.

Electrons trapped on the floating gate raise the threshold voltage of the n- channel EPROM transistor. Once programmed, an n- channel EPROM device remains off even with VDD applied to the top gate. An unprogrammed n- channel device will turn on as normal with a top-gate voltage of VDD. Exposure to an ultraviolet (UV) lamp will erase the EPROM cell. An absorbed light quantum gives an electron enough energy to jump from the floating gate. To erase a part we place it under a UV lamp (Xilinx specifies one hour within 1 inch of a 12,000 m Wcm 2 source for its EPLDs). Programming an EEPROM transistor is similar to programming an UV-erasable EPROM transistor, but the erase mechanism is different.

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ELE 4550 ASIC Technologies Week 11 Tutorial

FPGA Architecture

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ELE 4550 ASIC Technologies Week 11 Tutorial ASIC Design Guideline:

I/O considerations - pins are valuable resources 1. driving capability of I/O cells in ASIC is limited, typically 4mA 2. provide adequate number of power and ground pins. One rule of thumb is to allow one pair of power and ground pins for every eight outputs that might drive or change states simultaneously 3. power and ground pins should be decoupled from the PCB via capacitors to provide some insulation from supply spikes.

4. 5.

pin assignment must be formulated early in the design process multiplexing is not encouraged

Simulation considerations 1. simulation should be performed at every level of the design hierarchy (such as pre-layout or post-layout) 2. simulation should run without any errors or warnings. Every simulator error and unknown signal state should be tracked, understood and fixed 3. simulation should include off-chip loading

4. 5. 6.

simulation should always start with an initialization routine each set of simulation or test vector should be self-contained be aware of maximum in test vector file specified by ASIC vendor. 4K is typical

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ELE 4550 ASIC Technologies Week 11 Tutorial

Design considerations 1. it is best to use synchronous technique 2. extra flip-flop may be used to break up long delay path (pipeline) 3. avoid excessive fan-out. Large load should be driven by a tree of buffers.

4. 5.

avoid excessive loading to minimize load-dependent delay do not rely on gates as delay element (use buffer)

6. 7. 8.

do not overdrive any one wire with multiple buffers avoid gating together clock and data or control signals(use global clock) do not leave tri-state buses floating when not in use

9. 10. 11. 12. 13.

provide a means of reseting or initializing all nodes to a known states RAM signals should be accessible from the I/O so that standard RAM tests can be performed feedback loop should be latched break designs into hierarchy do not push technology to its limit

Design Reliability 1. minimize manufacturing defects (increase tolerance) 2. provide adequate supply pads and lines 3. minimize high current density 4. provide adequate current drive 5. avoid using a single large buffer (cascade buffer)

Reference: [1] http://www.edacafe.com/books/ASIC/Book/CH04/CH04.1.php#pgfId=1061

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