EXCEL ENGINEERING COLLEGE

(Autonomous)
ELECTRONICS AND COMMUNICATION ENGINEERING
Fifth Semester
20PE021 ASIC Design
Regulations 2020
Question Bank
UNIT – II (Programmable ASICs, Logic Cells and I/O Cells)
Anti fuse - static RAM - EPROM and EEPROM technology - Actel ACT - Xilinx LCA – Altera FLEX - Altera MAX - DC & AC
outputs - DC & AC inputs - Clock input - Power input - Xilinx I/O blocks.
PART- A
Q.No Questions
Define Antifuse.
1  An Antifuse is an opposite of a regular fuse. Antifuse is normally an open circuit until you force a programming
current about 5 mA through it.
Sketch the cross section of Actel antifuse.

List the two advantages of metal–metal antifuse over poly–diffusion antifuse.

 Connections to a metal–metal antifuse are direct to metal and the wiring layers. Connections from a poly–
3 diffusion antifuse to the wiring layers require extra space and create additional parasitic capacitance.
 Direct connection to the low-resistance metal layers makes it easier to use larger programming currents to
reduce the antifuse resistance.
Infer about hot-electron injection or avalanche injection.
 A high electric field causes electrons flowing toward the drain to move so fast they jump across the insulating
4
gate oxide where they are trapped on the bottom of floating gate in EPROM transistor.
 These energetic electrons are hot and the effect is known as hot-electron injection or avalanche injection.
Define derating factors.
5  Convert nominal or typical timing figures to the worst case or best case, we use measured or empirically
derived constants called derating factors.
Label any four features of XC3000 CLB.
 A 32-bit look-up table
6  CLB propagation delay is fixed and independent of the logic function
 7 inputs to the XC3000 CLB: 5 inputs CLB inputs and 2 inputs flip-flop outputs
 2 outputs from the LUT
Classify the three types of programming in PALs.
 Fusible links
7
 UV –Erasable EPROM
 EEPROM (E2PROM)–Electrically Erasable Programmable ROM.
8 List the two advantages and one disadvantage of static RAM.
Advantages
 Designers can reuse chips during prototyping and a system can be manufactured using ISP.
 Customer can be sent a new configuration file to reprogram a chip not a new chip.
 Disadvantage
 Volatile – needs power all the time / use PROM to download configuration data.
Name the four types of logic cells.
 Actel ACT
9  Xilinx LCA
 Altera FLEX
 Altera MAX
State Noise Margin.
 The allowable noise voltage on the input of a gate so that the output will not be affected.
10
 The specification most commonly used to specify noise margin is in terms of two parameters-
LOW noise margin, NML, and HIGH noised margin, NMH.
Justify why Actel architecture is called as a non deterministic architecture?
 We cannot predict the exact delays on an Actel chip until we have performed the place and route step.
11
 By using that only we know how much delay is contributed by the interconnect, since we cannot determine the
exact delay before physical layout is complete, so that Actel Architecture is non deterministic.
Mention about speed grading.
12
 FGPA vendors sort chips according to their speed. The sorting is known as speed grading or speed binning.
What is worst case timing?
 The maximum delays that may encounter which is worst case timing.
13
 Maximum delays in CMOS logic occur when operating voltage is minimum, maximum temperature and slow-
slow process condition.
Infer about propagation delay.
14  The propagation delay is defined as the average of the rising and falling propagation delays of the logic
module.
State Shannon’s expansion theorem and its function.
 In logic design we often have to deal with functions of many variables. We need a method to break down these
15 large functions into smaller pieces.
 Using the Shannon expansion theorem, we can expand a Boolean logic function F in terms of a Boolean
variable A, F= A.F (A=’1’) + A’.F (A=’0’)
Define power input.
16  We need to supply the power to the I/O cells and the logic in the core without introducing voltage drop or noise
is called as power input.
Infer about programmable Interconnect.
 Electrically programmable interconnections provide the routing path for the programmable logic blocks.
17
 Routing paths contain wire segments of varying lengths which can be interconnected via electrically
programmable switches.
Sketch the Xilinx SRAM.

18

Define power on reset.

 Each FPGA has its own power on reset sequences. All the flip flops as either SET or RESET.
19  After chip programming is complete the global SET /RESET signals forces all flip flops on the chip to know
state.
 This is important since it determine the initial state of a state machine.
 Label the five different types of terminations used in transmission line.
 Open-circuit or capacitance termination
 Parallel resistive termination
20
 Thevenin termination
 Series termination at the source parallel termination with a voltage bias
 Parallel termination with a series capacitance.
PART- B
Q.No Questions
1 Explain the classification of antifuse in detail with neat sketch.
Anti fuse
 An antifuse is the opposite of a regular fuse. It is normally an open circuit until you force a programming
current through it (about 5mA).
Poly diffusion antifuse
 In a poly diffusion anti fuse the high current density causes a large power dissipation in a small area, which
melts a thin insulating dielectric between poly silicon and diffusion electrodes and forms a thin, permanent and
resistive silicon link.
 The programming process also drives dopant atoms from the poly and diffusion electrodes into the link, and the
final level of doping determines the resistance value of the link.
 Actel calls its antifuse a programmable low-impedance circuit element.

Fig 1.1 Actel anti fuse

 The Fig 1.1 shows a poly–diffusion anti fuse with an oxide–nitride–oxide ( ONO ) dielectric sandwich of silicon
dioxide (SiO 2) grown over the n -type anti fuse diffusion, a silicon nitride (Si 3N 4 ) layer, and another thin
SiO 2 layer.
 The layered ONO dielectric results in a tighter spread of blown anti fuse resistance values than using a single-
oxide dielectric.
 The effective electrical thickness is equivalent to 10nm of SiO 2 and Si 3 N 4 has a higher dielectric constant than
SiO 2, so the actual thickness is less than 10 nm.
 Sometimes this device is called a fuse even though it is an anti fuse, and both terms are often used
interchangeably.
 To design and program an Actel FPGA, designers iterate between design entry and simulation. When they are
satisfied the design is correct they plug the chip into a socket on a special programming box, called an Activator
that generates the programming voltage.
 A PC downloads the configuration file to the Activator instructing it to blow the necessary anti fuses on the chip.
 When the chip is programmed it may be removed from the Activator without harming the configuration data and
the chip assembled into a system.
 One disadvantage of this procedure is that modern packages with hundreds of thin metal leads are susceptible
to damage when they are inserted and removed from sockets.
 The advantage of other programming technologies is that chips may be programmed after they have been
 assembled on a printed-circuit board—a feature known as in-system programming (ISP).
Metal–Metal Anti fuse
 The Fig 1.2 shows a metal–metal antifuse .The link is an alloy of tungsten, titanium, and silicon with a bulk
resistance of about 500 mW cm.

Fig 1.2 Metal–Metal antifuse

 There are two advantages of a metal–metal antifuse over a poly–diffusion antifuse. The first is that connections
to a metal–metal antifuse are direct to metal—the wiring layers.
 Connections from a poly–diffusion antifuse to the wiring layers require extra space and create additional
parasitic capacitance.
 The second advantage is that the direct connection to the low-resistance metal layers makes it easier to use
larger programming currents to reduce the antifuse resistance.
 The size of an antifuse is limited by the resolution of the lithography equipment used to makes ICs. The Actel
antifuse connects diffusion and polysilicon. Both these materials are too resistive for use as signal
interconnects.
 To connect the antifuse to the metal layers requires contacts that take up more space than the antifuse itself,
reducing the advantage of the small antifuse size.
 The antifuse is so small that it is normally the contact and metal spacing design rules that limit how closely the
antifuses may be packed rather than the size of the antifuse itself.
 Antifuse is resistive and the addition of contacts adds parasitic capacitance. The intrinsic parasitic capacitance
of an antifuse is small, but to this we must add the extrinsic parasitic capacitance that includes the capacitance
of the diffusion and poly electrodes and connecting metal wires.

 These unwanted parasitic elements can add considerable RC interconnect delay if the number of antifuses
connected in series is not kept to an absolute minimum.
2 Summarize the concepts of following:
(i) Static RAM
(ii) EPROM and EEPROM technology
(i) Static RAM
 This Xilinx SRAM configuration cell is constructed from two cross-coupled inverters as shown in Fig 2.1 and
uses a standard CMOS process.
 The configuration cell drives the gates of other transistors on the chip either turning pass transistors or
transmission gates on to make a connection or off to break a connection.
 Fig 2.1 Static RAM
 The advantages of SRAM programming technology are that designers can reuse chips during prototyping and
a system can be manufactured using ISP.
 This programming technology is also useful for upgrades a customer can be sent a new configuration file to
reprogram a chip, not a new chip. Designers can also update or change a system on the fly in reconfigurable
hardware.
 The disadvantage of using SRAM programming technology is that you need to keep power supplied to the
programmable ASIC for the volatile SRAM to retain the connection information.
(ii) EPROM and EEPROM technology
 Altera MAX 5000 EPLDs and Xilinx EPLDs both use UV-erasable electrically programmable read-only
memory cells as their programming technology. Altera's EPROM cell is shown in Fig 2.2.
 The EPROM cell is almost as small as an antifuse. An EPROM transistor looks like a normal MOS transistor
except it has a second, floating, gate (gate1 in Figure).
 Applying a programming voltage V PP usually greater than 12 V to the drain of the n- channel EPROM transistor
programs the EPROM cell.
 A high electric field causes electrons flowing toward the drain to move so fast they jump across the insulating
gate oxide where they are trapped on the bottom, floating, gate.
 These energetic electrons are hot and the effect is known as hot-electron injection or avalanche injection.
EPROM technology is sometimes called floating-gate avalanche MOS (FAMOS).

Fig 2.2 An EPROM transistor

 Electrons trapped on the floating gate raise the threshold voltage of the n- channel EPROM transistor
(Figure b). Once programmed, an n- channel EPROM device remains off even with VDD applied to the top
gate.
 An un programmed n- channel device will turn on as normal with a top-gate voltage of VDD.
 The programming voltage is applied either from a special programming box or by using on-chip charge pumps.
Exposure to an ultraviolet (UV) lamp will erase the EPROM cell (Figure c).
 An absorbed light quantum gives an electron enough energy to jump from the floating gate. To erase a part we
place it under a UV lamp.
 The manufacturer provides a software program that checks to see if a part is erased. The packages get hot
 while they are being erased, so that windowed option is available with only ceramic packages, which are more
expensive than plastic packages.
 Programming an EEPROM transistor is similar to programming an UV-erasable EPROM transistor, but the
erase mechanism is different.
 In an EEPROM transistor an electric field is also used to remove electrons from the floating gate of a
programmed transistor.
 This is faster than using a UV lamp and the chip does not have to be removed from the system. If the part
contains circuits to generate both program and erase voltages, it may use ISP.
3 Discuss in detail about the ACT Logic Module architecture.

Fig 3.1 The interconnect architecture used in an Actel ACT family FPGA
 The channel routing uses dedicated rectangular areas of fixed size within the chip called wiring channels
 Within the horizontal or vertical channels wires run horizontally or vertically respectively within tracks
 Actel divides the fixed interconnect wires within each channel into various lengths or wire segments
 The designer then programs the interconnections by blowing antifuses and making connections between wire
segments as shown in Fig 3.1.
ACT 1 Logic Module

Fig 3.2 ACT 1 horizontal and vertical channel architecture

Routing Resources
 22 horizontal tracks per channel for signal routing with three tracks dedicated to VDD, GND and the global
clock (GCLK)
 Eight vertical tracks per Logic Module are available for inputs. A vertical track that extends across the two
channels above the module and across the two channels below the module - Output Stub.
 One vertical track per column is a long vertical track (LVT) that spans the entire height of the chip as shown in
Fig 3.2.
Actel ACT 1 architecture

Fig 3.3 The Actel ACT architecture. (a) Organization of the basic logic cells. (b) The ACT 1 Logic Module. (c) An
implementation using pass transistors (without any buffering). (d) An example logic macro.

 We can build a logic function using an Actel Logic Module by connecting logic signals as shown in Fig 3.3(a) to
some or all of the Logic Module inputs, and by connecting any remaining Logic Module inputs to VDD or GND.
 As an example, Fig (c) shows the connections to implement the function F = A · B + B' · C + D.
ACT 2 and ACT 3 Logic Modules
 Using two ACT 1 Logic Modules for a flip-flop also requires added interconnect and associated parasitic
capacitance to connect the two Logic Modules.
 To produce an efficient two-module flip-flop macro we could use extra antifuses in the Logic Module to cut
down on the parasitic connections. However, the extra antifuses would have an adverse impact on the
performance of the Logic Module in other macros.
 The alternative is to use a separate flip-flop module, reducing flexibility and increasing layout complexity. In the
ACT 1 family Actel chose to use just one type of Logic Module.
 The ACT 2 and ACT 3 architectures use two different types of Logic Modules, and one of them does include
the equivalent of a D flip-flop.
 The ACT 2, C-Module is similar to the ACT 1 Logic Module but is capable of implementing five-input logic
functions.
 Actel calls its C-module a combinatorial module even though the module implements combinational logic. The
use of MUXes in the Actel Logic Modules can cause confusion in using and creating logic macros.

Fig 3.4 The Actel ACT 2 and ACT 3 Logic Modules. (a) The C-Module for combinational logic. (b) The ACT 2
S-Module. (c) The ACT 3 S-Module. (d) The equivalent circuit (without buffering) of the SE (sequential element). (e) The
sequential element configured as a positive-edge–triggered D flip-flop.
  For the Actel library, setting S = '0' selects input A of a two-input MUX. For other libraries setting S = '1' selects
input A.
 Similar problems arise in flip-flops and latches with MUX inputs. A safer way to label the inputs of a two-input
MUX is with '0' and '1', corresponding to the input selected when the select input is '1' or '0'.
 This notation can be extended to bigger MUXes but in the above Fig 3.4 (c) does the input combination S0 = '1'
and S1 = '0' select input D10 or input D01.
 The S-Module (sequential module) contains the same combinational function capability as the C-Module
together with a sequential element that can be configured as a flip-flop. Fig 3.4 (d) shows the sequential
element implementation in the ACT 2 and ACT 3 architectures.
4 Interpret the architecture of Xilinx LCA and XC3000 CLB with its speed-grade systems.

Fig 4.1 Xilinx LCA interconnect. (a) The LCA architecture (notice the matrix element size is larger than a CLB). (b) A
simplified representation of the interconnect resources. Each of the lines is a bus.

 The vertical lines and horizontal lines run between CLBs.

 The general-purpose interconnect joins switch boxes (also known as magic boxes or switching matrices)
shown in Fig 4.1.
 The long lines run across the entire chip. It is possible to form internal buses using long lines and the three-
state buffers that are next to each CLB.
 The direct connections (not used on the XC4000) bypass the switch matrices and directly connect adjacent
CLBs.
 The Programmable Interconnection Points (PIPs) are programmable pass transistors that connect the CLB
inputs and outputs to the routing network.
 The bidirectional (BIDI) interconnect buffers restore the logic level and logic strength on long interconnect
paths.
XC3000 CLB
 It has a 32-bit look-up table (LUT)
 CLB propagation delay is fixed (the LUT access time) and independent of the logic function
 7 inputs to the XC3000 CLB: 5 CLB inputs (A–E), and 2 flip-flop outputs (QX and QY)
 2 outputs from the LUT (F and G). Since a 32-bit LUT requires only five variables to form a unique address.
 Use 5 of the 7 possible inputs (A–E, QX, QY) with the entire 32-bit LUT (the CLB outputs (F and G) are then
identical)
 Split the 32-bit LUT in half to implement 2 functions of 4 variables each, choose 4 input variables from the 7
inputs (A–E, QX, QY).You have to choose 2 of the inputs from the 5 CLB inputs (A–E) as shown in Fig 4.2 then
 one function output connects to F and the other output connects to G.

Fig 4.2 The Xilinx XC3000 CLB

 We can split the 32-bit LUT in half, using one of the 7 input variables as a select input to a 2:1 MUX that
switches between F and G (to implement some functions of 6 and 7 variables).
Xilinx CLB Analysis
The use of a LUT has advantages and disadvantages:
 An inverter is as slow as a five-input NAND
 A LUT simplifies timing of synchronous logic
 Matched to large SRAM programming technology

Fig 4.3 Xilinx LCA timing model

Xilinx uses two speed-grade systems:
 Maximum guaranteed toggle rate of a CLB flip-flop (in MHz) as a suffix—higher is faster
 Delay time of the combinational logic in a CLB in ns—lower is faster
5 Explain the architecture of Altera Max with neat sketch.
Altera MAX 5000 and 7000
 Altera MAX 5000 devices and all MAX 7000 devices use a Programmable Interconnect Array (PIA), shown
in Fig 5.1. The PIA is a cross-point switch for logic signals traveling between LABs.
 The advantages of this architecture (which uses a fixed number of connections) over programmable
interconnection schemes (which use a variable number of connections) is the fixed routing delay.
 An additional benefit of the simpler nature of a large regular interconnect structure is the simplification and
improved speed of the placement and routing software.
 Fig 5.1 (a) illustrates that the delay between any two LABs, t PIA, is fixed.
 The delay between LAB1 and LAB2 (which are adjacent) is the same as the delay between LAB1 and LAB6
 (on opposite corners of the die).

Fig 5.1 A simplified block diagram of the Altera MAX interconnect scheme. (a) The PIA (Programmable Interconnect
Array) is deterministic—delay is independent of the path length. (b) Each LAB (Logic Array Block) contains a
programmable AND array. (c) Interconnect timing within a LAB is also fixed.

 It may seem rather strange to slow down all connections to the speed of the longest possible connection - a
large penalty to pay to achieve a deterministic architecture.
 However, it gives Altera the opportunity to highly optimize all of the connections since they are completely fixed.

Altera MAX 9000

 Fig 5.2 shows the Altera MAX 9000 interconnect architecture. The size of the MAX 9000 LAB arrays varies
between 4 x 5 (rows x columns) for the EPM9320 and 7 x 5 for the EPM9560.
 The MAX 9000 is an extremely coarse-grained architecture, typical of complex PLDs, but the LABs themselves
have a finer structure.
 Sometimes we say that complex PLDs with arrays that are themselves arrays (of macrocells) have a dual-grain
architecture.

Fig 5.2 The Altera MAX 9000 interconnect scheme. (a) A 4 x 5 array of Logic Array Blocks (LABs), the same size as the
EMP9400 chip. (b) A simplified block diagram of the interconnect architecture showing the connection of the Fast Track
buses to a LAB.

 In Fig 5.2 (b), boxes A, B, and C represent the interconnection between the FastTrack buses and the 16
macrocells in each LAB:
 Box A connects a macrocell to one row channel.

 Box B connects three column channels to two row channels.

  Box C connects a macrocell to three column channels.

Fig 5.3 The Altera MAX architecture. (a) Organization of logic and interconnect. (b) A MAX family LAB (Logic Array
Block). (c) A MAX family macrocell. The macrocell details vary between the MAX families—the functions shown here are
closest to those of the MAX 9000 family macrocells.
 Macro cell features:
 Wide
 Programmable AND array Narrow
 Fixed OR array
 Logic Expanders
 Programmable inversion
6 Discuss in detail about the following:
(i) Xilinx LCA and XC3000 CLB
(ii) Altera Flex architecture
(i) Xilinx LCA

Fig 6.1 Xilinx LCA interconnect

 (a) The LCA architecture (notice the matrix element size is larger than a CLB)
(b) A simplified representation of the interconnect resources.
 Each of the lines is a bus.
 The vertical lines and horizontal lines run between CLBs.
 The general-purpose interconnect joins switch boxes (also known as magic boxes or switching matrices).
 The long lines run across the entire chip. It is possible to form internal buses using long lines and the three-
state buffers that are next to each CLB.
 The direct connections (not used on the XC4000) bypass the switch matrices and directly connect adjacent
CLBs.
 The Programmable Interconnection Points (PIPs) are programmable pass transistors that connect the CLB
inputs and outputs to the routing network.
 The bidirectional (BIDI) interconnect buffers restore the logic level and logic strength on long interconnect
paths.
XC3000 CLB

Fig 6.2 XC3000 CLB

 A 32-bit look-up table (LUT)
 CLB propagation delay is fixed (the LUT access time) and independent of the logic function
 7 inputs to the XC3000 CLB: 5 CLB inputs (A–E), and 2 flip-flop outputs (QX and QY)
 2 outputs from the LUT (F and G). Since a 32-bit LUT requires only five variables to form a unique address
(32=25 ), there are several ways to use the LUT:
 Use 5 of the 7 possible inputs (A–E, QX, QY) with the entire 32-bit LUT (the CLB outputs (F and G) are then
identical)
 Split the 32-bit LUT in half to implement 2 functions of 4 variables each; choose 4 input variables from the 7
inputs (A–E, QX, QY).You have to choose 2 of the inputs from the 5 CLB inputs (A–E); then one function output
connects to F and the other output connects to G.
 We can split the 32-bit LUT in half, using one of the 7 input variables as a select input to a 2:1 MUX that
switches between F and G (to implement some functions of 6 and 7 variables).
(ii) Altera Flex Architecture
 The Fig 6.3 shows the interconnect used in the Altera FLEX family of complex PLDs. Altera refers to the FLEX
interconnect and MAX 9000 interconnect by the same name, Fast Track but the two are different because the
granularity of the logic cell arrays is different.
 The FLEX architecture is of finer grain than the MAX arrays—because of the difference in programming
technology.
 The FLEX horizontal interconnect is much denser than the vertical interconnect, creating an aspect ratio for the
interconnect.
  This imbalance is partly due to the aspect ratio of the die, the array and the aspect ratio of the basic logic cell,
the LAB.

Fig 6.3 The Altera FLEX architecture. (a) Chip floorplan. (b) LAB (Logic Array Block). (c) Details of the LE
(Logic Element)

 It appears that there is still approximately twice as much interconnect capacity in the horizontal direction as the
vertical. If we look inside the boxes A, B, and C in Fig 6.3 (b) we see that for individual lines on each bus:
 Box A connects an LE to two row channels.
 Box B connects two column channels to a row channel.
 Box C connects an LE to two column channels.
 There is some dependence between boxes A and B since they contain MUXes rather than direct connections,
but essentially there are twice as many connections to the column FastTrack as the row FastTrack, thus
restoring the balance in interconnect capacity.
(Note:*Blooms Level (R – Remember, U – Understand, AP – Apply, AZ – Analyze, E – Evaluate, C – Create)
PART A- Blooms Level : Remember, Understand, Apply
PART B- Blooms Level: Understand, Apply, Analyze, Evaluate(if possible)
Marks: 16 Marks, 8+8 Marks, 10+6 Marks)

Subject In charge Course Coordinator HOD IQAC

(Name & Signature) (Name & Signature)