EE537- Spring 2020

Digital Integrated Circuit Design

Instructor: Engr. Dr. Nasir Mohyuddin
Homework # 4, Due on 10th May 2020, Online Submission by 10:00pm PST

Problem # 1
Draw block diagram of 64 Bit adder for following configurations
1. Ripple Carry Adder (RCA)
2. Carry Select Adder (CSA)
3. Carry Look-ahead Adder (CLA) using 2-way look-ahead logic (CLA-2)
4. Carry Look-ahead Adder (CLA) using 4-way look-ahead logic (CLA-4)
Calculate their worst case delay, assume all AND/OR gates up to five inputs and two input XOR have
same delay and denote it by “D”. Further assume that both true and complemented input data bits are
available at the same time.

Problem # 2
Sum = A  B  C
Carry = MAJ (A, B, C)

Above are the logic equations for full adder cell.

a) Design a full adder cell with complex AOI gates having equal worst case rise and fall delay
and calculate delay from every input to every output using effort delay model. Assume n/p=
2 and each output has Cload = Input capacitance of minimum size 2-Input NAND gate. Further
assume that both true and complement values of input data are available.

b) With above full adder cells, design 16-bit ripple carry adder and calculate critical path delay
with effort delay model. Assume n/p= 2 and all the gates are minimum size.

c) With above full adder cells, design 16 bit carry skip adder with block size of 4. (Block of carry
skip adder is serial connection of full adder cells. Carry skip adder can be designed with these
blocks and skip logic that is serial connection of AND and OR gate)

d) Calculate critical path delay of above carry skip adder using delay values as:
(Tcell: delay from any input of full adder cell to any output of full adder cell,
Tand : delay of 2input AND gate, Tor: delay of 2input OR gate, Tor + Tand = Tcell)

e) Now assume that we can use variable block size in carry skip adder. Design fastest 16 bit carry
skip adder and calculate its critical path delay with values given in problem d)

f) Design 16 bit Carry look-ahead adder of group size 4. Implement group P and G cells using
complex AOI logic gate. Calculate delay from A0 (One input in 0th adder cell) to ~S15 (Sum
output of 15th adder cell) using effort delay model assuming n/p= 2 and all the gates are
minimum size.

1
 Let this path be the critical path of the adder. Compare the delay value with the delay value
calculated in b). How fast carry look-ahead adder is (in %) compared to ripple carry adder?
Problem # 3
Explain why the Barrel Shifter shown on slide 41 of the “Designing Arithmetic Building Blocks Ch
11 Part 2” implements two’s complement shift

Problem # 4
Draw dot diagram of 7x7 Wallace tree multiplier, showing all reduction steps and final output