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ECE 221 – Lecture14

CMOS Logic Devices

ECE 221 – Fall 2015


Implementation of Logic Gates
 Principles of operation of logic gates
 Transistor as a switch
 MOS transistor, CMOS process

 Reading assignment for this lecture


 Mano, Chapter 10.7-10.8 (CMOS devices)
ECE 221 - Fall 2016 2
Device Physics - basics
 Current = flow of electrical charges
 Two types of charge carriers
 Electrons
 Holes Metal
 Two types of semiconductors Oxide (SiO2)
 n-type, rich in electrons Si-substrate
Semiconductor (Si)
 p-type, rich in holes
 MOS = metal, oxide, semiconductor structure
 MOS transistor = voltage-controlled switch
 When control (gate) voltage = high (1), transistor is ON, conducts
 When control (gate) voltage = low (0), transistor is OFF
 There are two types of MOS transistors
 nMOS – conducting charges are electrons
 pMOS – conducting charges are holes

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The MOS Transistor
Polysilicon

Aluminum

nMOS
transistor

 nMOS transistor
 electrons in the channel conduct current when Gate is ON (1)
 pMOS transistor
 hoes in the channel conduct current when Gate is OFF (0)

ECE 221 - Fall 2016 4


The CMOS Process
 http://www.youtube.com/watch?v=gBAKXvsaEiw&feature=related
 http://www.youtube.com/watch?v=wXVpQipeEh8&feature=related

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Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2 (d) After development and etching of resist,
chemical or plasma etch of SiO
Si-substrate 2

(b) After oxidation and deposition Hardened resist


of negative photoresist SiO
2
Si-substrate
UV-light
Patterned (e) After etching
optical mask

Exposed resist
SiO
2

Si-substrate Si-substrate

(f) Final result after removal of resist


(c) Stepper exposure

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Transistor as a Switch
 We need a switch to turn the gate ON or OFF
 Switch implemented as MOS transistor
|VGS |
Non-zero resistance (R)
VGS  V T nMOS
Ron
S D
pMOS

 VT = threshold voltage, VGS = gate-to-source voltage


 VGS must be greater than VT to turn the transistor ON

 Two types of transistors/switches


 nMOS – turns ON when gate voltage is logic 1, OFF when logic 0
 pMOS – turns ON when gate voltage is logic 0, OFF when logic 1
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CMOS Inverter
N Well VDD

VDD PMOS 2l

Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS

NMOS
GND

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CMOS Inverter – Simplified Operation

V DD V DD

Vin = 0 V out V out


Vin = 1

Vin = 0, Vout = 1 Vin = 1, Vout = 0

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CMOS Inverter - Operation
Vdd = power supply (~1.5V)

V DD V DD

Rp

V out V out

Vin = 0 Vin = 1 R n

Vin = 0, Vout = 1 Vin = 1, Vout = 0

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CMOS NAND and NOR Gates

A
A
B
A B

Vout
A
Vout
B

A A B

NAND2 NOR2

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Integrated Circuits

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CMOS Process
CMOS = Complementary Metal-Oxide-Semiconductor

Fabrication technology, structure


Logic operation

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Advanced Metallization

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Advanced Metallization

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CMOS Inverter Layout
GND In VD D

A A’

Out

(a) Layout

A A’
n
p-substrate Field
+ + Oxide
n p
(b) Cross-Section along A-A’

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Perspectives

FinFET MOS transistor

ECE 221 - Fall 2016 17

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