Design and Implementation of

VLSI Systems
Lecture 02

Thuan Nguyen
Faculty of Electronics and Telecommunications,
University of Science, VNU HCMUS
Spring 2012
1

Ref: Neil H.E. Weste, David Money Harris; CMOS VLSI Design: A Circuit and Systems Perspective 4th
CONTENT

1 MOS Transistor

2 CMOS Logic

A) Combinational

B) Sequential

2
CONTENT

1 MOS Transistor

2 CMOS Logic

3
DOPED SEMICONDUCTOR
silicon
IMPACT OF DOPING ON 4.9951022 atoms in cm3
SILICON RESISTIVITY Resistivity 3.2  105 Ωcm

dope with
dope with
phosphorous
boron 
or arsenic 
p-type
n-type

1 atom in billion  88.6 Ωcm 1 atom in billion  266.14 Ωcm

1 atom in million  0.114 Ωcm 1 atom in million  0.344 Ωcm
1 atom in thousand  0.00174 Ωcm 1 atom in thousand  0.00233 Ωcm
4
 Electrons are more mobile/faster than holes
NMOS AND PMOS TRANSISTORS
Each transistor consists of a stack of a conducting gate, an insulating
layer of silicon dioxide and a semiconductor substrate (body or bulk)

nMOS transistor pMOS transistor

5
NMOS TRANSISTOR
Source Gate Drain
Polysilicon
SiO2

n+ n+

p bulk Si

g=0 (the gate is at a low voltage)

transistor is OFF
source and drain disconnected

g=1 (the gate is at a high voltage)

 transistor ON
 source and drain connected, transistor can be viewed
as a resistor
6
 NMOS PASS ‘0’ MORE STRONGLY THAN
‘1’
Source Gate Drain
Polysilicon
SiO2

n+ n+

p bulk Si

7
• What does ‘degraded 1’ mean?
PMOS TRANSISTOR
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

g=0 (the gate is at a low voltage)

transistor is ON
source and drain connected, transistor can be
viewed as a resistor

g=1 (the gate is at a high voltage)

 transistor OFF
8
 source and drain disconnected
 PMOS PASS ‘1’ MORE STRONGLY THAN
‘0’
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

9
• What does ‘degraded 0’ mean?
CONTENT

1 MOS Transistor

2 CMOS Logic

10
INVERTER GATE

VDD
A Y P1

A Y
N1

GND

An nMOS and pMOS make up an inverter 11

NAND GATE

P2 P1
Y
A N1

B N2

12
3-INPUT NAND GATE

P3 P2 P1

N1

N2
N3

13
AND GATE

N1

N2

P1 P2

14
Bad design because of degraded 0 and 1
CMOS LOGIC GATE IN GENERAL

pMOS
pull-up
network
inputs
output

nMOS
pull-down
network

15
WARM UP EXERCISE (0.1 POINT)

How CMOS AND2 gate, OR2 gate , NOR2 gate look like?

16
SERIES-PARALLEL COMBINATIONS
a a a a a
0 0 1 1
g1

 nMOS in Serial g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

a a a a a
0 0 1 1
g1
 pMOS in Serial g2
0 1 0 1
b b b b b
(b) ON OFF OFF OFF

a a a a a

 nMOS in Parallel g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

 pMOS in Parallel g1 g2 0 0 0 1 1 0 1 1
b b b b b 17
(d) ON ON ON OFF
SUMMARY
Source Gate Drain Source Gate Drain
Polysilicon Polysilicon
nMOS SiO2 SiO2
pMOS

n+ n+ p+ p+

p bulk Si n bulk Si

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pMOS strong ‘1’, weak ‘0’
nMOS strong ‘0’, weak ‘1’
SUMMARY

 GENERIC LOGIC GATE

pMOS pull up
nMOS pull down

 NOT
pMOS pull up
nMOS pull down

 NAND2:
pMOS parallel pull up
nMOS serial pull down

 NOR2:
pMOS serial pull up 19
nMOS parallel pull down
COMPOUND GATE
AND-OR-INVERT-22 (AOI22): Y = A.B + C.D

A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D 20
(f)

(e)
COMPOUND GATE

Y = (A + B + C).D Y = (A.B.C) + D

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TRANSMISSION GATE

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

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TRI-STATE BUFFER

The transmission gate has the same

truth table as a tristate buffer

It only requires two transistors but it is

a nonrestoring circuit.
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TRI-STATE INVERTER

A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A
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2:1 MULTIPLEXER (2:1 MUX)

 How many S
transistors do
you need to build D0 0
Y
a 2:1 MUX gate
D1 1
S

D0
S Y

1:12
1:13
1:14
1:15
1:16
1:17
1:18
1:19
1:20
1:21
1:22
1:23
1:24
1:25
1:26
1:27
1:28
1:29
1:30
1:31
1:32
1:33
1:34
1:35
1:36
1:37
1:38
1:39
1:40
1:41
1:42
1:43
1:44
1:45
1:46
1:47
1:48
1:49
1:50
1:51
1:52
1:53
1:54
1:55
1:56
1:57
1:58
1:59
2:00
1:00
1:01
1:02
1:03
1:04
1:05
1:06
1:07
1:08
1:09
1:10
0:12
0:13
0:14
0:15
0:16
0:17
0:18
0:19
0:20
0:21
0:22
0:23
0:24
0:25
0:26
0:27
0:28
0:29
0:30
0:31
0:32
0:33
0:34
0:35
0:36
0:37
0:38
0:39
0:40
0:41
0:42
0:43
0:44
0:45
0:46
0:47
0:48
0:49
0:50
0:51
0:52
0:53
0:54
0:55
0:56
0:57
0:58
0:59
0:01
0:02
0:03
0:04
0:05
0:06
0:07
0:08
0:09
0:10
1:11
0:11
End D1
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S
 2:1 INVERTING MUX
 Inverting multiplexer
 Use compound AOI22
 Or pair of tristate inverters
 Essentially the same thing
 Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
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4:1 MULTIPLEXER (4:1 MUX)

 4:1 mux chooses one of 4 inputs using two selects

 Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0
 Or four tristates

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

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D3
D LATCH

 When CLK = 1, latch is transparent

 D flows through to Q like a buffer
 When CLK = 0, the latch is opaque
 Q holds its old value independent of D
 a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q
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D LATCH DESIGN

 Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

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D LATCH OPERATION

Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

Q
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D FLIP-FLOP

 When CLK rises, D is copied to Q

 At all other times, Q holds its value

 a.k.a. positive edge-triggered flip-flop, master-slave flip-

flop

CLK
CLK
D
Flop

D Q
Q

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D FLIP-FLOP DESIGN

 Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

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D FLIP-FLOP OPERATION
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

Q
33
Q&A

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