Code No: R05410508 R05 Set No.

2
IV B.Tech I Semester Examinations,December 2011
ADVANCED COMPUTER ARCHITECTURE
Computer Science And Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. What are the uses of conditional or predicated instructions? Mention their advan-
tages and limitations. [16]

2. Write short notes on:

(a) Strided addressing.

(b) Little endian and big endian formats. [8+8]

3. (a) Explain how coherence and consistence are complementary.

(b) Briefly explain about cache coherence protocols. [8+8]

4. (a) Give the applications of the interrupt driven IO.

(b) Write about the bit interleaved parity. Give an example comparing RAID 3
and RAID 4/5 on small write updates. [8+8]

5. Consider a cache M1 and memory M2 hierarchy with the following characterics:

M1 : 16K words,50ns access time
M2 : 1M words,400ns access time. Assume eight word cache blocks and a set of 256
words with set associative mapping.

(a) Show the mapping between M2 and M1 .

(b) Calculate the effective memory access time with a cache hit ratio of h=0.95.
[16]

6. (a) What are the major functions of an I/O module?

(b) What is the difference between memory mapped I/O and isolated I/O?
(c) What is meant by direct memory access? [6+5+5]

7. Write the formula for total execution time. Explain the same with an example.
[16]

8. Write notes on pipelining. How does it differ from parallesim? [16]

?????

1
Code No: R05410508 R05 Set No. 4
IV B.Tech I Semester Examinations,December 2011
ADVANCED COMPUTER ARCHITECTURE
Computer Science And Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. (a) Explain how coherence and consistence are complementary.

(b) Briefly explain about cache coherence protocols. [8+8]

2. Write notes on pipelining. How does it differ from parallesim? [16]

3. Write the formula for total execution time. Explain the same with an example.
[16]

4. Consider a cache M1 and memory M2 hierarchy with the following characterics:

M1 : 16K words,50ns access time
M2 : 1M words,400ns access time. Assume eight word cache blocks and a set of 256
words with set associative mapping.

(a) Show the mapping between M2 and M1 .

(b) Calculate the effective memory access time with a cache hit ratio of h=0.95.
[16]

5. (a) Give the applications of the interrupt driven IO.

(b) Write about the bit interleaved parity. Give an example comparing RAID 3
and RAID 4/5 on small write updates. [8+8]

6. What are the uses of conditional or predicated instructions? Mention their advan-
tages and limitations. [16]

7. (a) What are the major functions of an I/O module?

(b) What is the difference between memory mapped I/O and isolated I/O?
(c) What is meant by direct memory access? [6+5+5]

8. Write short notes on:

(a) Strided addressing.

(b) Little endian and big endian formats. [8+8]

?????

2
Code No: R05410508 R05 Set No. 1
IV B.Tech I Semester Examinations,December 2011
ADVANCED COMPUTER ARCHITECTURE
Computer Science And Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Write the formula for total execution time. Explain the same with an example.
[16]

2. (a) Explain how coherence and consistence are complementary.

(b) Briefly explain about cache coherence protocols. [8+8]

3. Consider a cache M1 and memory M2 hierarchy with the following characterics:

M1 : 16K words,50ns access time
M2 : 1M words,400ns access time. Assume eight word cache blocks and a set of 256
words with set associative mapping.

(a) Show the mapping between M2 and M1 .

(b) Calculate the effective memory access time with a cache hit ratio of h=0.95.
[16]

4. Write notes on pipelining. How does it differ from parallesim? [16]

5. Write short notes on:

(a) Strided addressing.

(b) Little endian and big endian formats. [8+8]

6. (a) Give the applications of the interrupt driven IO.

(b) Write about the bit interleaved parity. Give an example comparing RAID 3
and RAID 4/5 on small write updates. [8+8]

7. What are the uses of conditional or predicated instructions? Mention their advan-
tages and limitations. [16]

8. (a) What are the major functions of an I/O module?

(b) What is the difference between memory mapped I/O and isolated I/O?
(c) What is meant by direct memory access? [6+5+5]

?????

3
Code No: R05410508 R05 Set No. 3
IV B.Tech I Semester Examinations,December 2011
ADVANCED COMPUTER ARCHITECTURE
Computer Science And Engineering
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
?????

1. Write short notes on:

(a) Strided addressing.

(b) Little endian and big endian formats. [8+8]

2. What are the uses of conditional or predicated instructions? Mention their advan-
tages and limitations. [16]

3. (a) What are the major functions of an I/O module?

(b) What is the difference between memory mapped I/O and isolated I/O?
(c) What is meant by direct memory access? [6+5+5]

4. (a) Give the applications of the interrupt driven IO.

(b) Write about the bit interleaved parity. Give an example comparing RAID 3
and RAID 4/5 on small write updates. [8+8]

5. Write notes on pipelining. How does it differ from parallesim? [16]

6. (a) Explain how coherence and consistence are complementary.

(b) Briefly explain about cache coherence protocols. [8+8]

7. Consider a cache M1 and memory M2 hierarchy with the following characterics:

M1 : 16K words,50ns access time
M2 : 1M words,400ns access time. Assume eight word cache blocks and a set of 256
words with set associative mapping.

(a) Show the mapping between M2 and M1 .

(b) Calculate the effective memory access time with a cache hit ratio of h=0.95.
[16]

8. Write the formula for total execution time. Explain the same with an example.
[16]

?????