 2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved.

This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.201 Give three examples of metastability that occur in everyday life, other than ones 3e7.1
discussed in this chapter.
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.202 Show how to build a flip-flop equivalent to the 74x109 positive-edge-triggered 3e7.7
J-K flip-flop using a 74x74 positive-edge-triggered D flip-flop and one or more
gates from a 74x00 package.
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.203 Repeat Drill 7.12, swapping AND and OR gates in the logic diagram. Is the new 3e7.10
state/output table the “dual” of the original one? Explain.
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.204 Analyze the clocked synchronous state machine in Figure X7.204. Write excita- 3e7.16
tion equations, excitation/transition table, and state/output table (use state names
A–H for Q1 Q2 Q3 = 000–111).

F i g u r e X 7. 2 0 4
Q1
Q2
Y

X D Q D Q D Q Q3
CLK CLK Q CLK

CLK
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.205 All of the state diagrams in Figure X7.205 are ambiguous. List all of the ambigu- 3e7.20
ities in these state diagrams. (Hint: Use Karnaugh maps where necessary to find
uncovered and double-covered input combinations.)

F i g u r e X 7. 2 0 5
W +X
(b)
W
X A B
(a) A B

X + Z′ X′ • Z W•Z
X′ Y 1

X+Y
1 C D
C D X•Y

W+Z

W′ X X′
X X • Z′ (d)
(c)
X′ • Y′ A X′ • Y′ • Z′ W′ • Y′ • Z′ B
A B

X′ • Y Z X • Z′ W Y
Z X Y•

Z′ C W′ • X′ • Y′ W′ • X′ • Z′ D
C D

Z′ Z Y′
X + Y′
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.206 Modify the state diagram of Figure 7-58 so that the machine goes into hazard 3e7.23
mode immediately if LEFT and RIGHT are asserted simultaneously during a turn.
Write the corresponding transition list.
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.207 Using ABEL and a GAL16V8 PLD, design a clocked synchronous state machine 3e7.33
that checks a serial data line for even parity. The circuit should have two inputs,
SYNC and DATA, in addition to CLOCK, and one Moore-type output, ERROR.
You should be able to do the job using just four states. Your program should use
an ABEL state_diagram. It should define the state assignments and include
comments that describe each state's meaning.
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.208 Write a new transition table and derive minimal-cost excitation and output equa- 3e7.36
tions for the state table in Table 7-5 using the “simplest” state assignment in
Table 7-6 and D flip-flops. Compare the cost of your excitation and output equa-
tions with the ones derived on page 565.
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.209 Suppose that the state machine with the equations derived on page 565 is to be 3e7.38
built using 74LS74 D flip-flops. What signals should be applied to the flip-flop
preset and clear inputs?
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.210 The output of a finite-memory machine is completely determined by its current finite-memory machine
input and its inputs and outputs during the previous n clock ticks, where n is a
finite, bounded integer. For example, Figure X7.210 shows the realization of a 3e7.56
finite-memory machine with one input and one output. Note that a finite-state
machine need not be a finite-memory machine; for example, a modulo-n counter
with an enable input and a “MAX” output has only n states, but its output may
depend on the value of the enable input at every clock tick since initialization.
Show how to realize the combination-lock machine of Table 7-11 as a finite-
memory machine.

F i g u r e X 7. 2 1 0
n flip-flops

IN D Q D Q D Q

CK CK CK

combinational logic OUT

CLOCK

D Q D Q D Q

CK CK CK

n flip-flops
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.211 A BUT flop may be constructed from an NBUT gate as shown in Figure X7.211 BUT flop
(An NBUT gate is simply a BUT gate with inverted outputs; see Exercise 6.31 for
the definition of a BUT gate.) Analyze the BUT flop as a feedback sequential cir-
cuit and obtain excitation equations, transition table, and flow table. Is this circuit 3e7.69
good for anything, or is it a flop?

Q1
X1
X2
Q2

F i g u r e X7 . 2 1 1
  2006 Pearson Education, Inc., Upper Saddle River, NJ. All rights reserved. This material is
protected under all copyright laws as they currently exist. No portion of this material may be
reproduced, in any form or by any means, without permission in writing by the publisher.
For exclusive use of adopters of the book Digital Design Principles and Practices,
Fourth Edition, by John F. Wakerly, ISBN 0-13-186389-4.

7.212 A clever student designed the circuit in Figure X7.79 to create a BUT gate. But 3e7.70
the circuit didn't always work correctly. Analyze the circuit and explain why.

74x139
1 4
1G 1Y0
5
1Y1 F i g ure X 7 . 2 1 2
2 6 74x04
A1 1A 1Y2
3 7 1 2
B1 1B 1Y3 Z1
U2
15 12
2G 2Y0
11
2Y1
14 10 74x04
A2 2A 2Y2
13 9 3 4
B2 2B 2Y3 Z2
U1 U2