VND920

Double channel high-side solid-state relay

Features

Type RDS(on) IOUT VCC

(1)
VND920 16 mΩ 35 A 36 V
1. Per channel with all the output pins connected to the
PCB.

■ CMOS compatible input SO-28 (double island)

■ Proportional load current sense
■ Shorted load protection
Description
■ Undervoltage and overvoltage shutdown
■ Overvoltage clamp The VND920 is a double chip device designed in
STMicroelectronics™ VIPower™ M0-3
■ Thermal shutdown technology. The VND920 is intended for driving
■ Current limitation any type of load with one side connected to
■ Protection against loss of ground and loss of ground. The active VCC pin voltage clamp
VCC protects the device against low energy spikes
(see ISO7637 transient compatibility table). Active
■ Very low standby power dissipation current limitation combined with thermal
■ Reverse battery protected shutdown and automatic restart protects the
device against overload.
The device integrates an analog current sense
output which delivers a current proportional to the
load current. The device automatically turns off in
the case where the ground pin becomes
disconnected.

Table 1. Device summary

Order codes
Package
Tube Tape and reel

SO-28 VND920 VND92013TR

February 2011 Doc ID 7767 Rev 5 1/26

www.st.com 1
Contents VND920

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 17
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 17
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 18
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 19

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 SO-28 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

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VND920 List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 13 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. VCC output diode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Current sense (9 V £ VCC £ 16 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 13. Thermal calculation according to the PCB heatsink area . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 15. SO-28 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Doc ID 7767 Rev 5 3/26

List of figures VND920

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. IOUT/ISENSE versus IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Over-voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. ILIM vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. On-state resistance vs VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. Input high-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 17. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 18. Input low-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 19. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 20. Maximum turn-off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. SO-28 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. Thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 24. Thermal fitting model of a double channel HSD in SO-28 . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. SO-28 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. SO-28 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. SO-28 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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VND920 Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

VCC 1

VCC OVERVOLTAGE
CLAMP DETECTION

UNDERVOLTAGE
DETECTION

GND 1
Power CLAMP

DRIVER
OUTPUT 1
INPUT 1 LOGIC
CURRENT LIMITER

VDS LIMITER

IOUT CURRENT
K SENSE 1
OVERTEMPERATURE
DETECTION

VCC 2

VCC OVERVOLTAGE
CLAMP DETECTION

UNDERVOLTAGE
DETECTION

GND 2
Power CLAMP

DRIVER
OUTPUT 2
INPUT 2 LOGIC
CURRENT LIMITER

VDS LIMITER

IOUT CURRENT
K SENSE 2
OVERTEMPERATURE
DETECTION

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Block diagram and pin description VND920

Figure 2. Configuration diagram (top view)

VCC 1 1 28 VCC1
GND 1 OUTPUT 1
INPUT 1 OUTPUT 1
CURRENT SENSE 1 OUTPUT 1
NC OUTPUT 1
NC OUTPUT 1
VCC 1 OUTPUT 1
VCC 2 OUTPUT 2
GND 2 OUTPUT 2
INPUT 2 OUTPUT 2
CURRENT SENSE 2 OUTPUT 2
NC OUTPUT 2
NC OUTPUT 2
VCC 2 14 15 VCC 2

Table 2. Suggested connections for unused and not connected pins

Connection / pin Current Sense N.C. Output Input

Floating X X X
Through 1KΩ Through 10KΩ
To ground X
resistor resistor

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VND920 Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

IS1 IS2

VCC1 VCC2 VF1 (*)

VCC1 VCC2

IOUT1
IIN1
OUTPUT1
INPUT1 VOUT1
VIN1 ISENSE1
CURRENT SENSE 1
VSENSE1
IOUT2
IIN2 OUTPUT2
INPUT2 VOUT2
VIN2 ISENSE2
CURRENT SENSE 2
GROUND1 GROUND2 VSENSE2

IGND1 IGND2

Note: VFn = VCCn - VOUTn during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to Absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics sure
program and other relevant quality document.

Table 3. Absolute maximum ratings

Symbol Parameter Value Unit

VCC DC supply voltage 41 V

-VCC Reverse DC supply voltage - 0.3 V
-Ignd DC reverse ground pin current - 200 mA
IOUT DC output current Internally limited A
-IOUT Reverse DC output current - 21 A
IIN DC input current +/- 10 mA
-3 V
VCSENSE Current sense maximum voltage
+ 15 V
Electrostatic discharge
(human body model: R = 1.5 KΩ; C = 100 pF)
– INPUT 4000 V
VESD
– CURRENT SENSE 2000 V
– OUTPUT 5000 V
– VCC 5000 V

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Electrical specifications VND920

Table 3. Absolute maximum ratings (continued)

Symbol Parameter Value Unit

Maximum switching energy

EMAX (L = 0.25 mH; RL = 0 Ω; Vbat = 13.5 V; 355 mJ
Tjstart = 150 °C; IL = 45 A)
Ptot Power dissipation TC ≤ 25 °C 6.25 W
Tj Junction operating temperature Internally limited °C
Tc Case operating temperature - 40 to 150 °C
Tstg Storage temperature - 55 to 150 °C

2.2 Thermal data

Table 4. Thermal data (per island)
Symbol Parameter Value Unit

Rthj-lead Thermal resistance junction-lead 20 °C/W

Rthj-amb Thermal resistance junction-ambient (one chip ON) 60(1) 45(2) °C/W
Rthj-amb Thermal resistance junction-ambient (two chips ON) 46(1) 32(2) °C/W
2
1. When mounted on a standard single-sided FR-4 board with 1cm of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.
2. When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35 µm thick) connected to
all VCC pins. Horizontal mounting and no artificial air flow.

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VND920 Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8 V < VCC < 36 V; -40 °C < Tj < 150 °C, unless
otherwise stated.

Table 5. Power
Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage 5.5 13 36 V

VUSD Undervoltage shutdown 3 4 5.5 V
VOV Overvoltage shutdown 36 V
IOUT = 10 A; Tj = 25 °C; 16 mΩ
RON On-state resistance IOUT = 10 A; 32 mΩ
IOUT = 3 A; VCC = 6 V 55 mΩ
VCLAMP Clamp voltage ICC = 20 mA 41 48 55 V
Off-state; VCC = 13 V;
10 25 µA
VIN = VOUT = 0 V
Off-state; VCC = 13 V;
IS Supply current 10 20 µA
VIN = VOUT = 0 V; Tj = 25 °C
On-state; VCC = 13 V; VIN = 5 V;
5 mA
IOUT = 0 A; RSENSE = 3.9 kΩ
IL(off1) Off-state output current VIN = VOUT = 0 V 0 50 µA
IL(off2) Off-state output current VIN = 0 V; VOUT = 3.5 V -75 0 µA
VIN = VOUT = 0 V; VCC = 13 V;
IL(off3) Off-state output current 5 µA
Tj = 125 °C
VIN = VOUT = 0 V; VCC = 13 V;
IL(off4) Off-state output current 3 µA
Tj = 25 °C

Note: VCLAMP and VOV are correlated. Typical difference is 5V.

Table 6. Switching (VCC = 13 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time RL = 1.3 Ω (see Figure 4) 50 µs

td(off) Turn-off delay time RL = 1.3 Ω (see Figure 4) 50 µs
dVOUT/dt(on) Turn-on voltage slope RL = 1.3 Ω (see Figure 4) See Figure 10 V/µs
dVOUT/dt(off) Turn-off voltage slope RL = 1.3 Ω (see Figure 4) See Figure 12 V/µs

Table 7. VCC output diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

VF Forward on voltage -IOUT = 5 A; Tj = 150 °C 0.6 V

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Electrical specifications VND920

Table 8. Logic inputs

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low-level voltage 1.25 V

IIL Low-level input current VIN = 1.25 V 1 µA
VIH Input high-level voltage 3.25 V
IIH High-level input current VIN = 3.25 V 10 µA
VI(hyst) Input hysteresis voltage 0.5 V
IIN = 1 mA 6 6.8 8 V
VICL Input clamp voltage
IIN = -1 mA -0.7 V

Table 9. Current sense (9 V ≤ VCC ≤ 16 V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOUT = 1 A; VSENSE = 0.5 V;

K1 IOUT/ISENSE 3300 4400 6000
Tj = -40 °C...150 °C
Current sense IOUT = 1 A; VSENSE = 0.5 V;
dK1/K1 -10 +10 %
ratio drift Tj = -40 °C...150 °C

IOUT = 10 A; VSENSE = 4 V;
K2 IOUT/ISENSE Tj = -40 °C; 4200 4900 6000
Tj= 25°C...150°C 4400 4900 5750
Current sense IOUT = 10A; VSENSE = 4V;
dK2/K2 -8 +8 %
ratio drift Tj = -40 °C...150 °C
IOUT = 30 A; VSENSE = 4 V;
K3 IOUT/ISENSE Tj = -40 °C 4200 4900 5500
Tj = 25 °C...150 °C 4400 4900 5250

Current sense IOUT = 30 A; VSENSE = 4 V;

dK3/K3 -6 +6 %
ratio drift Tj = -40 °C...150 °C
VCC = 6...16 V; IOUT = 0 A;
Analog sense
ISENSE0 VSENSE = 0 V; 0 10 µA
current
Tj = -40 °C...150 °C
VCC = 5.5 V; IOUT = 5 A;
Max analog 2 V
RSENSE = 10 kΩ
VSENSE sense output
voltage VCC > 8 V, IOUT = 10 A;
4 V
RSENSE = 10 kΩ
Sense voltage in
VSENSEH overtemperature VCC = 13 V; RSENSE = 3.9 kΩ 5.5 V
condition

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VND920 Electrical specifications

Table 9. Current sense (9 V ≤ VCC ≤ 16 V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Analog sense
output
RVSENSEH impedance in VCC = 13 V; Tj > TTSD; output open 400 Ω
overtemperature
condition
Current sense
tDSENSE To 90% ISENSE(1) 500 µs
delay response
1. Current sense signal delay after positive input slope.

Table 10. Protections(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

TTSD Shutdown temperature 150 175 200 °C

TR Reset temperature 135 °C
Thyst Thermal hysteresis 7 15 °C
VCC = 13 V 30 45 75 A
Ilim Current limitation
5 V < VCC < 36 V 75 A
Turn-off output clamp IOUT = 2 A; VIN = 0 V;
Vdemag VCC - 41 VCC - 48 VCC - 55 V
voltage L = 6 mH
Output voltage drop IOUT = 1 A;
VON 50 mV
limitation Tj = -40 °C...150 °C
1. To ensure long term reliability under heavy over-load or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles.

Table 11. Truth table

Conditions Input Output Sense

L L 0
Normal operation
H H Nominal
L L 0
Over-temperature
H L VSENSEH
L L 0
Under-voltage
H L 0
L L 0
Over-voltage
H L 0
L L 0
Short circuit to GND H L (Tj < TTSD) 0
H L (Tj > TTSD) VSENSEH
L H 0
Short circuit to VCC
H H < Nominal
Negative output voltage clamp L L 0

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Electrical specifications VND920

Table 12. Electrical transient requirements

ISO T/R Test level
7637/1
Test pulse I II III IV Delays and impedance

1 - 25V(1) - 50V(1) - 75V(1) - 100V(1) 2ms, 10Ω

2 + 25V(1) + 50V (1)
+ 75V (1)
+ 100V (1)
0.2ms, 10Ω
(1) (1) (1) (1)
3a - 25V - 50V - 100V - 150V 0.1µs, 50Ω
3b + 25V(1) + 50V(1) + 75V(1) + 100V(1) 0.1µs, 50Ω
4 - 4V(1) - 5V (1)
- 6V (1)
- 7V(1)
100ms, 0.01Ω
(1) (2) (2) (2)
5 + 26.5V + 46.5V + 66.5V + 86.5V 400ms, 2Ω
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.

Figure 4. Switching characteristics

VOUT

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf
t
ISENSE

90%

t
tDSENSE
INPUT
td(on) td(off)

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VND920 Electrical specifications

Figure 5. IOUT/ISENSE versus IOUT

IOUT/ISENSE

6500
6500

6000
6000
max.Tj=-40°C
5500
5500
max.Tj=25...150°C
5000
5000

min.Tj=25...150°C typical value

4500
4500

4000
4000 min.Tj=-40°C

3500
3500

3000
3000
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32

IOUT (A)

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Electrical specifications VND920

Figure 6. Waveforms

NORMAL OPERATION
INPUT
LOAD CURRENT
SENSE

UNDERVOLTAGE
VCC
VUSDhyst
VUSD
INPUT
LOAD CURRENT
SENSE

OVERVOLTAGE

VOV
VCC
VCC > VUSD VOVhyst
INPUT
LOAD CURRENT
SENSE

SHORT TO GROUND
INPUT
LOAD CURRENT
LOAD VOLTAGE
SENSE

SHORT TO VCC
INPUT
LOAD VOLTAGE
LOAD CURRENT
SENSE
<Nominal <Nominal

OVERTEMPERATURE
TTSD
Tj
TR

INPUT
LOAD CURRENT
VSENSEH
SENSE ISENSE=
RSENSE

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VND920 Electrical specifications

2.4 Electrical characteristics curves

Figure 7. Off-state output current Figure 8. High-level input current
IL(off1) (uA) Iih (uA)
9 5

8 4.5
Vin=3.25V
7 4

3.5
6
3
5
2.5
4
2
3
1.5
2
1

1 0.5

0 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 9. Input clamp voltage Figure 10. Turn-on voltage slope

Vicl (V) dVout/dt(on) (V/ms)
10 700

9.5
650
Iin=1mA
9 Vcc=13V
600
Rl=1.3Ohm
8.5
550
8
500
7.5
450
7
400
6.5

6 350

5.5 300

5 250
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (ºC)

Figure 11. Over-voltage shutdown Figure 12. Turn-off voltage slope

Vov (V) dVout/dt(off) (V/ms)

50 550

48
500
Vcc=13V
450
46 Rl=1.3Ohm
400
44
350
42
300
40
250
38
200
36
150
34
100
32 50

30 0
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

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Electrical specifications VND920

Figure 13. ILIM vs Tcase Figure 14. On-state resistance vs VCC

Ilim (A) Ron (mOhm)

100 50

90 45
Vcc=13V
80 40

70 35
Tc= 150ºC
60 30

50 25

40 20
Tc= 25ºC
30 15

20 10
Tc= - 40ºC
10 5

0 0
5 10 15 20 25 30 35 40
-50 -25 0 25 50 75 100 125 150 175
Tc (°C) Vcc (V)

Figure 15. Input high-level Figure 16. Input hysteresis voltage

Vih (V) Vhyst (V)

3.6 1.5

1.4
3.4
1.3
3.2
1.2
3
1.1

2.8 1

0.9
2.6
0.8
2.4
0.7
2.2
0.6

2 0.5
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175
Tc (°C) Tc (°C)

Figure 17. On-state resistance vs Tcase Figure 18. Input low-level

Ron (mOhm) Vil (V)

50 2.6

45
2.4
Iout=10A
40
Vcc=8V; 36V 2.2
35
2
30

25 1.8

20
1.6
15
1.4
10
1.2
5

0 1
-50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 75 100 125 150 175

Tc (ºC) Tc (°C)

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VND920 Application information

3 Application information

Figure 19. Application schematic

+5V

Rprot INPUT1 VCC1 VCC2

Dld
Rprot C. SENSE 1 OUTPUT1

Rprot INPUT2

μC
Rprot C. SENSE 2 OUTPUT2

GND1 GND2

RSENSE1,2
RGND
VGND DGND

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resistor in the ground line (RGND only)

This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1. RGND ≤ 600 mV / (IS(on)max).
2. RGND ≥ (-VCC) / (-IGND)
where - IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC < 0: during reverse battery situations) is:
PD = (-VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high-side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).

Doc ID 7767 Rev 5 17/26

Application information VND920

3.1.2 Solution 2: diode (DGND) in the ground line

A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600 mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
Series resistor in INPUT and STATUS lines are also required to prevent that, during battery
voltage transient, the current exceeds the absolute maximum rating.
Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the microcontroller I/O pins to latch-up.
The value of these resistors is a compromise between the leakage current of microcontroller
and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of
microcontroller I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax
Calculation example:
For VCCpeak = -100V and Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V
5 kΩ ≤ Rprot ≤ 65 kΩ.
Recommended values: Rprot = 10 kΩ .

18/26 Doc ID 7767 Rev 5

VND920 Application information

3.4 Maximum demagnetization energy (VCC = 13.5V)

Figure 20. Maximum turn-off current versus inductance

ILMAX (A)
100

B
C
10

1
0.01 0.1 1 10 100
L(mH)

A: Tjstart = 150°C single pulse

B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse

9,1,/

'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ 'HPDJQHWL]DWLRQ

*$3*&)7

Note: Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.

Doc ID 7767 Rev 5 19/26

Package and PCB thermal data VND920

4 Package and PCB thermal data

4.1 SO-28 thermal data

Figure 21. SO-28 PC board

Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm,
PCB thickness = 2 mm, Cu thickness = 35 µm, Copper areas: 0.5 cm2, 3 cm2, 6 cm2).

Table 13. Thermal calculation according to the PCB heatsink area

Chip 1 Chip 2 Tjchip1 Tjchip2 Note

ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb

OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb
ON ON RthB x (Pdchip1 + Pdchip2) + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1 = Pdchip2
ON ON (RthA x Pdchip1) + RthC x Pdchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1 ≠ Pdchip2

RthA = Thermal resistance Junction to Ambient with one chip ON

RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1 = Pdchip2
RthC = Mutual thermal resistance

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VND920 Package and PCB thermal data

Figure 22. Rthj-amb vs PCB copper area in open box free air condition

RTHj_am b
(°C/W)
70

60

50
RthA
40
RthB
30
RthC
20

10
0 1 2 3 4 5 6 7
PCB Cu heatsink area (cm ^2)/island

Figure 23. Thermal impedance junction ambient single pulse

Zth(°C/W)
100 0,5 cm ^2/is land

3 cm ^2/is land

6 cm ^2/is land

10

One channel ON
1
Tw o channels ON

0.1

0.01
0.0001 0.001 0.01 0.1 1 10 100 1000
time(s)

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Package and PCB thermal data VND920

Equation 1pulse calculation formula

Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tp ⁄ T

Figure 24. Thermal fitting model of a double channel HSD in SO-28

Tj_1 C1 C2 C3 C4 C5 C6

R1 R2 R3 R4 R5 R6
Pd1

C1 C2
Tj_2
R1 R2

Pd2

T_amb

Table 14. Thermal parameters

Area/island (cm2) 0.5 6

R1 (°C/W) 0.02
R2 (°C/W) 0.1
R3 (°C/W) 2.2
R4 (°C/W) 11
R5 (°C/W) 15
R6 (°C/W) 30 13
C1 (W.s/°C) 0.0015
C2 (W.s/°C) 7.00E - 03
C3 (W.s/°C) 1.50E - 02
C4 (W.s/°C) 0.2
C5 (W.s/°C) 1.5
C6 (W.s/°C) 5 8

22/26 Doc ID 7767 Rev 5

VND920 Package and packing information

5 Package and packing information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 25. SO-28 package dimensions

Table 15. SO-28 mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 2.65
a1 0.10 0.30
b 0.35 0.49
b1 0.23 0.32
C 0.50
c1 45° (typ.)
D 17.7 18.1
E 10.00 10.65
e 1.27
e3 16.51
F 7.40 7.60
L 0.40 1.27
S 8° (max.)

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Package and packing information VND920

5.2 SO-28 packing information

Figure 26. SO-28 tube shipment (no suffix)

Base Q.ty 28
Bulk Q.ty 700
Tube length (± 0.5) 532
A 3.5
B 13.8
C C (± 0.1) 0.6
B
All dimensions are in mm.

Figure 27. SO-28 tape and reel shipment (suffix “TR”)

Reel dimensions

Base Q.ty 1000

Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4

Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 16
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm. End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

24/26 Doc ID 7767 Rev 5

VND920 Revision history

6 Revision history

Table 16. Document revision history

Date Revision Changes

07-Jul-2004 1 Initial release.

Minor changes.
Current and voltage convention update (page 2).
Configuration diagram (top view) and suggested connections for
unused and n.c. pins insertion (page 2).
09-Sep-2004 2
6 cm2 Cu condition insertion in thermal data table (page 3).
VCC - output diode section update (page 4).
Revision history table insertion (page 34).
Disclaimers update (page 35).
03-May-2006 3 Suggested connections for unused and n.c.pins correction.
Document reformatted and restructured.
17-Dec-2008 4 Added content, list of figures and tables.
Added ECOPACK® packages information.
Updated following figures:
– Figure 13: ILIM vs Tcase
28-Feb-2011 5
– Figure 22: Rthj-amb vs PCB copper area in open box free air
condition

Doc ID 7767 Rev 5 25/26

 VND920

Please Read Carefully:

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