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Micoprocesador LG VCT49XYI PDF
Micoprocesador LG VCT49XYI PDF
Video-Controller-Text-IF-
Audio IC Family
Edition 12.12.2003
6251-573-1AI
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
Video-Controller-Text-IF-Audio IC Family
Contents
1-4 1. Introduction
1-4 1.1. Features
1-6 1.2. Chip Architecture
1-7 1.3. System Application
1-12 4. Specifications
1-12 4.1. Outline Dimensions
1-14 4.2. Pin Connections and Short Descriptions
1-19 4.3. Pin Descriptions
1-19 4.3.1. Supply Pins
1-19 4.3.2. IF Pins
1-19 4.3.3. Audio Pins
1-20 4.3.4. Video Pins
1-20 4.3.5. CRT Pins
1-21 4.3.6. Controller Pins
1-22 4.4. Pin Configuration
1-24 4.5. Pin Circuits
1-24 4.5.1. IF Pins
1-24 4.5.2. Audio Pins
1-25 4.5.3. Video Pins
1-25 4.5.4. CRT Pins
1-26 4.5.5. Controller Pins
1-28 4.6. Electrical Characteristics
1-28 4.6.1. Absolute Maximum Ratings
1-30 4.6.2. Recommended Operating Conditions
1-30 4.6.2.1. General Recommended Operating Conditions
1-31 4.6.3. Recommended Tuner Characteristics
1-31 4.6.3.1. Recommended Crystal Characteristics
1-32 4.6.3.2. Analog Input and Output Recommendations
1-33 4.6.4. Characteristics
1-33 4.6.4.1. Package Characteristics
1-33 4.6.4.2. Standby Power Consumption
1-34 4.6.4.3. Normal Power Consumption
1-34 4.6.4.4. Leakage Current
1-34 4.6.4.5. Test Input
1-34 4.6.4.6. Reset Input/Output
Contents, continued
1-56 5. Application
Video-Controller-Text-IF-Audio IC Family
Contents, continued
2-3 1. Introduction
2-3 1.1. Chip Architecture
2-3 1.2. Features
2-4 1.3. Overview
2-4 1.4. Analog TV Application
2-4 1.4.1. SAW Filter
2-4 1.4.2. Processing Overview
2-5 1.4.3. Initialization for Analog TV
2-5 1.4.4. Multistandard Configuration for B/G, L, I, D/K and M/N
2-5 1.4.5. Multistandard Configuration for L’
2-5 1.5. FM Radio
2-6 1.6. Using DRX with an IF frequency other than 38.9 MHz
2-6 1.6.1. I2C settings
2-6 1.6.2. SAW filter considerations
Contents, continued
Video-Controller-Text-IF-Audio IC Family
Contents, continued
3-4 1. Introduction
3-4 1.1. Chip Architecture
3-5 1.2. MSP Features
3-6 1.3. Application Fields
Contents, continued
Video-Controller-Text-IF-Audio IC Family
Contents, continued
4-4 1. Introduction
4-4 1.1. Chip Architecture
4-5 1.2. Video Features
Contents, continued
Video-Controller-Text-IF-Audio IC Family
Contents, continued
5-4 1. Introduction
5-4 1.1. Chip Architecture
5-4 1.2. Features
5-5 1.3. Overview
Contents, continued
Video-Controller-Text-IF-Audio IC Family
Contents, continued
6-7 1. Introduction
6-7 1.1. Chip Architecture
6-8 1.2. Features
6-9 1.3. Overview
6-9 1.4. Block Diagram
Contents, continued
Video-Controller-Text-IF-Audio IC Family
Contents, continued
Contents, continued
Video-Controller-Text-IF-Audio IC Family
Contents, continued
Volume 1:
General Description
Edition 12.12.2003
6251-573-1-1AI
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
Contents
1-4 1. Introduction
1-4 1.1. Features
1-6 1.2. Chip Architecture
1-7 1.3. System Application
1-12 4. Specifications
1-12 4.1. Outline Dimensions
1-14 4.2. Pin Connections and Short Descriptions
1-19 4.3. Pin Descriptions
1-19 4.3.1. Supply Pins
1-19 4.3.2. IF Pins
1-19 4.3.3. Audio Pins
1-20 4.3.4. Video Pins
1-20 4.3.5. CRT Pins
1-21 4.3.6. Controller Pins
1-22 4.4. Pin Configuration
1-24 4.5. Pin Circuits
1-24 4.5.1. IF Pins
1-24 4.5.2. Audio Pins
1-25 4.5.3. Video Pins
1-25 4.5.4. CRT Pins
1-26 4.5.5. Controller Pins
1-28 4.6. Electrical Characteristics
1-28 4.6.1. Absolute Maximum Ratings
1-30 4.6.2. Recommended Operating Conditions
1-30 4.6.2.1. General Recommended Operating Conditions
1-31 4.6.3. Recommended Tuner Characteristics
1-31 4.6.3.1. Recommended Crystal Characteristics
1-32 4.6.3.2. Analog Input and Output Recommendations
1-33 4.6.4. Characteristics
1-33 4.6.4.1. Package Characteristics
1-33 4.6.4.2. Standby Power Consumption
1-34 4.6.4.3. Normal Power Consumption
1-34 4.6.4.4. Leakage Current
1-34 4.6.4.5. Test Input
1-34 4.6.4.6. Reset Input/Output
1-35 4.6.4.7. I2C Bus Interface
1-35 4.6.4.8. IF Input
Contents, continued
1-56 5. Application
Release Note: This data sheet describes functions The VCT 49xyI, VCT 48xyI family offers a rich feature
and characteristics of the VCT 49xyI, VCT 48xyI- set, covering the whole range of state-of-the-art 50/
C4. 60 Hz TV applications.
– PSSDIP88-1/-2 package
1. Introduction – PMQFP144-2 package
– Submicron CMOS technology
The VCT 49xyI, VCT 48xyI is an IC family of high-qual-
ity single-chip TV processors. Modular design and – Low-power standby mode
deep-submicron technology allow the economic inte-
gration of features in all classes of single-scan TV – Single 20.25 MHz reference crystal
sets. The VCT 49xyI, VCT 48xyI family is based on – 8-bit 8051 instruction set compatible CPU
functional blocks contained and approved in existing
products like DRX 396xA, MSP 34x5G, VSP 94x7B, – Up to 256 kB on-chip program ROM
DDP 3315C, and SDA 55xx. – WST, PDC, VPS, and WSS acquisition
Each member of the family contains the entire IF, – Closed Caption and V-chip acquisition
audio, video, display, and deflection processing for 4:3 – Up to 10 pages on-chip teletext memory
and 16:9 50/60-Hz mono and stereo TV sets. The inte-
grated microcontroller is supported by a powerful OSD – Multi-standard QSS IF processing with single SAW
generator with integrated Teletext & CC acquisition – FM Radio and RDS with standard TV tuner
including on-chip page memory.
– TV-sound demodulation:
• all A2 standards
• all NICAM standards
Video & Sound IF
DRX 396xA • BTSC/SAP with MNR (DBX optional)
• EIA-J
– Baseband sound processing for loudspeaker chan-
nel:
Audio Processing
MSP 34x5G • volume and balance
• bass/treble or equalizer
• loudness and spatial effect (e.g. pseudo stereo)
• Micronas AROUND (virtual Dolby optional)
Video Processing VCT 49xyI
VSP 94x7B VCT 48xyI
• Micronas BASS and Subwoofer output
• further optional and licence requiring sound
enhancements as BBE, SRS Wow and Micronas
VOICE
Display & Deflection
– CVBS, S-VHS, YCrCb and RGB inputs
DDP 3315C
– 4H adaptive comb filter (PAL/NTSC)
– multi-standard color decoder (PAL/NTSC/SECAM)
Control, OSD, Text – Nonlinear horizontal scaling “panorama vision”
SDA 55xx
– Luma and chroma transient improvement (LTI, CTI)
– Non-linear color space enhancement (NCE)
Fig. 1–1: Single-chip VCT 49xyI, VCT 48xyI
– Dynamic black level expander (BLE)
– Scan velocity modulation output
– Soft start/stop of H-drive
– Vertical angle and bow correction
– Average and peak beam current limiter
– Nonlinear and dynamic EHT compensation
– Black switch off procedure (BSO)
Micronas
Typical TV Application: Eco CRT Basic CRT Basic 16/9 CRT LCD Emu
4x21
4x22
4923
4924
4931
4932
4933
4934
4x41
4x42
4943
4944
4x46
4947
4948
4951
4952
4953
4954
4956
4957
4958
4962
4963
4964
4966
4967
4968
4972
4973
4974
4976
4977
4978
4982
4983
4986
4987
4992
4993
4996
4997
49xy
SRS® WOW (SRS&TruBass&Focus) opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt
BBETM (High Definition Sound) opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt opt
4H adaptive comb filter y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y
Panorama scaler y y y y y y y y y y y y y y y y y y y y y
2nd RGB/YCrCb input y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y
Softmix 2nd RGB via fastblank y y y y y y y y y y y y y y y y y y y y y
CTI, LTI, histogram y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y
Dynamic EHT compensation y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y
Scan velocity modulation (SVM) y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y
Dynamic focus control y y y y y y y y y y y y y y y y y y y y y
ITU-656 Input or Output y y y y y y y y y
15.12.2003; 6251-573-1-1AI
Teletext, VPS, PDC, WSS y y y y y y y y y y y y y y y y y y y y y y
On-chip program memory JE JE JE JE JE JE JE JE IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG IFG
PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY PY
PY PY PY PY PY PY PY PY
Packages PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ PZ XM XM XM XM XM XM XM XM XM
PZ PZ PZ PZ PZ PZ PZ PZ
XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM XM
Memory/Package Definition: ROM: J = 128 kB; I = 256 kB; Flash: E = 128 kB; F = 256 kB; G = 512 kB; PY == PSSDIP88-1; PZ = PSSDIP88-2 (mirrored); XM = PMQFP144-2;
Common Features:
IF Processing: global alignment-free quasi split sound video and sound IF with single SAW, SIF-out (alternativvely to AIN1_R)
global mono audio, mono FM radio, standard selection, automatic volume control, volume, 1 sppeaker out
Audio Processing:
PSSDIP88: 2/3 line in, 2/1 line out (switchable); PMQFP144: 3 line in, 2 line out , 4xy1 versions in PSSDIP88: 3 line in, 1 line out
11 CVBS/YC/RGB/YCrCb inputs, 3 CVBS outputs, 1H NTSC comb filter, blackline detector
Color Decoder:
49xy: global color decoder; 48xy: NTSC only color decoder
Video Processing: contrast, saturation, tint, peaking, brightness, gamma, black and blue stretch, programmable R RGB matrix
Display Processing: analog RGB inputs, cutoff and white balance control, beamcurrent limiter
Deflection: H, V and E/W deflection, H and V EHT compensation, soft start/stop, black switch off, angle andd bow, protection circuit
Controller: CC, V-Chip, ROM, RAM, OSD, DAC, ADC, RTC, timer, watchdog, interrupt controller, UART, I2C bus, Flash version, patch modul
Miscellaneous: one crystal, few external components, alignment-free
VCT 49xyI, VCT 48xyI
5
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
SPEAKER
TAGC
AOUT
AIN
SIF
IFIN+ IF IF Sound Audio
IFIN- Frontend Processor Demodulator Processor
PROT
HOUT
HFLB
VERT
CVBS in Comb Color
Filter Decoder Display & EW
YCrCb in Video Panorama Video
Deflection SVM
RGB in Frontend Scaler Backend
Component Processor RGB out
CVBS out Interface RGB in
SENSE
RSW
I2C Master/
Bus Display I2C
Slicer Slave
Arbiter Generator
Timer
CRT
PWM RESETQ
24kB CPU Reset & Test
ADC
Char ROM 8051 Logic TEST
UART
Watchdog
RTC
256kB Memory Clock XTAL1
20kB XRAM
Prog ROM Interface I/O-Ports Generator XTAL2
20.25 MHz
AOUT1
AIN1 SAW Tuner
RGB/FB/C1 IFIN+
VOUT1 IFIN-
CVBS1/Y1
TAGC
AV1
I2C
ID1
4:3/16:9 CRT
AOUT2 H/V/EW
AIN2
C2
VOUT2 RGB/SVM
VCT 49xyI
CVBS2/Y2
VCT 48xyI SENSE
AV2
ID2
Loudspeaker
SPEAKER
C3
CVBS3/Y3
AIN3
Headphone
separate AIN3
AV3
only available in
PMQFP package
S-Video Video L - Audio - R
20.25 MHz
VOUT2
VOUT1 SAW Tuner
AOUT1 IFIN+
IFIN-
Mon
Y Cb Cr 4:3/16:9 CRT
C1 H/V/EW
CVBS1/Y1
AIN1
RGB/SVM
VCT 49xyI
VCT 48xyI
AV1
SENSE
S-Video Video L - Audio - R
C2
CVBS2/Y2
AIN2
Loudspeaker
AV2
available in
QFP package
S-Video Video L - Audio - R
1 MByte
CE# Flash
(e.g. Am29LV800B)
PSENQ
PSWEQ
DB[7-0]
VCT 49xyI
VCT 48xyI ADB[19-0]
WRQ
RDQ
1 MByte
CE# SRAM
(e.g. TC55VBM316)
Fig. 1–5: VCT 49xyI, VCT 48xyI application with external program and teletext memory
2. Functional Description
2.1. VCTI
2.2. DRX
2.3. MSP
2.4. VSP
2.5. DDP
2.6. TVT
3. Control Interface
Write Read
VCT 49xyI
IO- TVT
DRX MSP VSP
Port 8051
I2C M/S
Interface
int. I2C-Bus
DDP
Buffer
ext. I2C-Bus
Computer
4. Specifications
Fig. 4–1:
PSSDIP88-1: Plastic Staggered Shrink Dual In-line Package, 88 leads, 750 mil
Ordering code: PY or PZ
Weight approximately 9.46 g
Fig. 4–2:
PMQFP144-2: Plastic Metric Quad Flat Package, 144 leads, 28 × 28 × 3.4 mm3, 21 × 21 mm2 heat slug
Ordering code: XM
Weight approximately 10.1 g
NC = not connected
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
IN = Input Pin
OUT = Output Pin
SUPPLY = Supply Pin
PSSDIP88-2
PMQFP144-2
PSSDIP88-1
PSSDIP88-2
PMQFP144-2
PSSDIP88-1
PSSDIP88-2
PMQFP144-2
PSSDIP88-1
PSSDIP88-2
PMQFP144-2
PSSDIP88-1
PSSDIP88-2
4.3. Pin Descriptions lines to the power supply. Decoupling capacitors from
VSUPxx to GND have to be placed as closely as pos-
4.3.1. Supply Pins sible to these pins. It is recommended to use more
than one capacitor. By choosing different values, the
VSUP1.8DIG − Supply Voltage 1.8 V frequency range of active decoupling can be extended.
This pin is main and standby supply for the digital core
logic of controller, video, display and deflection pro-
cessing. 4.3.2. IF Pins
VSUP1.8FE − Supply Voltage 1.8 V VREFIF − Reference Voltage for analog IF (Fig. 4–8)
This pin is main and standby supply for the analog This pin must be connected to GND via a circuitry
video front-end. according to the application circuit. Low inductance
caps are necessary.
VSUP3.3FE − Supply Voltage 3.3 V
This pin is main and standby supply for the analog IFIN+, IFIN- − Balanced IF Input (Fig. 4–6)
video front-end. These pins must be connected to the SAW filter out-
put. The SAW filter has to be placed as close as possi-
VSUP3.3IO − Supply Voltage 3.3 V ble. The layout of the IF input should be symmetrical
This pin is main and standby supply for the digital I/O- with respect to GND.
ports.
SIF − 2nd Sound IF Output (Fig. 4–9)
VSUP3.3DIG − Supply Voltage 3.3 V Output level is set via I2C-Bus. An appropriate sound
This pin is main supply for the digital core logic of IF processor (e.g. MSP) can be connected to this pin.
and audio processing and digital video back-end. This pin is also configurable as audio input (see
Fig. 4–10).
VSUP3.3BE − Supply Voltage 3.3 V
This pin is main supply for the analog video back-end. TAGC − Tuner AGC Output (Fig. 4–7)
This pin controls the delayed tuner AGC. As it is a
VSUP5.0FE − Supply Voltage 5.0 V noise-shaped-I-DAC output, it has to be connected
This pin is main supply for the analog IF front-end. according to the application circuit.
VSUP5.0BE − Supply Voltage 5.0 V VREFAU – Reference Voltage for Analog Audio (Fig.
This pin is main supply for the analog video back-end. 4–14)
This pin serves as the internal ground connection for
VSUP8.0AU − Supply Voltage 8.0 V the analog audio circuitry. It must be connected to the
This pin is main supply for the analog audio process- GND pin with a 3.3 µF and a 100 nF capacitor in paral-
ing. lel. This pins shows a DC level of typically 3.77 V.
GNDDAC − Ground for 3.3 V Video DAC Supply AIN2 R/L – Audio 2 Inputs (Fig. 4–10)
The analog input signals for audio 2 are fed to these
VSUP3.3EIO − Supply Voltage 3.3 V pins. Analog input connection must be AC coupled.
This pin is main and standby supply for the extended
digital I/O-ports available in QFP package only. It is AIN3 R/L – Audio 3 Inputs (Fig. 4–10)
internally connected to VSUP3.3IO. The analog input signals for audio 3 are fed to these
pins. Analog input connection must be AC coupled.
GNDEIO − Ground for 3.3 V Extended I/O Supply
It is internally connected to GND. AOUT1 R/L – Audio 1 Outputs (Fig. 4–11)
Output of the analog audio 1 signal. Connections to
Application Note: these pins are intended to be AC coupled.
All GND pins must be connected to a low-resistive
ground plane underneath the IC. All supply pins must
be connected separately with short and low-resistive
AOUT2 R/L – Audio 2 Outputs (Fig. 4–11) XREF − DAC Current Reference (Fig. 4–20)
Output of the analog audio 2 signal. Connections to External reference resistor for DAC output currents,
these pins are intended to be AC coupled. typical 1 kΩ to adjust the output current of the D/A con-
verters. (see recommended operating conditions). This
SPEAKER R/L – Loudspeaker Outputs (Fig. 4–13) resistor has to be connected to ground as closely as
Output of the loudspeaker signal. A 1 nF capacitor to possible to the pin.
GND must be connected to these pins. Connections to
these pins are intended to be AC-coupled.
4.3.5. CRT Pins
SUBW – Subwoofer Outputs (Fig. 4–13)
Output of the subwoofer signal. A 1 nF capacitor and a HOUT − Horizontal Drive Output (Fig. 4–21)
10 kΩ resistor to GND must be connected to this pin. This open source output supplies the drive pulse for
Connections to this pin are intended to be AC-coupled. the horizontal output stage. An external pulldown
resistor has to be used. The polarity and gating with
the flyback pulse are selectable by software.
4.3.4. Video Pins
HFLB − Horizontal Flyback Input (Fig. 4–22)
VIN 1–11 − Analog Video Input (Fig. 4–15) Via this pin the horizontal flyback pulse is supplied to
These are the analog video inputs. A CVBS, S-VHS, the VCT 49xyI, VCT 48xyI.
YCrCb or RGB/FB signal is converted using the luma,
chroma and component AD converters. The input sig- VPROT − Vertical Protection Input (Fig. 4–22)
nals must be AC-coupled by 100nF. In case of an ana- The vertical protection circuitry prevents the picture
log fast blank signal carrying alpha blending information tube from burn-in in the event of a malfunction of the
the input signal must be DC-coupled. vertical deflection stage. If the peak-to-peak value of
the sawtooth signal from the vertical deflection stage is
VOUT 1-3 − Analog Video Output (Fig. 4–16) too small, the RGB output signals are blanked.
The analog video inputs that are selected by the video
source select matrix are output at these pins. SAFETY − Safety Input (Fig. 4–22)
This input has two thresholds. A signal between the
RIN, GIN, BIN − Analog RGB Input (Fig. 4–17) lower and upper threshold means normal function. A
These pins are used to insert an external analog RGB signal below the lower threshold or above the upper
signal, e.g. from a SCART connector which can be threshold is detected as malfunction and the RGB sig-
switched to the analog RGB outputs with the fast blank nals will be blanked.
signal. Separate brightness and contrast settings for
the external analog signals are provided. VERT+, VERT− − Vertical Sawtooth Output (Fig. 4–23)
These pins supply the symmetrical drive signal for the
FBIN − Fast Blank Input (Fig. 4–18) vertical output stage. The drive signal is generated
This pin is used to switch the RGB outputs to the exter- with 15-bit precision. The analog voltage is generated
nal analog RGB inputs. The active level (low or high) by a 4 bit current-DAC with an external resistor of
can be selected by software. 6.8 kΩ and uses digital noise shaping.
ROUT, GOUT, BOUT − Analog RGB Output (Fig. 4– EW − East-West Parabola Output (Fig. 4–24)
19) This pin supplies the parabola signal for the East-West
These pins are the analog Red/Green/Blue outputs of correction. The drive signal is generated with 15 bit
the back-end. The outputs are current sinks. precision. The analog voltage is generated by a 4 bit
current-DAC with an external resistor of 6.8 kΩ and
SVMOUT − Scan Velocity Modulation Output (Fig. 4– uses digital noise shaping.
19)
This output delivers the analog SVM signal. The D/A PWMV − PWM Vertical Output (Fig. 4–21)
converter is a current sink like the RGB D/A convert- This pin provides an adjustable vertical parabola with 7
ers. At zero signal the output current is 50% of the bit resolution and approx. 79.4 kHz PWM frequency.
maximum output current.
DFVBL − Dynamic Focus Vertical Blanking (Fig. 4–21)
VRD − DAC Reference Decoupling (Fig. 4–20) This pin supplies the blank pulse for dynamic focus
Via this pin the RGB-DAC reference voltage is decou- during vertical blanking period or a free programmable
pled by an external capacitor. The DAC output cur- horizontal pulse for horizontal dynamic focus genera-
rents depend on this voltage, therefore a pulldown tion. Alternatively it can be programmed as FIELD out-
transistor can be used to shut off all beam currents. A put, delivering even/odd field information.
decoupling capacitor of 4.7 µF in parallel to 100 nF
(low inductance) is required. SENSE − Measurement ADC Input (Fig. 4–27)
This is the input of the analog to digital converter for
the picture and tube measurement. Three measure- ADB0−ADB19 − Address Bus Output (Fig. 4–35)
ment ranges are selectable with RSW1 and RSW2. These 20 lines provide the CPU address bus output to
access external memory.
GNDM − Measurement ADC Reference Input
This is the reference ground for the measurement A/D DB0−DB7 − Data Bus Input/Output (Fig. 4–36)
converter. Connect this pin to GND. These 8 lines provide the bidirectional CPU data bus
to access external memory.
RSW1 − Range Switch1 for Measuring ADC (Fig. 4–
25) WRQ − Data Write Enable Output (Fig. 4–35)
These pin is an open drain pull-down output. During This pin controls the direction of data exchange
cutoff and white drive measurement the switch is off. between the CPU and the external data memory
During the rest of time it is on. The RSW1 pin can be device (SRAM).
used as second measurement ADC input for picture
beam current measurement. RDQ − Data Read Enable Output (Fig. 4–35)
This pin is used to enable the output driver of the
RSW2 − Range Switch2 for Measuring ADC (Fig. 4– external data memory device (SRAM) for read access.
26)
These pin is an open drain pull-down output. During PSENQ − Program Store Enable Output (Fig. 4–35)
cutoff measurement the switch is off. During white This pin is used to enable the output driver of the
drive measurement the switch is on. Also during the external program memory device (ROM/FLASH) for
rest of time it is on. It is used to set the range for white read access.
drive current measurement.
PSWEQ − Program Store Write Enable Output (Fig. 4–
35)
4.3.6. Controller Pins This pin is used to write into the external program flash
memory device.
XTAL1 − Crystal Input and XTAL2 Crystal Output (Fig.
4–28) XROMQ − External ROM Enable Input (Fig. 4–37)
These pins connect a 20.25 MHz crystal to the internal This pin must be pulled low to access the external pro-
oscillator. An external clock can be fed into XTAL2. gram memory. XROMQ has an internal pull-up resis-
tor.
RESETQ − Reset Input/Output (Fig. 4–29)
A low level on this pin resets the VCT 49xyI, EXTIFQ − Enable External Memory Interface Input
VCT 48xyI. The internal CPU can pull down this pin to (Fig. 4–37)
reset external devices connected to this pin. This pin must be pulled low to enable the external
memory interface. EXTIFQ has an internal pull-up
TEST − Test Input (Fig. 4–30) resistor.
This pin enables factory test modes. For normal opera-
tion, it must be connected to ground. Alternatively this STOPQ − Stop CPU Input (Fig. 4–37)
pins serves as subwoofwer output. Applying a low level during the input phase freezes the
real-time relevant internal peripherals such as timers
SCL − I2C Bus Clock (Fig. 4–31) and interrupt controller. STOPQ has an internal pull-up
This pin delivers the I2C bus clock line. The signal can resistor.
be pulled down by external slave ICs to slow down
data transfer. ENEQ − Enable Emulation Input (Fig. 4–37)
Only if this pin is set to low level, STOPQ and OCF are
SDA − I2C Bus Data (Fig. 4–31) operational. ENEQ has an internal pull-up resistor.
This pin delivers the I2C bus data line.
ALE − Address Latch Enable Output (Fig. 4–35)
P10−P13, P20−P23 − I/O Port (Fig. 4–32) This signal indicates changes on the address bus.
These pins provide CPU controlled I/O ports.
OCF − Opcode Fetch Output (Fig. 4–35)
P14−P17 − I/O Port (Fig. 4–33) A high level driven by the CPU during output phase
These pins provide CPU controlled I/O ports. Addition- indicates the beginning of a new instruction.
ally they can be used as analog inputs for the control-
ler ADC. RSTQ − Internal CPU Reset Input/Output (Fig. 4–38)
This pin is used for emulation purpose only. A low level
P24−P26, P30−P37 − I/O Port (Fig. 4–34) on this pin resets the CPU. It also indicates an internal
These pins provide CPU controlled I/O ports. reset of the CPU. RSTQ has an internal pull-up resis-
tor.
Fig. 4–3: PSSDIP88-1 package Fig. 4–4: PSSDIP88-2 package (pinning mirrored)
P24 / 656CLKIO
P25 / 656HIO
P26 / 656VIO
P30 / 656IO0
P31 / 656IO1
P32 / 656IO2
P33 / 656IO3
P34 / 656IO4
P35 / 656IO5
VSUP3.3DIG
VSUP1.8DIG
VSUP3.3EIO
VSUP5.0FE
VSUP5.0IF
RESETQ
GNDEIO
PSENQ
ADB10
XTAL1
XTAL2
ADB0
ADB1
ADB2
ADB3
GND
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
P22
P23
102
101
100
98
97
96
92
91
90
88
86
84
81
80
105
104
103
99
95
94
93
89
87
85
83
82
79
78
77
108
107
106
76
75
74
73
IFIN+ 109 72 P36 / 656IO6
IFIN- 110 71 P37 / 656IO7
VREFIF 111 70 VIN11
TAGC 112 69 VIN10
AIN1R / SIF 113 68 VIN9
AIN1L 114 67 VIN8
AIN2R 115 66 VIN7
AIN2L 116 65 VIN6
AIN3R 117 64 VIN5
AIN3L 118 63 VIN4
AOUT2R 119 62 VIN3
AOUT2L 120 61 VIN2
AOUT1R 121 60 VIN1
AOUT1L 122 59 VOUT1
SPEAKERR 123 58 VOUT2
SPEAKERL 124 57 VOUT3
VREFAU 125 56 VSUP1.8FE
VSUP8.0AU 126 55 GND
GND 127 VCT 49xyI, VCT 48xyI XM 54 GND
GND 128 53 VSUP3.3FE
VSUP5.0BE 129 52 EXTIFQ
TEST / SUBW 130 51 XROMQ
VERT+ 131 50 P10
VERT- 132 49 P11
EW 133 48 P12
RSW2 134 47 P13
RSW1 135 46 P14
SENSE 136 45 P15
GNDM 137 44 P16
FBIN 138 43 P17
RIN 139 42 P20
GIN 140 41 P21
BIN 141 40 SCL
SVMOUT 142 39 SDA
ROUT 143 38 DFVBL / FIELD
GOUT 144 37 PWMV
10
11
12
13
14
15
16
17
18
19
20
21
24
25
26
27
30
31
33
34
35
36
22
23
28
29
32
1
2
3
4
5
7
8
9
6
VSUP3.3BE
SAFETY
ALE
VRD
GND
GND
VSUP3.3DAC
GNDDAC
HFLB
PSWEQ
STOPQ
ENEQ
RDQ
WRQ
RSTQ
VSUP3.3IO
ADB11
ADB9
ADB8
ADB13
ADB14
ADB17
ADB18
ADB16
ADB15
ADB12
ADB7
ADB6
ADB5
ADB4
ADB19
BOUT
XREF
HOUT
VPROT
OCF
4.5.1. IF Pins
VSUP8.0AU
VSUP5.0FE
30 k
≈ 3.75 V
2k
+ GND
- Fig. 4–10: Input Pins: AIN1-3 R/L
GND
VSUP8.0AU
120 k
VSUP5.0FE
300
≈ 3.75 V
N
GND
6.6 pF
VSUP8.0AU
VSUP5.0FE 1.2k - 478k
300
125 k
≈ 2.5 V
≈ 3.75 V
GND
GND
Fig. 4–8: Supply Pin: VREFIF
Fig. 4–12: Output Pins: AOUT2 R/L
VSUP8.0AU
54 pF
VSUP8.0AU
3.8k - 60k
GND 300
GND
VSUP8.0AU VSUP5.0BE
125 k
VREF
≈ 3.75 V
GND GND
Fig. 4–14: Supply Pin: VREFAU Fig. 4–18: Input Pin: FBIN
VSUP5.0BE
4.5.3. Video Pins
N
VSUP3.3FE
to ADC GND
VRD
VSUP3.3FE int. ref.
voltage +
ref. current
VINx + V=1 150 -
- XREF
GND
GND
Fig. 4–20: Supply Pins: XREF, VRD
Fig. 4–16: Output Pins: VOUT 1-3
P/N VSUP3.3IO
Clamping P/N
P
VCM
GND
N
Fig. 4–17: Input Pins: RIN, GIN, BIN
GND
VSUP3.3IO VSUP5.0BE
VREF
N
GND
GND
Fig. 4–22: Input Pins: SAFETY, VPROT, HFLB
Fig. 4–26: Output Pin: RSW2
VSUP5.0BE
Flyback VSUP5.0BE
P
P P P
VERT-
N
VERT+
GND
N
Fig. 4–27: Input Pin: SENSE
GND
VSUP5.0BE
VSUP3.3IO
P N
P P P
XTAL1 XTAL2
N
N P
GND
GND
Fig. 4–28: Input/Output Pins: XTAL1, XTAL2
Fig. 4–24: Output Pin: EW
VSUP3.3IO
VSUP5.0BE
47k
P
to ADC
N N
N GND
GND Fig. 4–29: Input/Output Pin: RESETQ
Fig. 4–25: Input/Output Pin: RSW1
VSUP5.0BE VSUP3.3IO
P
N
GND
GND
Fig. 4–30: Input Pin: TEST
Fig. 4–35: Output Pins: ADB0-ADB19, WRQ, RDQ,
PSENQ, PSWEQ, ALE, OCF
VSUP3.3IO
VSUP3.3IO
P
N
GND
GND
VSUP3.3IO
47k
N
GND
VSUP3.3IO
to ADC N 47k
GND
GND
GNDEIO
Abbreviations:
tbd = to be defined
vacant = not applicable
positive current values mean current flowing into the chip
Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute
maximum rating conditions for extended periods will affect device reliability.
This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso-
lute maximum-rated voltages to this high-impedance circuit.
All voltages listed are referenced to ground (list voltages = 0 V) except where noted. ???
All GND pins must be connected to a low-resistive ground plane close to the IC.
Min. Max.
Min. Max.
II Input Current mA
IO Output Current mA
1)
Refer to Pin Circuits section 4.5. on page 24
Functional operation of the device beyond those indicated in the “Recommended Operating Conditions/Characteris-
tics” is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device.
All voltages listed are referenced to ground (list voltages = 0 V) except where noted. ???
All GND pins must be connected to a low-resistive ground plane close to the IC.
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For
power up/down sequences, see the instructions in volume 6.
RV Reset Voltage V
1)
A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the “Rec-
ommended Operating Conditions” must not be exceeded at worst case conditions of the application.
2)
PMAX variation: user-determined by application circuit for I/Os
RR Series Resistance – – 25 W
C0 Shunt Capacitance 3 – 7 pF
IF
Audio
Video
RGB
Deflection
4.6.4. Characteristics
If not otherwise designated under test conditions, all characteristics are specified for recommended operating condi-
tions (see Section 4.6.2. on page 1-30).
PTOT Total Power Dissipation VSUPxx − 2200 tbd mW recommended operating con-
ditions, all ports in input mode
IVSUP1.8DIG Current Consumption VSUP1.8DIG − 175 tbd mA
CI Input Capacitance – – 5 pF
4.6.4.8. IF Input
SAW Input
TOP = 15 − 20 − mVpp
− 77 − dBuV
Analog Front-end
Carrier Recovery
VIF AGC
Reference Voltage
VAINCL Analog Input Clipping Level for 2.00 − 2.25 VRMS fsignal = 1 kHz
Analog-to-Digital-Conversion
(VSUP8.0AU = 8 V)
VAout Signal Level at Audio Output 1.8 1.9 2.0 VRMS fsignal = 1 kHz
(VSUP8.0AU = 8 V) Volume 0 dB
Full Scale input
Signal Level at Audio Output 1.17 1.27 1.37 VRMS
(VSUP8.0AU = 5 V)
AAintoAout Gain from Analog Audio Input AINns1) −1.0 − +0.5 dB fsignal = 1 kHz
to Audio Output →
AOUTns1)
frAintoAout Frequency Response from −0.5 − +0.5 dB with resp. to 1 kHz
Analog Input to Audio Output Bandwidth: 0 to 20000 Hz
Speaker Output
VSpeaker Signal Level at Speaker Output 1.8 1.9 2.0 VRMS fsignal = 1 kHz
(VSUP8.0AU = 8 V) Volume 0 dB
Full-scale input
Signal Level at Speaker Output 1.17 1.27 1.37 VRMS
(VSUP8.0AU = 5 V)
1) “n” means “1”, “2”, or “3”; “s” means “L” or “R”
Subwoofer Output
VSubw Signal Level at Subwoofer Output 1.8 1.9 2.0 VRMS fsignal = 100 Hz
(VSUP8.0AU = 8 V) Volume 0 dB
Full-scale input
Signal Level at Subwoofer Output 1.17 1.27 1.37 VRMS
(VSUP8.0AU = 5 V)
from Analog Audio Input to AINns1) − 0.01 0.03 % Input Level = −3 dBr,
Audio Output → fsig = 1 kHz,
AOUTns1) unweighted 20 Hz...20 kHz
THDNICAM Total Harmonic Distortion + Noise − − 0.1 % 2.12 kHz, Modulator input
of NICAM Baseband Signal level = 0 dBref
dVFMOUT Tolerance of Output Voltage SPEAKERs1) −1.5 − +1.5 dB 1 FM-carrier, 50 µs, 1 kHz,
of FM Demodulated Signal AOUTns1) 40 kHz deviation; RMS
BTSC Characteristics (MSP Standard Code = 20hex, 21hex) DRX-Input: norm conditions
S/NBTSC S/N of BTSC Stereo Signal SPEAKERs1) tbd − − dB 1 kHz L or R or SAP, 100%
AOUTns1) modulation, 75 µs deempha-
S/N of BTSC-SAP Signal tbd − − dB
sis, RMS unweighted 0 to 15
kHz
Frequency Response of BTSC- −2.0 − 2.0 dB SAP, white noise, 10% Modu-
SAP, 50 Hz...9 kHz lation, MNR
fPilot Pilot Frequency Range 15.563 − 15.843 kHz standard BTSC stereo sig-
nal, sound carrier only
1)
“n” means “1”or “2” or “3”; “s” means “L” or “R”
2)
EIM refers to 75-µs Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation,
when the DBX encoding process is replaced by a 75-µs preemphasis network.
BTSC Characteristics (MSP Standard Code = 20hex, 21hex) DRX-Input: norm conditions
with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal
components)
S/NBTSC S/N of BTSC Stereo Signal SPEAKERs1) tbd − − dB 1 kHz L or R or SAP, 100%
AOUTns1) modulation, 75 µs deempha-
S/N of BTSC-SAP Signal tbd − − dB
sis, RMS unweighted
0 to 15 kHz
fPilot Pilot Frequency Range SIF 18.844 − 19.125 kHz standard FM radio
stereo signal
1)
“n” means “1”or “2” or “3”; “s” means “L” or “R”
VVIN Full-Scale Input Voltage 1.3 1.5 1.7 VPP min. AGC Gain
VVIN Full-Scale Input Voltage 0.4 0.5 0.6 VPP max. AGC Gain
XTALK Crosstalk, any Two Video Inputs – –53 – dB 1 MHz, –2 dBr signal level
THD VOUT Total Harmonic Distortion − −50 −46 dB Input: −2 dBr of main ADC
range,
CL ≤ 10 pF
1 MHz, 5 Harmonics
CL Load Capacitance − − 10 pF
Resolution EW − 15 − bit
VERT+
VOMIN Minimum Output Voltage VERT- − 0 − V Rload = 6.8 kΩ
Rxref = 1 K
RI Input Impedance 1 − − MΩ
tc Conversion Time − 10 − µs
ts Sample Time − 2 − µs
tAADR Address Access Data Read Time − 150 193 ns see ext. SRAM spec
tOEDR Output Enable Data Read Time − 90 94 ns see ext. SRAM spec
State S4 S5 S6 S1 S2 S3 S4
ADB[19:0]
tAAPR
DB[7:0] DIN DIN DIN
tOEPR tPRS tPRH
PSENQ tAPS tPW
tAADR
DB[7:0] DIN
tOEDR tDRS tDRH
RDQ tARS tRW
DB[7:0] DOUT
tDWS tDWH
WRQ tWW
PSWEQ tAWS
5. Application
CRT_MODUL
VCT_I UNIT
ANTENNA
D D
Tuner AGC JOKE
TUNER IF_in SAW_Filter
SAW-Filter
RGB
B_SW SVM RGB-SVM RGB-AMP
TDA6109 PICTURE TUBE
I²C SENSE DRIVER TDA6107
CON500
R_A
CVBS5
L_A
RinBinGin+FBin(Backend)
Y ,Cb ,Cr RGB+FB or C1 or Y, CR ,CB (Frontend)
DEFLECTION UNIT
ADVANCED - PIP
(OPTION)
ADVANCED-AUDIO
aditional RGB/YCbCr/V5
Passive AV5(in/out)
AV5
CVBS (option) 33V 33V
to Headphone Amp EW EW
CON702
VCT 49xyI, VCT 48xyI
ST1
ST2
B_SW
Tuner AGC
TDA8172
TDA8172
C CVBS C
SCART1
Hout Hout
Y/C
AV1
VCR/DVD
IF
Volume 1: General Description
REAR
RGB+FB 200V +13V -13V
P17
P15
P22
CON700
CON701
Ain1
Ain2
HFLB HFLB
Aout1
YCbCr
Aout2
TAGC
ST1
VPROT VPROT
12V
Ub1
GND
Vin8..11
SPEAKERR
RGB+FBin
ST2 CVBS/Y1
C2
Vin7
Vin6
SPEAKERL/(SIF)
CVBS/Y2 Vin5 12V
CVBS C4 POWER SUPPLY UNIT
Y/C Vin4
Y4
Vin3
Vin2 VCT49xyI PZ 5V 5V
5V
12V
Ub1
Vin1
GND
SAT
3V3 3V3
CVBS3out
AV2
SCART2
CVBS2out STANDBY.sch
CVBS1out STANDBY
P23
P10
SDA/SCL
P11
P13
ADW_P14
P16
P12
SWITCHED Ub
5V
12V
WP POWER
TDA16846 230V~
20,25MHz TDA16846
CON600
1V8S 1V8S
15.12.2003; 6251-573-1-1AI
EE-PROM STBY_L STBY_L
3V3S
GND
(OPTION)
MC14053
STEREO A_SW
KEY_BOARD - AUDIO_AMP UNIT
AUDIO3-4in
AUDIO-SWITCH
AV4
Y/C C4
LED LED
Y4
SERVICE
CVBS I²C
GND
3V3S
KB KB
FRONT
AUDIO-AMP
AV3
CVBS3 KEY BOARD
IR IR
YC4/CVBS3
TDA7263M Loudspeaker
CON300
AUDIO
DIGITAL PHOTO
TDA7263
HEADPHONE AMP
SERVICE CONNECTOR
to Aout2 (OPTION)
R_A
CON402
TL082C
L_A
HEADPHONE
A A
Micronas
ADVANCE INFORMATION
1 2 3 4 5 6 7 8
G G G G G G G G G G G G G G G G
TU200 TUNER-M SCART-1 SCART-2
SC102
75R
470k
( Temic 6002PH5 )
330p
470k
R227
470k
330p
330p
SC101 B2 B1 A1 A3 A5
G R230 R120 12V_V2
75R
75R 75R
R215
R214
Micronas
AGC
PWM
GND
SCL
SDA
Vin
33V
IF
IF
R102
15
15
1
3
5
7
9 75R
11
13
17
19
21
1
3
5
7
9
11
13
17
19
21
470R R212
C108
C228
C109
R254 R247
R101
R209
3
R100
2 5 47k 470R
1
2
3
4
5
7
9
0
10
11
G L204 470R G
1 4 A2
880n R103
G
0
FI200 470R C126 R118 Q201
2
4
6
8
2
4
6
8
J208 SAW-FILTER2 C122 Q202
12
14
16
18
20
10
12
14
16
18
20
33Vtuner R113 G
D R260 BC858B D
10 J280 G 330p 470R
R236
15k
J209 G B7
R213
470R
330p
15k
SCL 5V_mod HL 470R R206 R242
R235 10
10 C121 R127 J237
27.5 B4 G G
J241
8k2
R216
10 7.5mm BC848B
R105
10k
75R
R261 470k R249
470R
SDA J281 G
J210 R237 L-SC2 J239 J238
HR
J226
0805
12.5mm
330p 470R
75R
L205 C227 C128 10 15
R119
R-SC2
5Vtuner 27.5 G G G
R-SC1
L-SC1
J122 8k2 G G 910R
10u/0.4R 10k 330p 330p
R251 12.5mm ST1
6k8 CON403 ST2 R246 R231
R250
75R
D712 YC/CVBS_IN 10k R248 75R
R232
ZTK33 820R
SC1-r
SC1-l
1
2
3
4
5k1
ADVANCE INFORMATION
C234 J262
100u C249 C200
SIF Vsup5.0(IF) Vsup3.3(DIG) Vsup1.8 G G G
10n C242 C255 100n
2u2
2u2
15 J225 J273
10n 100n 10
C262
C261
G G GG G 30
R-SC1
J254 L-SC2
SC1-l
SC1-r
12.5mm to AUDIO-SWITCH
J229
12.5mm
(Y)
10u
G G G G G G G G S2R S2L
(Cb)
10u
L211
10u
G G
C217
100u
10u
C251
100n
100u
(C) (Cr)
10u
C216 J230 R-SC2
C236
C273
100u
C245
C219 L-SC1
10u
J207
10
L215
L214
FBin
Bin
Gin
Rin
2u2
G
J253
C259
V_SC1
C207 22pF
C206 22pF
20
C218
10u
100u
C244
C_SC2
V_SC2
3u3
10u
C235 C232
C246 L209
G G 10u Vsup1.8
C125
22.5
L_A
R_A
G from A-SW 100n 100n J260
C243 SC1_V
L212
C271
J268
J218 Ain2R
12.5mm
J202
Y200
J265
CVBS3
(Y-rear)
100n 10
12.5mm
8V G 12.5mm
20.25MHz
100n
C224
C222 C_4
Ain2L G G G G 100u
20 J240
100n
100u
J271
100n
C240 Y/V4
C241 CVBS5
100n 12,5mm
C211 C210
C231 J266
12V_V
J270 C260
7.5mm 2u2
7.5mm
STANDBY-UB
C229 J264
100n 12,5mm
100n
C213
C220
J252
J251
C201
100n 12.5mm
30
STANDBY-UB
100n
100n
C 100u C
C233
220n
100n
C203 B_SWA_SW R125 R123
C268
100n 100n 100n 47k 470R
1
2
3
4
5
6
7
8
9
10 J205
11 J206
12
13
14
15
16100n
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 C230
32
33
34 C263
35
36
37
38 C221
39
40 SC1_V
41 SC2_V
42 PIP_Video
43
44
100n
Volume 1: General Description
G G
7.5mm
7.5mm
Q101
C250 Q102
P22
P23
IFin-
Vin9
Vin8
Vin7
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
IC200 J259
GND
IFin+
GND
GND
GND
Vin11
Vin10
Vout1
Vout2
Vout3
Ain2L
Ain1L
12V_CRT SC2_V BC858B
Ain2R
TAGC
Aout1L
Aout1R
XTAL1
XTAL2
VREFIF
RESETQ
VREFAU
17.5mm
Ain1R/SIF
VSUP5.0IF
100u
VSUP5.0FE
VSUP1.8FE
SPEAKERL
SPEAKERR
VSUP8.0AU
VSUP3.3DIG
VSUP1.8DIG
Ain3L/Aout2L
Ain3R/Aout2R
R122
C239 BC848B
R501
22R
820R 100n
VCT49xyI PZ
100u
G J245 15
G G G G
J244 22,5mm
Q500 B8
D501 B9 G B7 SC1inL
BC548B CVBS5
B10 CVBS5 B6 33Vpip
PIP_Video
1N4148 B13 PIP_Video B5 Vsup3.3(PIP)
Rin
GND
VSUP5.0BE
TEST
VERT+
VERT-
EW
RSW2
RSW1
SENSE
GNDM
FBin
Rin
Gin
Bin
SVMout
Rout
Gout
Bout
VRD
XREF
VSUP3.3BE
GND
GND
VSUP3.3IO
VSUP3.3DAC
GNDDAC
SAFETY
HFLB
Hout
VPROT
SDA
SCL
PMMV/P21
DFVBL/P20
P17
P16
P15
ADW_P14
P13
P12
P11
P10
VSUP3.3FE
GND
88
87
86
85
84
83
82
81
80
79
78
74
73
72
71
70
69
68
67
65
64
63
62
61
60
58
57
56
55
52
50
49
48
46
45
FBin B1 SC1outL
17.5mm
10
15.12.2003; 6251-573-1-1AI
L207 J217 G A12 G
22.5mm
22.5mm
J220
17.5mm
1206
C214
10k 47
0805
J221 77
J223 75
22.5mm
J282 54
0805
J235 53
J233 51
100n
R233
100R 59
R224
R225
C257 66
17.5mm
J227
B B
VERT
A11 SIF
100u_3R
VERTQ
100n G G G G G G G
J213 0805
3k3( 0R)
3k3
J201 J224
J234
J216
1k2
100R
100R
IR
SD101
LED
C226
10u
17.5mm R245
PIP_R
WP
L206
C254
100u
R280
SDA SCL B15 PIP_R A9 L_AMP
R205
R207 270R
STANDBY-UB
R264 120k
R208
100u G PIP_G
PIP_FB J228
PIP_R
PIP_G C225 J222 76
PIP_B
SERVICE
STANDBY-UB
100u 150R 150R 150R 270R PIP_B A8 R_AMP
C264 PIP_H R239
C258
47n
47n
47n
PIP_V
100n G STBY_L A7 A3inL
(SDA95xx)
10k
R241
G G 100n Key board to GND
A6 5V_MOD
10k
G Vsup3.3 NVM ADR492 1xxx xxxx R243 L210
R238
R240 10k
C272 10k
0R
J267 10u
100u A5 SC2inL
7.5mm
10
J257 J200 J501 J502 R244 J236 30 PIP_H
J272
22k SVM 100n C4 PIP_H A4 A3inR
1k2
25 0805 0805 0805
R252
L213 C274
2k2
HFLB
10u C3 PIP_V A3 SC2outL
VPROT
33R
1k
R226
4u7
1k5
C507 12.5mm 1
R265 27k
G G
220n G 2 C2 SDA A2 SC2inR
33R
R507
G J269 15
C505
560p
C504
560p
C506
560p
C204 100n
C280 Vsup3.3(BE) 3
R505 33R
R288
R229 1k5
G 4 C1 SCL A1 SC2outR
C265
22u
C205
C266
100n
R509
PIP/YUV-MODUL
R204
RGB-DRIVER R219 5
ADVANCED-AUDIO-MODUL
EW
1206
8
7
6
5
9 G
BC858B BC858B BC858B ADR51D xxxx xxx0 xxxx xxx1
8 R512
PAD
PAD
PAD
PAD
PAD
A 7 G C508 EE-PROM A
22k
100k SCL SDA
R510
PAD201
PAD202
PAD203
PAD204
PAD205
6 1n
FACTORY CON
ST24Cxx (3.3V)
G
G
G
G
G
5 G
G
R511
33R
4 INDEX : RELEASE DATE : DEPARTMENT :
G G G PROJECT :
TDA6109
3 12V_CRT R513 R515 R517 C270 Micronas Application Engineering COSIMA-2
2.1 11.06.2003
2 G R 270R G 270R B 270R 100n NAME : No. : DOCUMENT :
CRT_MODULE
1 R503 1
SIEGFRIED KRUEGER
1
2
3
4
IC201
DATE : SHEET : OF :
D-79108 Freiburg (Germany)
G G G 220R G G G G G 14-Aug-2003 2 6
Hans Bunte Strasse 19
GND VCTI SIGNAL PART 2.1
Phone: +49-761-517-2912
1 2 3 4 5 6 7 8
58
59
to VCTI
10k 4 75R
R302 3
BC848B 4 3
2 G
C313 R301
100k J300 J310 J311 J312 1
D
1k 25 17 20 20
25V to Power Supply 2 1 D
A8 47u MUTE = L
C314
9
G G (1nF) IC301
J305 TDA7263M C315 R402 R415
22.5 75R 75R
MUTE
Vs
J303 100n 1000u
5
30
R319 C327 G G G G G
5 G G R362_rHR R363_r AV3_Y/CVBS
R_A NII_R 1000u
8 C316
1k5 OUT_R CN400
100n R404
100R 100R L402 33R R 3
R308 C356
A9 C346 C338 22n CON300 100u CON402 CON422 10u
G J405
1n
G 1
R G 1 3
L2
J306 10R 1
2 10 2 2 R403 33R
22.5 G R316 G 3 3 1
J304 4 J301 HEAD-PHONE-MG_L
II_R 4 L401
27.5mm 10 L
C325 1k CON4 10u C405 C406
R320
1 C341 R360_l R361_l C357
L_A NII_L L400 47n 47n
10
1k5 OUT_L
100n 100u 10u
1000u 100R HL 100R
C347
R309
1n
AUDIO_IN L404
10R
C
G
II_L
2
R306 AUDIO_SWITCH C401 1u
C
CON401 CON411 C408 R400
GND
1k A_SW 1 3
470p
C334 C312 P401
G 2 2
15.12.2003; 6251-573-1-1AI
1u 470R AV3_r
low = SC2 3 1
L403
6
R317 Q302 9
5k6 22k 22k C
G G TL082C IC302
R321 3
R350
Vs
22k 4 Z1
C352 10u 2 R356
HL IN-(1) R318 Z
1 5
10k OUT(1) 100k BC848B Z0 10
3 6
IN+(1) 47R INH J309
7 16
Vee Vdd 12VM
8
Vss
C353 10u R351 J242 2
G
6 R355 10
HR IN-(2)
B 7 B
10k OUT(2)
5 G G G
IN+(2) 47R
GND
12V_V2 C402
1
R354 G
C354 22k 4u7
4
C358 3V3standby
R352
10u
5k6
R410 R413
100n D400 100R 15k
R411 J401
LED
G G G G 10
470R CON404
1
CON444
5
TLHR4601 R412
1k8 KEY_BOARD
HEADPHONE_AMP IR
2
3
4
3
4 2
R405 R406 R407 R408 L- = 0.6V
100R 390R 1k2 2k7 5k6
ADVANCE INFORMATION
R409 G 5 1 G
L+ = 1.3V
CON5 CON5
J402
SW400 SW401 SW402 SW403 P- = 2V
3V3S 3V3S KB
12.5mm
P+ = 2.5V
C407
100n
L- L+ P- P+ * Matrix changed (KB wake up function)
refer also VCTI pin change P1.7 / ADW_P1.4
A G G Software 26.01 onwards A
NVM-edit ADR492 0xxx xxxx = key board to 3.3V
1xxx xxxx = key board to ground
INDEX : RELEASE DATE : DEPARTMENT : PROJECT :
2.1 12.06.2003 Micronas Application Engineering COSIMA-2
NAME : No. : DOCUMENT :
SIEGFRIED KRUEGER 1
DATE : SHEET : OF :
D-79108 Freiburg (Germany)
Micronas
D702
+13V
Micronas
1n4002 C702 V-AMP
220u
2
6
VERTQ C700 C701 IC700
TDA8172
1000u 100n
D R701 7 3 D
VERTQ
47k 2% A59EAK071X01
L700
5
FXC3B CON700
C722 V
R700 47k 2% 1
1 R703 R704 R705 .
VERT 4k7 1R5 NKS3 470R 2
R744 10nF V_ABL JOKE
VPROT Vsup3.3(BE)
not inserted
D701 C710 C712
4
ADVANCE INFORMATION
LL4148 . . . C713
100p 100V
R752 R753 R712 68n 0.22u R719 PICTURE TUBE
6k8 6k8 R702 not inserted
3k9
68n
68n
10n
2R2 2% M
10R
G D705 CON701
C752
C753
C751
* not inserted
CRT - BOARD
33k 2%
R710 LL4148 *
6k2 R737 -13V 1
2
R718
R743
C707 C706 H
33k 2% 3
100n
G G 1000u H_ABL
* TR700 1352.xxxxA
G_V DST-M2
J708 R725
HFLB
12.5mm 18k 8
D708 D707
L701
Vsup3.3(FE) D703 . * C708 28kV
C 1N4148 1N4148 BY228 C
H-AMP 5.6n 1.6kV R715 R716 R717
Volume 1: General Description
Ferrit-Spule
Q701 2R2 10k 1k
C703 H-DRIVE S2000T
6
5
R711 FOCUS
G D706
TR701 C709 4 L702 3
220u R708 2 3 0R62 . 2 1
1R R709 33V
2.2u 160V G2
47R C705 BA159 LIN-COIL-M R761
12V_H
1.8n 2kV
* J716 10 18k
J703 J781 19n 400V 5 4
12V 12V_EW C714 R745 R713 R714 . 3 1
.
11
.
100n
33n BYW74 R727 L703 9
G
C718 7
.
D713 39R G
LL4148 Q700 10u 200V 10R DZ not inserted not inserted 4n7 . 6.3V
LL4148 0.47u 400V 5 R729
Ub1
C734 3R9 METOX 1W 0R47 NKS2 CON702
J709 R720 C725 R730
C733
680n 250V
.
Hout J707 L705 6
12.5mm 100R 3 G_H
Bridge Coil 12V_H 5
1u BSP372-M 20
R721 R726 4
* 4
10k 5R6 3
D710
R731 2
15.12.2003; 6251-573-1-1AI
Ub1 Picture Tube 6
1
156V A59EAK071X01 10R NKS3
BA158
to CRT - BOARD
B B
L704 140V A51ERF135X70
G G E-W Coil
C727
20
H G G PAD703
G G_H C730 PAD
EW-PWM PWM EAST -WEST BDX53 PAD-COOL
C790_PWM
.
C790_A
1,5uF
Q781 330R Q782 R784 C716 33nF 100nF D711
4k7 R735 J719
R780 1 J701
J770 J780 C782 +13V
L705 1,2mH 820uH 1R NKS3 20
EW 100u 15
BA158
20 12.5mm 4k7 R719 -- 2R7 2% M C731
BC808C BC808C
V
.
A A
470p
R790 EW-Analog
6k8 R783 R785
C780 10k 1k8 Q780 INDEX : RELEASE DATE : DEPARTMENT : PROJECT :
C781
4.7u
10n 2.1 11.06.2003 Micronas Application Engineering COSIMA-2
BD241C
G NAME : No. : DOCUMENT :
G G G G G G G G SIEGFRIED KRUEGER 1 2
DATE : SHEET : OF :
D-79108 Freiburg (Germany)
ANALOG EAST -WEST BD241C Hans Bunte Strasse 19 14-Aug-2003 4 6
Phone: +49-761-517-2912 DEFLECTION 2.1
60
61
1 2 3 4 5 6 7 8
C604
J610 1206 alternativ R604
! 100k
IC604 D601 47n
J606 4 1 R606 R607
20 3k3 220k
R639 R602 R603 470k
3 2 LL4148
1
C606
1k8 R651 SFH617-P4 R601 1k
D600 3 220p Ub1 adjust
100R L604 1k
D 9 18 IC603 D
10mmFerrit Ub1 Picture Tube
C602 BA158 L600 with 156V TL431 R605
10u 1k 156V A59EAK071X01
R600
2
C600 140V A51ERF135X70
12k D602
100n L604_2
22u 16
Ub1
5mmFerrit
not in layout 2.1 BYW76 C607
R640 TR600 alternative C603 R632
IC600 C601 47k with 140V 330p 2kV 33k 5W
4.7n J602 22u 200V
14 5 J609 20
.
1206
C610 G
3.3n 4 3 R631
G
10k
C651
OP2 7 14 C641 R617
R630 G STBY_L
11 1 470R D652
3
5
J612_2 ** 100n
.
820R
220p TDA8132 IC601 P1
4.7n
5
R608 R614 D603_PFC D604
56p
C608 27k R611 4k7 L605 F603 1N4148
8 10 5 8 J603 2 6
16V 12V
R610
VCT 49xyI, VCT 48xyI
4.7n 33k .
2A_TR5 15
STTA506D BYV28-100
C612
3.9M 1% VR25
C616
C611
D606
6 12 220n C619
UF4007
C R627 100n C
C615
L603 10R 1 7
8V 5V
Volume 1: General Description
C609 C-COIL
.
R638
2 9 .
Q600 C617 C618 C620 C621
4k7 220n 4 100n
C626
33n 630V
C614
470u
820p 2,5% FKP2
220p 1600V
7 13 R612 . 470u 470u
R609
10R D605
L606 F602 J601
1M 1% VR25
P6NB80 10
TDA16846 R628_PFC * alternative BUZ334 15
2A_TR5
20
R619
C642
33k 5W
J608_1
.
220p
not inserted
BAV18 330p L4931C33 IC602
R626 C631 J608_2 1 3
470u Vin Vout 3V3S
120k 2% D612_PFC 25
11 C633
GND
C636
R618 C634 C635 100u
STTA506D
NTC-M 5 100n 100n
2
380V
J611_2
400V 12 470u
**
GND
C639 R613 G
15.12.2003; 6251-573-1-1AI
L602_PFC 1,8mH
PFC Spule
. C623 . 220k
1n4007
C644
33n 630V
D613 R625
D607
C627
B . L607 F601 B
! 1n 400V 1.5n 6
1n4007
25V to AUDIO AMP
220u 450V
.
D609
C624 D611_PFC 2A_TR5 1R2DZ
BYV28-200
G 100n
C622
L601
R621
BYW76
. ! C625 . 220k C630
.
1n4007
C640 (or UF5407) C628_PFC
470n .
TR602 1n 400V 1.5n 220pF 1,2kV
D608
1n4007
.
! . 470p
C629_PFC C632
D610
! 1u 400V J616 R623
R620_PFC 13 2k2
4k7 T1
Line Filter 1
T1
! C638 1000u
230V~ SW600 J615
CON600
.
F600 T3
1 3 330n
2
GND_A
1 Main Fuse
2 4 MECH600
NETZ
R624
GDE S 95
G6126
C605 0 0
.
SMT-COOL 15 4
T2
! + -
J_S40 0.1u 2
2
( Alternativ GDE S 40 with Jumper J_S40 ) GL600 SMT-M2 C637
22,5mm BRUECKE-M
G
.
2
1
A A
2.2n 3kV
PAD-G PAD-G PAD-G PAD-G CON601 alternative !
DEGAUSS
R622 INDEX : RELEASE DATE : DEPARTMENT : PROJECT :
PAD
PAD
PAD
PAD
G Micronas Application Engineering COSIMA-2
2.1 11.06.2003
PAD602
PAD602
PAD601
PAD600
8.2M
NAME : No. : DOCUMENT :
G
G
G
G
! SIEGFRIED KRUEGER 1
G DATE : SHEET : OF :
D-79108 Freiburg (Germany)
** not included with PFC
Micronas
ADVANCE INFORMATION
1 2 3 4 5 6 7 8
J810
33V 33Vtuner
15
Micronas
J813
12V 12V_V
22.5mm
J815
J864
D 12.5mm D
12V_HP
J859 20
12V_CRT
27.5mm J812
1 3
Vin Vout 8V
7.5mm
IC803
GND
LE80CZ
2
G
ADVANCE INFORMATION
from POWER-SUPPLY
G
5Vpip
J855
25
Vsup5.0(BE)
SWITCHED Ub
3V3S
IC806 J863
MC269D3.3 17,5mm
3 2
Vin Vout Vsup3.3(BE)
R858 C835 J853
GND
C U1 to 3V3s 25 C
120R 100u Vsup3.3(FE)
IC853 R864 J842
R857
1
Volume 1: General Description
4 1 30 J845
to PIN11 IC600 OP1 C862 Vsup3.3(PIP)
150R 1% C860 12
3 2 4k7
P2 to D652 8R2 1%
10u 100u
SFH617-P4 R865 Vsup3.3(DIG)
C861
100n
T1 T1 ! G G G G G
R860
T1..T3/380V to POWER SUPPLY 100k
Q850
(SMT)
alternative
BT137-M R861_2
T2
68R
R861 IC855 !
6 1
220R 4 2
T3 C1 to VCTI Pin76
PTC IL4216
D850 R850 J850
380V ! 20
ZPY18 68R PRIMARY SECONDARY Vsup3.3
R859
220R
3V3standby
15.12.2003; 6251-573-1-1AI
IC850 J850_2
B D851 L850 12.5mm B
8
7
6
5
TR850
alternative
10u
1N4934 C854 C855 R854
470u 15k/1%
470u
TNY253 STANDBY-T
J852
20
! R852 J851
39R Vsup1.8
IC852 25
STAND BY Ub
1
2
3
4
4 1 IC807
MC33269DT
(2V)
3 2 R853 3 2
! 10k Vin Vout 1V8S
SFH617-P4
GND
1
R851 !
100R C853
1
3 100n
R863
C851 IC851
C850 1n/1kV C852 R855
100n 56p TL431 8k2/1% 820R 1%
2
R862
R856 C819 470R 1% C818
GND 0R
10u
C815
100n
100u
A A
alternative G G G G G G G G
1 2 3 4 5 6 7 8
62
ADVANCE INFORMATION VCT 49xyI, VCT 48xyI
Volume 1: General Description
Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-573-1-1AI retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Volume 2:
DRX - Analog TV IF-
Demodulator
Volume 2: DRX - Analog TV IF- Demodulator
Contents
2-3 1. Introduction
2-3 1.1. Chip Architecture
2-3 1.2. Features
2-4 1.3. Overview
2-4 1.4. Analog TV Application
2-4 1.4.1. SAW Filter
2-4 1.4.2. Processing Overview
2-5 1.4.3. Initialization for Analog TV
2-5 1.4.4. Multistandard Configuration for B/G, L, I, D/K and M/N
2-5 1.4.5. Multistandard Configuration for L’
2-5 1.5. FM Radio
2-6 1.6. Using DRX with an IF frequency other than 38.9 MHz
2-6 1.6.1. I2C settings
2-6 1.6.2. SAW filter considerations
1. Introduction
SPEAKER
TAGC
AOUT
AIN
SIF
VERT
CVBS in Comb Color
Filter Decoder Display & EW
YCrCb in Video Panorama Video
Deflection SVM
RGB in Frontend Scaler Backend
Component Processor RGB out
CVBS out Interface RGB in
SENSE
RSW
I2C Master/
Bus Display I2C
Slicer Slave
Arbiter Generator
Timer
CRT
PWM RESETQ
24kB CPU Reset & Test
ADC
Char ROM 8051 Logic TEST
UART
Watchdog
RTC
256kB Memory Clock XTAL1
20kB XRAM
Prog ROM Interface I/O-Ports Generator XTAL2
Fig. 1–1: Block diagram of the VCT 49xyI, VCT 48xyI highlighting the DRX Parts
• Digital IF processing for the following standards: • Programmable standard specific digital group delay
B/G, D/K, I, L/L’, and M/N equalization
DRX
IF Frontend IF Processor
Tuner Tuner
Clock D/A
clk20.25 AGC AGC
Generator
IFIN+ Group
Carrier Video tuner
TOP A/D Filtering Delay D/A
IFIN- Recovery AGC cvbs
Equalizer
VSUP5.0FE
SIF
I2C D/A SIF
VSUP5.0IF AGC
Interface
1.4. Analog TV Application These signals are available from conventional tuners.
32.4 MHz
7.7 MHz
7.7 MHz
FM Radio 88...108MHz
32 40
Audio
2nd SIF
1.6. Using DRX with an IF frequency other than Table 1–2: IF_FREQ register values
38.9 MHz
TV Setting for Setting for Setting for
Internally, the DRX mixes the wanted picture carrier
Std. 38.0 MHz 45.75 MHz 58.75 MHz
down to a frequency that corresponds to the typical
channel raster of the selected standard, e.g. 7 MHz for M/N 320 (0x140) 397 (0x18D) 526 (0x20E)
B, 8 MHz for G, D/K, I, L and L’, and 6 MHz for M/N.
This is performed using a PLL (later called LO-PLL) SAW X6894 X6964 X6989
that is set to a frequency corresponding to the IF fre- type*
quency minus the above-mentioned channel raster.
Only for L’, the situation is different, since the default IF
is 32.9 MHz and the mixing frequency must be 8 MHz *: example SAW types
higher than the picture carrier frequency. The reason
for this is the mirrored RF spectrum of L’. The values labeled “not recommended” are due to
restrictions of available SAW filters.
Table 1–1: Default settings of LO_PLL in MHz
Example 1: Set M/N standard with 45.75 MHz IF
TV standard Channel Default LO-PLL
width <0x82 0x10 0x00 0x20 0x00 0x02> ’std.M/N
<0x82 0x10 0x10 0x22 0x01 0x8D> ’IF_FREQ
B 7 31.9
Example 2: Set B standard with 38.0 MHz IF
G, D/K, I, L 8 30.9
<0x82 0x10 0x00 0x20 0x01 0x03> ’std.B
L’ (IF=32.9) 8 40.9
<0x82 0x10 0x10 0x22 0x01 0x36> ’IF_FREQ
M/N 6 32.9
Example 3: Set L standard with 38.9 MHz IF
2. Functional Description Table 2–1: TOP setting (for 21 dB SAW insertion loss)
Note: The TOP is the tuner input voltage at which the 3 111
IF circuit (e.g. the DRX) begins to reduce the
tuner gain. Thus, above this voltage the tuner 4 109.7
output voltage remains nearly constant.
5 108.3
6 107
Of course, the gain of the tuner is only allowed to be
reduced if the S/N is sufficiently high. A level of 7 105.7
60...70 dBµV at the antenna input is a typical value.
8 104.3
On the other hand, the output voltage of the tuner has
to be limited to prevent the tuner from generating inter- 9 103
modulation. 105...110 dBµV is a common range for the
maximum tuner output level. Hence, with a tuner gain 10 101.7
of 35...45 dB the input voltage requirement 11 100.3
(60...70 dB µV) is achieved automatically.
12 99
As the DRX is able to measure the tuner output volt-
age very accurately, the desired maximum tuner out- 13 97.7
put voltage can be set with TOP_SET_BS[3:0].
14 96.3
The values in Table 2–1 refer to the wanted channel. A
headroom for adjacent channels which may have 15 95
higher levels, must be taken into account.
The PLL incorporates its own AFC function and pro- In case of ADC range overflow due to very strong adja-
vides the frequency offset from the desired IF fre- cent channels, the tuner gain is reduced, too
quency for external use (AFC_DEV). A special digital (TAGC_HR).
validation algorithm allows long frequency lock at
100% modulation. Additionally, the PLL aligns the digi-
tally calculated Nyquist slope to the picture carrier fre- 2.7. Group Delay Equalizing
quency.
The group delay is set to compensate the pre-distor-
The proportional, integral and differential gain of the tion of the transmitter. Additionally, the standard set-
loop (CR_P, CR_I, CR_F) can be set via I2C; but the tings can be changed by means of four coefficients to
default values are optimized and should remain optimize the complete signal path (EQU_0, EQU_1,
unchanged. To optimize the PLL performance at sig- EQU_2, EQU_3).
nals from transmitters with high modulator imbalance it
can be switched off during low carrier periods
(CR_AMP_TH). The threshold up to which overmodu- 2.8. Peaking
lation is accepted can be set, too (CR_OVM_TH). For
more details, please refer to the register definition. To shape the frequency response, a peaking filter is
implemented. The following figure indicates the possi-
Due to its digital implementation, the carrier recovery is ble frequency responses:
absolutely offset-free, alignment-free, drift-free, and
quartz-accurate.
Video Response [dB]
10
7.5
2.5. Channel Filtering and Audio/Video Splitting
5
2.11.SIF Output
2.12.1.Standard B 2.12.2.Standard G
10 10
0 0
- 10 - 10
- 20 - 20
- 30 - 30
- 40 - 40
- 50 - 50
- 60 - 60
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
10 10
0 0
- 10 - 10
- 20 - 20
- 30 - 30
- 40 - 40
- 50 - 50
- 60 - 60
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
10 10
0 0
- 10 - 10
- 20 - 20
- 30 - 30
- 40 - 40
- 50 - 50
- 60 - 60
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
10 10
0 0
- 10 - 10
- 20 - 20
- 30 - 30
- 40 - 40
- 50 - 50
- 60 - 60
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
2.12.5.Standard FM
10
0
- 10
- 20
- 30
- 40
- 50
- 60
2 4 6 8 10
Frequency [MHz]
CONTROL 00 Read/Write- Write: Software reset of DRX and MSP-Part Table 3–4 on page 2-
short Read: Hardware error status of MSP 16
WR_DRX 10 Write-long write address
Write-Long protocol
S 8Ehex Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P
10h high low high low
Read-Long protocol
S 8Ehex Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S 8Fhex Wait ACK data-byte- ACK data-byte NAK P
11h high low high low
Write-Short to Control
S 8Ehex Wait ACK 00hex ACK S 8Fhex Wait ACK data-byte- ACK data-byte NAK P
high low
3.1.3.1. Symbols
Micronas
Table 3–3: I2C Subaddress Index
h11-1003 SYNC_SLICE_BS[9:0]
h11-1005 VID_GAIN_BS[10:0]
h11-1006 TAGC_I_BS[10:0]
h11-1007 TAGC_KI[2:0] VAGC_KI[2:0]
h10-1007 TAGC_REDUC[1:0] VAGC_REDUC[1:0] h0000
h10-1008 TAGC_HR_BS[10:0] h0096
h11-100A SIF_GAIN_BS[10:0]
h11-100B AFC_DEV[7:0] AFC_LOCK
h11-100C AFC_LOCK_QUAL[10:0]
h11-100D VID_AMP_HEAD_BS[11:0] h0380
h10-1012 TOP_SET_BS[3:0] h0008
h10-1014 CR_I[2:0] CR_D[2:0] CR_P[2:0] h009B
h10-1015 CR_OVM_TH_BS[7:0] h00A0
Volume 2: DRX - Analog TV IF- Demodulator
2-15
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
Minimum value:
B/G,D/K, L/Lí, M/N : h96
I: hAA
VID_AMP_HEAD_BS[1 h11 h100D[11:0] W 896 - Video Amplitude Headroom
1:0] 2048..204 Controls the DC level of the CVBS output signal
7
CR_I[2:0] h10 h1014[8:6] W 2 0..7 Carrier Recovery Control Integral Coefficient
CR_D[2:0] h10 h1014[5:3] W 3 0..7 Carrier Recovery Control Differential Coefficient
CR_P[2:0] h10 h1014[2:0] W 3 0..7 Carrier Recovery Control Proportional Coefficient
The carrier recovery performs like a PLL and includes a PID-
control (Proportional Integral Differential) block. Each part has
a gain coefficient. Together they define the loop characteristics
(resonance frequency, damping factor).
CR_OVM_TH_BS[7:0] h10 h1015[7:0] W 160 0..255 Carrier Recovery Overmodulation Thresholds
Overmodulation causes a phase shift of 180 degrees. The
overmodulation threshold defines the amplitude up to which
such phase shifts are tolerated.
CLIP_REF_BS[8:0] h10 h1016[8:0] W 448 0..511 Reference value for clipping detection
CR_AMP_TH_BS[7:0] h10 h1017[7:0] W 16 0..255 Carrier Recovery Amplitude Threshold
Bad modulators generate a orthogonal signal vector. There-
fore, the phase of the picture carrier at small carrier amplitudes
becomes unreliable. The amplitude threshold defines the car-
rier level below which the PLL does not consider the phase
information.
DPHI_2IF_BS[11:0] h10 h1021[11:0] W 2832 0..4095 Manual 2nd IF setting f =( DPHI_2IF/16384)*40.5 MHz
B hB3B
G hCA
D/K hCA4
I hCA4
L hCA4
Lí hCA4
M/N h97B
FM hFFF
IF_FREQ_BS[9:0] h10 h1022[9:0] W 317 0..1023 Manual IF frequency setting
Sets the frequency of the analog synthesizer if the default IF
frequency does not fit. Calculation formula:
Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-573-2-1AI retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Volume 3:
Multistandard Sound
Processor
Volume 3: Multistandard Sound Processor
Contents
3-4 1. Introduction
3-4 1.1. Chip Architecture
3-5 1.2. MSP Features
3-6 1.3. Application Fields
Contents, continued
1. Introduction
SPEAKER
TAGC
AOUT
AIN
SIF
IFIN+
Audio
IF IF Sound
Processor
IFIN- Frontend Processor Demodulator
(DSP)
PROT
HOUT
HFLB
VERT
CVBS in Comb Color
Filter Decoder Display & EW
YCrCb in Video Panorama Video
Deflection SVM
RGB in Frontend Scaler Backend
Component Processor RGB out
CVBS out Interface RGB in
SENSE
RSW
I2C Master/
Bus Display I2C
Slicer Slave
Arbiter Generator
Timer
CRT
PWM RESETQ
24kB CPU Reset & Test
ADC
Char ROM 8051 Logic TEST
UART
Watchdog
RTC
256kB Memory Clock XTAL1
20kB XRAM
Prog ROM Interface I/O-Ports Generator XTAL2
Fig. 1–1: Block diagram of the VCT 49xyI, VCT 48xyI highlighting the MSP-Parts
digital
sif
MSP
sda I2C
Audio
Inter-
Demodulator
scl face
NICAM Analog I2C
left
D/A SPEAKER_L
Deemphasis
Volume
Speaker
subw
Proces- D/A Subwoofer
Quellenauswahl
Prescaling
sing
right
D/A SPEAKER_R
Analog Input
Monitor-
Select
A/D Channel
left
Volume
A/D D/A
SCART Channel
right
D/A AOUT1_L
Analog Output Select
AIN1L
AIN1R
Volume
AOUT2_L / HP_L
AIN2L
AIN2R AOUT2_R / HP_R
AIN3L
AIN3R
I2C
Table 1–1: Stereo Sound Standards covered by the VCTI Family (details see Appendix A)
TV-System Position of Sound Sound Modulation Color System Broadcast e.g. in:
Carrier /MHz
Micronas
DBX/MNR Channel or Σ
digital SIF Secondary Proc. Highpass Effects
Prescale Matrix Equalize
Stereo or A/B 1
(0Ehex) (08hex) (29hex) (02hex) (04hex) (2Dhex) (05hex) (01hex)
SPEAKERR
Decoded 0.5
(03hex) A
Standards: Stereo or A MB
NICAM 3
Cutoff- MB
− NICAM NICAM
Deemphasis Noise Filter SUBWoofer
Beeper
− A2 J17 Generator
Stereo or B 4 (2Dhex) (00hex) Micronas
− AM Prescale (14hex)
BASS/Subwoofer
− BTSC (10hex) (6xhex) (2C/2Dhex)
− EIA-J
− FM-Radio Carrier a.
2. Functional Description
ADVANCE INFORMATION
Source Select
(0Chex)
RDS-Read Out
STATUS
Read
STATUS-Change Register
Interrupt
A SCART
Volume D
2 SCART
Channel SCART AOUT1L
D Prescale Matrix A
(0Dhex)
(0Ahex) (07hex)
AOUT1R
(subadr15hex)
AIN1L
AIN1
Analog Matrix
AIN2L
AIN2
AIN2R Volume AOUT2L
AIN3L
AIN3
AIN3R
AOUT2R
(13hex) (13hex)
(subadr15hex)
Fig. 2–1: Signal flow block diagram of the MSP section (input and output names correspond to pin names)
3-7
VCT 49xyI, VCT 48xyI
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
2.1. Architecture of the MSP RDS-Data are provided array-wise, each array con-
taining 18 words of 12 bit RDS-data. A new array is
Fig. 2–1 on page 3-7 shows a simplified block diagram indicated in the STATUS-register and optionally by an
of a typical MSP. Other members of the VCT family do interrupt (see MODUS-register). Additionally for each
not have the complete set of features. new RDS-array the RDS_Array_Ct is incremented to
enable the synchronisation of reading RDS-Data.
all analog sound standards Evaluation of the identification or pilot signal and automatic switching to mono, stereo, or bilingual.
Preparing four demodulator source channels according to Table 2–2.
B/G-NICAM, L-NICAM, I-NICAM, Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four
D/K-NICAM demodulator source channels according to Table 2–2.
In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches
back to NICAM if possible. A hysteresis prevents periodical switching.
M/N-BTSC-SAP In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP
switches automatically to SAP (see Table 2–2).
Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select
B/G-NICAM 08, 032) NICAM not available or analog Mono analog Mono analog Mono analog Mono
L-NICAM 09 error rate too high
I-NICAM 0Ahex
D/K-NICAM 0Bhex, 042), 052) MONO analog Mono NICAM Mono NICAM Mono NICAM Mono
0Chex
STEREO analog Mono NICAM Stereo NICAM Stereo NICAM Stereo
2.3. Audio Baseband Processing (DSP) inputs. The decay time is programmable by means of
the AVC register.
2.3.1. Preprocessing of Demodulator Signals
For input signals ranging from −24 dBr to 0 dBr, the
The NICAM signals must be processed by a deempha- AVC maintains a fixed output level of −18 dBr. Fig. 2–2
sis filter and adjusted in level. The analog demodu- shows the AVC output level versus its input level. For
lated signals must be processed by a deemphasis fil- prescale and volume registers set to 0 dB, a level of
ter, adjusted in level, and dematrixed. The level 0 dBr corresponds to full scale input/output. This is
adjustment has to be done by means of the FM/AM
– Input/output 0 dBr = 2.0 Vrms
and NICAM prescale registers.
output level
2.3.2. Preprocessing for Analog Inputs [dBr]
After selection of one analog input for A/D-conversion
this input signal can be adjusted in level by means of −18
the SCART prescale register.
−24
Amplitude (db)
The Micronas BASS system extends the frequency
range of loudspeakers or headphones.
ing a "license key" into the MSP section of the VCT. intelligibility are the second to fourth formants of
For information on how to obtain this license key from speech. These formants are detected and
Micronas, please contact your Micronas sales repre- increased, while other parts of the signal are
sentative. decreased.
According to speech theory, there are two main effects Fig. 2–6: Possible Virtual Surround Sound systems
that affect the intelligibility of speech. Micronas VOICE
combines both effects to achieve a maximum
enhancement of intelligibility. 2.3.5. Headphone Outputs
– Forward and backward masking: For intelligibility,
consonants are more important than vowels, but the The analog output pair AOUT2 can alternatively be
amplitude of consonants is much lower than that of used as headphone output, providing volume and
vowels. The consonants are masked by the vowels. matrix control.
Therefore the amplitude of consonants is increased
and the amplitude of vowels decreased.
– Phonemes and formants: Most important for the
3. Control Interface 3.1.1. Reset of MSP and DRX via I2C (Soft-Reset)
3.1. I2C Bus Register and Interface Description Besides the possibility of hardware reset, the MSP can
also be reset by means of the RESET bit in the CON-
The MSP is controlled by the VCT controller section TROL register (see Section 3.1.6. on page 3-17) by
via the I2C bus slave interface. the controller via I2C bus. This register is shared with
the DRX-section, using the DRX-device addresses for
The MSP is selected by transmitting the MSP device read and write. Note, that the Soft-Reset affects
address. A device address pair is defined as a write always the MSP and the DRX.
address and a read address (see Table 3–1).
Two register types require different protocolls to 3.1.2. I2C Bus Response Time
access them. There are registers, which are
addressed merely by the subaddress (“short”), others Due to the architecture of the MSP, the IC cannot react
require an additional address (below the subaddress, immediately to an I2C request. The typical response
“long”). Each of the following protocolls is framed by a time is about 0.3 ms. If the MSP cannot accept another
start and stop condition. byte of data (e.g. while servicing an internal interrupt),
it holds the clock line I2C_CL low to force the transmit-
Write-Long is done by sending the write device ter into a wait state. The I2C Bus Master must read
address, followed by the subaddress byte, two back the clock line to detect when the MSP is ready to
address bytes, and two data bytes. receive the next I2C transmission. The positions within
a transmission where this may happen are indicated
Write-Short is done by sending the write device by ’Wait’ in Section 3.1.5. The maximum wait period of
address, followed by the subaddress byte and two the MSP during normal operation mode is less than
data bytes. 1 ms.
Unused parts of the 16-bit write registers must be zero. Indication of reset:
Refer to Section 3.1.5. for the detailed I2C bus protocol Any reset, even caused by an unstable reset line etc.,
and to Section 3.1.7. on page 3-18 for generalized I2C is indicated in bit[15] of CONTROL (see Table 3–4 on
telegrams. See a list of available subaddresses in page 3-17).
Table 3–2 on page 3-17. Details concerning start and
stop bits are shown in Fig. 3–1.
I2C_DA
1
Table 3–1: I2C Bus Device Address 0
S P
I2C_CL
Mode Write Read
MSP-device address 8Chex 8Dhex Fig. 3–1: I2C bus protocol (MSB first; data must be
stable while clock is high)
3.1.4. FBL-Status
S 8Chex Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P
10h or 12h high low high low
S 8Chex Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S 8Dhex Wait ACK data-byte- ACK data-byte NAK P
11h or 13h high low high low
S 8Chex Wait ACK 80hex ACK S 8Dhex Wait ACK data-byte NAK P
Write-Short to Control
S 8Ehex Wait ACK 00hex ACK S 8Fhex Wait ACK data-byte- ACK data-byte NAK P
high low
CONTROL 00 Read/Write- Write: Software reset of DRX and MSP-Part (see Section 3.1.6. on
Note: DRX- short Read: Hardware error status of MSP page 3-17)
Device-Addr.
WR_DEM 10 Write-long write address for demodulator registers (see Table 3–6 on
page -23)
RD_DEM 11 Write-long read address for demodulator registers
CONTROL 00hex RESET status of DRX and MSP- DRX: I2C Time Out MSP: I2C Time Out not of
parts after last reading of CONTROL: interest
0 : no error occured 0 : no error occured
0 : no reset occured 1 : response time 1 : response time
1 : reset occured >1.6 ms occured >1.6 ms occured
Reading of CONTROL will reset the bits[15,14,13] of CONTROL. After Power-on, bit[15] of CONTROL will be
set; it must be read once to be reset.
3.1.7.1. Symbols
3.1.7.4. Examples
3.3. I2C Register Block Index Name Addr Page Name Addr Page
DCO_A_LO[11:0] h10-00A3 35 Src_Sel_QP[7:0] h12-000C 30
DCO_B_HI[11:0] h10-009B 35 Src_Sel_SC_Out[7:0] h12-000A 30
Name Page
DCO_B_LO[11:0] h10-0093 35 Stat_Bad_NICAM h11-0200 24
Additional DSP Registers 35
Dynam_Fast_Blank h80 36 Stat_Bil_or_SAP h11-0200 24
Additional NICAM-Information 35
Eff_HP_G_Main[3:0] h12-0005 29 Stat_Carr_A h11-0200 24
Analog I/O Selection 34
Eff_Mode_Main[1:0] h12-0005 29 Stat_Carr_B h11-0200 24
Analog Power-Up Configuration 34
Eff_Strgth_Main[7:0] h12-0005 29 Stat_Indep_Mono h11-0200 24
AOUT2: Volume and Matrix 31
EQ_Band1_Main[7:0] h12-0021 31 Stat_New_RDS_D h11-0200 24
Automatic Sound Select-Configu- 25
ration EQ_Band2_Main[7:0] h12-0022 31 Stat_NICAM h11-0200 24
Demodulator 24 EQ_Band3_Main[7:0] h12-0023 31 Stat_Stereo h11-0200 24
Demodulator: Manual Tuning 35 EQ_Band4_Main[7:0] h12-0024 31 Static_Fast_Blank h80 36
FBL 36 EQ_Band5_Main[7:0] h12-0025 31 STD_Result[15:0] h11-007E 24
Hard- and Software Revision 35 Error_Rate[11:0] h11-0057 35 STD_Sel[11:0] h10-0020 24
MODUS 23 FM_AM_Presc[7:0] h12-000E 26 SUBW_CFRQ[7:0] h12-002D 32
Quasi Peak Channel 30 FM_DC_LEV_A[15:0] h13-001B 36 SUBW_CHAR[7:4] h12-002D 33
RDS-Data 26 FM_DC_LEV_B[15:0] h13-001C 36 SUBW_Enable h14 34
SCART-Processing Channel 30 FM_Deemph[7:0] h12-000F 35 SUBW_HP[3:0] h12-002D 33
Source Prescaling 26 FM_Ident[7:0] h13-0018 36 SUBW_LEV[7:0] h12-002C 32
Speaker Channel: Basic Features 27 FM_Matrix[7:0] h12-006F 36 Tone_Mode_Main[7:0] h12-0020 31
Speaker Channel: Equalizer 31 Frequ_Beeper[7:0] h12-0014 29 Treble_Main[7:0] h12-0003 28
Speaker Channel: Micronas BASS 33 Loud_Main[7:0] h12-0004 28 Vol_AOUT2[7:0] h12-0013 31
Speaker Channel: Micronas 33 Loud_Main_Mode[2:0] h12-0004 28 Vol_Beeper[7:0] h12-0014 29
VOICE Matr_Sel_Main[7:0] h12-0008 29 Vol_Clip_Mode[1:0] h12-0000 27
Speaker Channel: Subwoofer 32 Matr_Sel_QP[7:0] h12-000C 30 Vol_Main[7:0] h12-0000 26
Speaker Channel: Virtual Sur- 31 Matr_Sel_SC_Out[7:0] h12-000A 30 Vol_Main_Resol[2:0] h12-0000 27
round
Matrix_AOUT2[1:0] h12-0013 31 Vol_SC_Proc_Ch[7:0] h12-0007 30
Speaker Channel: Volume 26
MB_AMP_LIM[7:0] h12-0069 33 Vol_SC_Resol[2:0] h12-0007 30
STATUS-Read-Out 24
MB_EFF_Str[7:0] h12-0068 33 VSS_3D_Str[7:0] h12-004A 32
MB_HARM_CT[7:0] h12-006A 33 VSS_Matr_Mode[7:0] h12-004B 32
3.4. I2C Bit Slices Index MB_HP_CFRQ[7:0] h12-006C 33 VSS_Noise_Sel[7:0] h12-004D 32
MB_LP_CFRQ[7:0] h12-006B 33 VSS_Noise_SW[7:0] h12-004D 32
Mod_4_5MHz[1:0] h10-0030 23 VSS_Spat_Str[7:0] h12-0049 32
Name Addr Page Mod_6_5MHz h10-0030 23 VSS_SW_Main[0] h12-0048 31
A2_Thld[11:0] h10-0022 25 Mod_ASS h10-0030 23 VSS_Virt_Mode[7:0] h12-004B 32
ADD_BIT[10:3] h11-0038 35 Mod_BTSC h10-0030 23
ADD_BIT[2:0] h11-0023 35 Mod_CM_A h10-0030 23
Ana_Amp_On_Off h14 34 Mod_CM_B h10-0030 23
Ana_DSP_In_Sel[2:0] h15 34 Mod_Dis_Std_Chg h10-0030 23
Ana_Ref_On_Off h14 34 Mod_FMRadio h10-0030 23
AOUT1_SEL[2:0] h15 34 Mod_HDEV_A h10-0030 23
AOUT2_Enable h14 34 Mod_StatInterr h10-0030 23
AOUT2_SEL[2:0] h15 35 MSP_FW_Rev[15:0] h11-0221 35
AVC_DEC_Main[3:0] h12-0029 30 MSP_HW_Rev[15:0] h11-0220 35
AVC_SW_Main[3:0] h12-0029 29 MVOICE_Str[7:0] h12-0067 33
Bal_Main[7:0] h12-0001 27 NICAM_Presc[7:0] h12-0010 26
Bal_Mode_Main[1:0] h12-0001 27 NICAM_Thld[11:0] h10-0021 25
Bass_Main[7:0] h12-0002 28 Q_Peak_Left[15:0] h13-0019 30
BTSC_Thld[11:0] h10-0023 25 Q_Peak_Right[15:0] h13-001A 30
CIB1 h11-003E 35 RDS_Array_Ct[11:0] h11-020F 26
CIB2 h11-003E 35 RDS_Data[11:0] h11-0210 26
CM_A_Thld[11:0] h10-0024 25 SCART_Presc[7:0] h12-000D 26
CM_B_Thld[11:0] h10-0025 25 SIF_Out_Enable h14 34
DCO_A_HI[11:0] h10-00AB 35 Src_Sel_Main[7:0] h12-0008 29
Micronas
Table 3–5: I2C Subaddress Index
h10-0030 Mod_BT Mod_4_5MHz[1:0] Mod_6_ Mod_F Mod_C Mod_C Mod_H Mod_Di Mod_St Mod_AS h0000
SC 5MHz MRadio M_B M_A DEV_A s_Std_C atInterr S
hg
h10-0020 STD_Sel[11:0] h0000
h11-007E STD_Result[15:0]
h11-0200 Stat_Ba Stat_Bil Stat_Ind Stat_Ste Stat_NI Stat_Ca Stat_Ca Stat_Ne
d_NICA _or_SA ep_Mon reo CAM rr_B rr_A w_RDS
M P o _D
h10-0021 NICAM_Thld[11:0] h02BC
h10-0022 A2_Thld[11:0] h0190
h10-0023 BTSC_Thld[11:0] h000C
h10-0024 CM_A_Thld[11:0] h002A
h10-0025 CM_B_Thld[11:0] h002A
h11-020F RDS_Array_Ct[11:0]
Volume 3: Multistandard Sound Processor
h11-0210 RDS_Data[11:0]
h12-000E FM_AM_Presc[7:0] h0000
3-20
Table 3–5: I2C Subaddress Index, continued
3-21
Sub Data Bits Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h12-0013 Vol_AOUT2[7:0] Matrix_AOUT2[1:0] h0000
h12-0014 Vol_Beeper[7:0] Frequ_Beeper[7:0] h0000
h12-0020 Tone_Mode_Main[7:0] h0000
h12-0021 EQ_Band1_Main[7:0] h0000
h12-0022 EQ_Band2_Main[7:0] h0000
h12-0023 EQ_Band3_Main[7:0] h0000
h12-0024 EQ_Band4_Main[7:0] h0000
h12-0025 EQ_Band5_Main[7:0] h0000
h12-0029 AVC_SW_Main[3:0] AVC_DEC_Main[3:0] h0000
VCT 49xyI, VCT 48xyI
Micronas
ADVANCE INFORMATION
Table 3–5: I2C Subaddress Index, continued
Micronas
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h10-00AB DCO_A_HI[11:0] h0000
h10-00A3 DCO_A_LO[11:0] h0000
h11-0023 ADD_BIT[2:0]
h11-0038 ADD_BIT[10:3]
h11-003E CIB2
ADVANCE INFORMATION
h11-003E CIB1
h11-0057 Error_Rate[11:0]
h12-000F FM_Deemph[7:0] h0000
h12-006F FM_Matrix[7:0] h0000
h13-0018 FM_Ident[7:0]
h13-001B FM_DC_LEV_A[15:0]
h13-001C FM_DC_LEV_B[15:0]
h12-0017 h0000
h80 Static_F Dynam_
ast_Blan Fast_Bl
k ank
h12-4444 h0000
Volume 3: Multistandard Sound Processor
3-22
ADVANCE INFORMATION VCT 49xyI, VCT 48xyI
Volume 3: Multistandard Sound Processor
Note:
For compatibility reasons, every undefined bit in a writeable register should be set to ’0’. Undefined bits in a readable
register should be treated as “don’t care”! Addresses not given in this table must not be accessed.
Although not mentioned explicitly, all registers addressed by the write-subaddress h12 are readable by means of the
read-subaddress h13.
Examples:
00h off
10h 0 dB gain
2Dh +9 dB gain (recommendation)
7Fh +18 dB gain (maximum gain)
SCART_Presc[7:0] h12 h000D[15:8] RW 0 0..h7F Prescaling gain for the analog SCART source:
Examples:
00h off
19h 0 dB gain (2 VRMS input leads to digital full scale)
7Fh +14 dB gain (400 mVRMS input leads to digital full scale)
2. Logarithmic Mode
7Fh Left -127 dB, Right 0 dB
7Eh Left -126 dB, Right 0 dB
...
01h Left -1 dB, Right 0 dB
00h Left 0 dB, Right 0 dB
FFh Left 0 dB, Right -1 dB
...
81h Left 0 dB, Right -127 dB
80h Left 0 dB, Right -128 dB
normal range
60h +12 dB
58h +11 dB
...
08h +1 dB
00h 0 dB
F8h -1 dB
...
A8h -11 dB
A0h -12 dB
2. If AOUT2 is selected:
0 AIN1 (RESET position)
1 AIN2
2 must not be used
7 mute DSP input
AOUT1_SEL[2:0] h15[5:3] RW 0 0, 1, 2, 3, Source Select for AOUT1-Output:
7 1. If AIN3 is selected and for PQFP Packages:
0 AIN2 (RESET position)
1 SCART DA
2 AIN1
3 AIN3
7 mute AOUT1
2. If AOUT2 is selected:
0 AIN2 (RESET position)
1 SCART DA
2 AIN1
3 must not be used
7 mute AOUT1
3. If AOUT2 is selected:
0 SCART DA (RESET position)
1 AIN1
2 AIN2
3 not defined; do not use
7 mute AOUT2
Hard- and Software Revision
MSP_HW_Rev[15:0] h11 h0220[15:0] R 0..hFF MSP Hardware_Revision Code
MSP_FW_Rev[15:0] h11 h0221[15:0] R 0..hFF MSP Firmware_Revision Code
Demodulator: Manual Tuning
DCO_B_HI[11:0] h10 h009B[11:0] W 0 0..hFFF Frequency Adjustment for Secondary Channel: High Part
DCO_B_LO[11:0] h10 h0093[11:0] W 0 0..hFFF Frequency Adjustment for Secondary Channel: Low Part
DCO_A_HI[11:0] h10 h00AB[11:0] W 0 0..hFFF Frequency Adjustment for Primary Channel: High Part
DCO_A_LO[11:0] h10 h00A3[11:0] W 0 0..hFFF Frequency Adjustment for Primary Channel: Low Part
Additional NICAM-Information
ADD_BIT[2:0] h11 h0023[7:5] R 0..7 NICAM: Additional Data Bits[2:0]
ADD_BIT[10:3] h11 h0038[7:0] R 0..hFF NICAM: Additional Data Bits[10:3]
CIB2 h11 h003E[0] R 0,1 NICAM: CIB2 Bit
CIB1 h11 h003E[1] R 0,1 NICAM: CIB1 Bit
Error_Rate[11:0] h11 h0057[11:0] R 0..h7FF NICAM: Error Rate:
Average error rate of the NICAM reception in a time interval of
182 ms, which should be close to 0. The initial and maximum
value of ERROR_RATE is 2047. Since the value is achieved
by filtering, a certain transition time (approx. 0.5 sec) is
unavoidable. Acceptable audio may have error rates up to a
value of 700 int. Individual evaluation of this value by the con-
troller and an appropriate threshold may define the fallback
mode from NICAM to FM/AM-mono in case of poor NICAM
reception.
This value can be used for frequency fine tuning. A too low
demodulation frequency (DCO) results in a positive DC-level
and vice versa. For further processing, the DC content of the
demodulated FM signals is suppressed. The time constant t,
defining the transition time of the DC Level Register, is approx-
imately 28 ms.
FM_DC_LEV_B[15: h13 h001C[15:0] R h8000..h7 DC level of the incoming FM signal of the Secondary
0] FFF Sound Channel
This value can be used for frequency fine tuning. A too low
demodulation frequency (DCO) results in a positive DC-level
and vice versa. For further processing, the DC content of the
demodulated FM signals is suppressed. The time constant t,
defining the transition time of the DC Level Register, is approx-
imately 28 ms.
FBL
Static_Fast_Blank h80[7] R 0,1 Static Fastblank Status
0 no fastblank active
1 fastblank active
Dynam_Fast_Blank h80[6] R 0,1 Dynamic Fastblank Status
0 no fastblank edge detected
1 fastblank edge detected
3.7. Application and Programming Tips least 30 ms longer than the 3.3 V and the 5 V power
supply to be traced.
This section describes the preferred method for initial-
izing and switch off the MSP. The initialization is
grouped into four sections: 3.7.2. Define Analog Input to DSP and AOUT1/2
– 3.7.1. Analog Power Configuration Setup 1. Select analog input for the SCART processing path
by means of the register Ana_DSP_In_Sel.
– 3.7.2. Define Analog Input to DSP and AOUT1/2
2. Set preferred prescale for SCART_IN processing
– 3.7.3. Demodulator Setup
path (SCART_Presc)
– 3.7.4. Loudspeaker and SCART Channel Setup
3. Select the sources for AOUT1 and AOUT2 using
AOUT1/2_SEL.
See Fig. 2–1 on page 3-7 for a complete signal flow.
3.7.5.1. TV-Standard B/G (A2 or NICAM) 3.7.5.5. Automatic Standard Detection for D/K,
<8E 00 80 00> // Soft reset (optional) applying STATUS-Change Interrupt
<8C 14 40 01> // Analog Power-up configuration <8E 00 80 00> // Softreset (optional)
<8C 10 00 30 00 03> // Mod_StatInterr=1 <8C 14 40 01> // Analog Power-up configuration
Mod_ASS=1 <8C 10 00 30 07 03> // Mod_4_5MHz=3
<8C 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St Mod_6_5MHz=1
Mod_StatInterr=1
<8C 12 00 0E 24 00> // FM/AM-Prescale = 24hex, Mod_ASS=1
<8C 12 00 10 2D 00> // NICAM-Prescale = 2Dhex <8C 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St
<8C 10 00 20 00 08> // Standard Selection: Preferred Standard <8C 12 00 0E 24 00> // FM/AM-Prescale = 24hex,
<8C 12 00 00 73 00> // Loudspeaker Volume 0 dB <8C 12 00 10 2D 00> // NICAM-Prescale = 2Dhex
<8C 10 00 20 00 01> // Standard Select: Autom. Standard Det.
3.7.5.2. TV-Standard M/N (BTSC,EIA-J, A2-Korea) <8C 11 00 7E <8D dd dd>// Read STANDARD RESULT
// Wait until STANDARD RESULT contains a value ≤ 07FF
<8E 00 80 00> // Soft reset (optional)
// IF STANDARD RESULT contains 0000
<8C 14 40 01> // Analog Power-up configuration
// error handling: set former standard or
<8C 10 00 30 00 03> // Mod_BTSC=0
derive standard from video information
Mod_StatInterr=1
Mod_ASS=1 // ELSE
<8C 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St <8C 12 00 00 73 00> // Loudspeaker Volume 0 dB
<8C 12 00 0E 24 00> // FM/AM-Prescale = 24hex,
<8C 10 00 20 00 20> // Standard Select: Preferred standard Interrupt Handler:
<8C 12 00 00 73 00> // Loudspeaker Volume 0 dB <8C 11 02 00 <8D dd dd> // Read STATUS
// Adjust TV-display with given STATUS information
// Return from Interrupt
3.7.5.3. BTSC-SAP with SAP at Loudspeakers
<8E 00 80 00> // Softreset (optional)
<8C 14 40 01> // Analog Power-up configuration 3.8. Manual Demodulator Programming Facilities
<8C 10 00 30 80 03> // Mod_BTSC=1 (BTSC-SAP)
Mod_StatInterr=1 3.8.1. Source Channel Assigment if Automatic
Mod_ASS=1 Sound Select is not applied
<8C 12 00 08 04 20> // Source Sel. = (St or B) & Ch. Matr. = St
<8C 12 00 0E 24 00> // FM/AM-Prescale = 24hex, Fig. 3–2 shows the source channel assignment of
<8C 10 00 20 00 20> // Standard Select: BTSC-SAP demodulated signals in case of manual mode (ASS =
<8C 12 00 00 73 00> // Loudspeaker Volume 0 dB
off). Specific information can be found in Table 3–7
“Demodulator Source Channels in Manual Mode”.
secondary
<8C 10 00 30 00 03> // Mod_FMRadio=0 or 1 (US/EU) channel
Prescale
Output-Ch.
Mod_StatInterr=1 matrices
Mod_ASS=1 NICAM
must be set
NICAM A
according to
<8C 12 00 08 03 20> // Source Sel. = (St or A) & Ch. Matr. = St NICAM the standard.
1
(Stereo or A/B)
<8C 12 00 0E 24 00> // FM/AM-Prescale = 24hex, NICAM B Prescale
The DCO registers are useful to adapt the MSP to a with: int = integer function
non-documented sound standard. In that case it is rec- f = IF frequency in MHz
ommended to start by means of the STANDARD fS = sampling frequency (20.25 MHz)
SELECT register with the “nearest” implemented stan-
dard and then to adapt the frequency tuning by means Conversion of INCR into hex-format and dividing up
of the DCO registers. To avoid any overwriting of this into 12-bit high and low parts lead to the required reg-
setting the Automatic Standard Change feature of the ister values (DCO_B_HI and_LO for the secondary
Automatic Sound Select feature has to be disabled. MSP Channel, DCO_A_HI and LO for the primary
The formula for the calculation of the registers for any MSP Channel.
chosen IF Frequency is as follows:
Table 3–7: Manual Sound Select Mode for Terrestric Sound Standards
B/G-NICAM 08 NICAM not available Sound A Mono1) analog Mono analog Mono
L-NICAM 09 or NICAM error rate
I-NICAM 0A too high
D/K-NICAM 0B
0C MONO Sound A Mono1) analog Mono NICAM Mono
Carrier frequency of 6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz
digital sound
Carrier frequency of 6.0 MHz 5.5 MHz 6.5 MHz AM mono 6.5 MHz
analog sound component FM mono FM mono FM mono
terrestrial cable
Characteristics Values
Number of channels 2
Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks
Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
4.2. A2 Systems
Table 4–3: Key parameters for A2 Systems of Standards B/G, D/K, and M
Preemphasis 50 µs 75 µs 50 µs 75 µs
Frequency deviation (nom/max) ±27/±50 kHz ±17/±25 kHz ±27/±50 kHz ±15/±25 kHz
Transmission Modes
Aural BTSC-MPX-Components
Carrier
(L+R) Pilot (L−R) SAP Prof. Ch.
Max. deviation to Aural Carrier 73 kHz 25 kHz1) 5 kHz 50 kHz1) 15 kHz 3 kHz
(total)
Table 4–5: Key parameters for Japanese FM-Stereo Sound System EIA-J
Aural EIA-J-MPX-Components
Carrier
FM (L+R) (L−R) Identification
Preemphasis 75 µs 75 µs none
Transmitter-sided delay 20 µs 0 µs 0 µs
Table 4–6: Key parameters for FM-Stereo Radio Systems and RDS
Aural FM-Radio-MPX-Components
Carrier
(L+R) Pilot (L−R) RDS/ARI
Preemphasis:
− USA 75 µs 75 µs
− Europe 50 µs 50 µs
Specification
4.6. Differences between the MSP part of VCTI and MSP 34/44xyG Stand-Alone Products
Table 4–8: Differences between the MSP part of VCTI and MSP 34/44xyG stand-alone products
Automatic Standard Change - for B/G and D/K-Standards - for B/G, D/K, and NTSC-Standards
as part of Automatic Sound - always active if ASS = on - to be disabled by MODU[2]
Select (ASS) in case of Mono
A2_Threshold
- force Mono Identification 07F0hex 07FFhex
Demodu-
lator NICAM-Threshold Register “AUTO_FM” Register “NICAM_Thld” Same I2C-Address
Select of - Standard Select = 40hex (US) - MODUS[11] = 0 : US (75 µs) VCTI: US/EU-
FM-Radio US/EU - set EU-version by changing = 1 : EU (50 µs) Version can be
Deemphasis manually - Standard Select = 40hex predefined for
Automatic Standard
Detection
FM-Deviation-Modes:
- max. Deviation normal: ±180 kHz. normal: > ±200 kHz VCTI: max.
HDEV2: ±350 kHz HDEV: > ±400 kHz Deviation also
HDEV3: > ±500 kHz depends on Mode of
- Activation of HDEV-Mode: by Standard Select Register by using MODUS[8] for each Code of DRX-Part
Standard Select Register
- Level-difference between
normal and HDEV(2) mode −6 dB 0 dB
Baseband NICAM-Prescaling 00hex...7Fhex: off ...+12 dB 00hex.....7Fhex: off .....+ 18 dB VCTI: 6 dB more
Process. gain possible for
NICAM
Micronas GmbH All information and data contained in this data sheet are without any
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Micronas GmbH.
Volume 4:
Video Processor
Edition 12.12.2003
6251-573-4-1AI
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
Contents
4-4 1. Introduction
4-4 1.1. Chip Architecture
4-5 1.2. Video Features
Contents, continued
1. Introduction
SPEAKER
TAGC
AOUT
AIN
SIF
VERT
CVBS in Comb Color
Filter Decoder Display & EW
YCrCb in Video Panorama Video
Deflection SVM
RGB in Frontend Scaler Backend
Component Processor RGB out
CVBS out Interface RGB in
SENSE
RSW
I2C Master/
Bus Display I2C
Slicer Slave
Arbiter Generator
Timer
CRT
PWM RESETQ
24kB CPU Reset & Test
ADC
Char ROM 8051 Logic TEST
UART
Watchdog
RTC
256kB Memory Clock XTAL1
20kB XRAM
Prog ROM Interface I/O-Ports Generator XTAL2
2.1.1. Analog Source Select While all inputs can be used to process Y/C signals,
only VIN3&4, VIN5&6 or VIN7&8 support Y/C to CVBS
The VSP provides 11 analog video inputs. The DRX conversion.
delivers an additional CVBS signal. Internally, three
additional CVBS signals are generated. The clamped input signals are lowpass-filtered, ampli-
fied and converted to digital signals.
The analog source select connects these 15 analog
input sources to 6 ADCs and to 3 analog outputs (see Video recording in standby (copy-mode) is supported
Fig. 2–1). It also delivers the clamping signals to the by STANDBYADC1-6 switching off the ADCs and
selected inputs. keeping the source-selector and the output buffers
operational. The output buffers can be disabled inde-
pendently by STANDBYBUF1-3.
CVBS
VIN1 C 1 1
CVBS
VIN2 C 2 2
CVBS / Y
VIN3 C 3 3
CVBS / C
VIN4 C 4 4
Y+C
+ 12
CVBS / Y
VIN5 C 5 5
CVBS / C Source Source Source Source Source Source Source Source Source
VIN6 C 6Select Select Select Select Select 6Select Select Select Select
1/15 1/15 1/15 1/15 1/15 1/11 1/11 1/11 1/11
Y+C
+ 13
Y+C
+ 14
SCART / DVD
CVBS / Y
VIN7 C 7 7
R / C / Cr
VIN8 C 8 8
G/Y
VIN9 C 9 9
B / Cb
VIN10 C 10 10
FB
VIN11 C 11 11
2.1.2. Digital Source Select from color decoder and slicer with the corresponding
ADC (see Fig. 2–3). The inputs for color decoder and
In normal operation, color decoder and teletext slicer teletext slicer (CVBS2LF, DCVBSVBI) are connected
share the same CVBS signal. Nevertheless, as two to the A/D converter via switching matrices and a
ADCs are available, it is possible to use different comb filter. Depending on COMBUSECD and COM-
sources for color decoder and slicer. Therefore, an BUSEVBI, ADC1, ADC2 or the comb filter are
additional switching matrix is implemented to select selected as signal source. Color decoder and sync sig-
the appropriate source for each module. A second nals used in the comb-filter are selected in the comb
switching matrix connects clamping and agc signals filter interface (see Fig. 2–2).
Table 2–1: Color Decoder Input Select Table 2–2: Teletext Slicer Input Select
1 adcr 1 cvbs2l
1 adcr 3 adcgf
2 X ycomb ccomb
3 0 adcgf adcgf
1 adcr
REMDEL1 DIS4HCOMB
0 NTSCM
1
9
τ1 τ2
CVBS1LF
ADC1 CVBS2CD 0
0
binary 2th compl. CVBS2LF 9
1 1 Y
9 CVBS2LF Color
ADC2 τ1 τ2 YCSEL
2
DCVBS2CD Decoder 9
1 UV
DCVBS2
DCVBS1
0 NTSCM
COMBUSECD
REMDEL2 3
YCBYR
0
1 YDC
2 1H NTSC or 0
INCOMB 4H adaptive
CDC
combfilter 1 Teletext
DCVBSVBI
Slicer
2
DIS4HCOMB
ADC3 ADC COMBUSEVBI
3
ADC4 RGB
ADC5 Frontend ADCR
I2C Register
ADC6
1 1 clamp_measure3-6
CLAMP_FBL3-6 I2C Register
1 clamp_on3-6
1
CLAMP_SYNC3-6 ADC 3-6 1 hpll_stable3-6
1 6 agcadj3-6
CLAMP_CHROMA3-6 AGCADJ3-6
CLPSTGY
CLMPSIG1 1 clmp1
CLMPST1/2
1 clamp_measure1 1 clmp2
1 1 CLMPD1/2
clamp_on1 clmps1 Color
1
CLAMP_SYNC1 ADC 1 1 hpll_stable1 1 clmps2 Decoder CLMPST1/2S
1 6 agcadj1 1 stab
CLAMP_CHROMA1
6 CLMPD1/2S
agcadj1
6
AGCADJ2 AGCADJ1
1 clamp_measure2 1 clmpvbi
1 clamp_on2 1 clmpsvbi
1 Teletext
CLAMP_SYNC2 ADC 2 1 hpll_stable2 1 stabvbi
Slicer
1 6 agcadj2 6
CLAMP_CHROMA2 AGCADJVBI
CLMPSIG2
2.1.4. Clamping
Signal Description
video
hsync
Sync
clamp Separation
agc H-PLL
4H Comb
adcg yuv 4:2:2
Filter
cvbs/c 1H
Color
adc2 Deskew Chroma
Decoder
Delay
The CVBS frontend consists mainly of four parts, the 2.2.1. Comb Filter
4H comb filter, the notch filter, the color decoder and a
synchronization circuit. The 4H comb filter separates The 4H adaptive comb filter is used for high quality
luminance and chrominance information from the luminance/chrominance separation for PAL or NTSC
CVBS input signal, while the notch filter removes the composite video signals. The comb filter improves the
color carrier in no comb mode. The color decoder luminance resolution (bandwidth) and reduces interfer-
decodes the input CVBS signal to Cr and Cb. The sync ences like cross-luminance and cross-color. The adap-
processing circuit separates the H/V sync out of the tive algorithm eliminates most of the mentioned errors
input signal. Additionally a skew correction filter and a without introducing new artifacts or noise.
baseband delay line are used. In PAL and SECAM
mode the baseband delay line is used for Cr and Cb. The comb-filter input can be selected by INCOMB.
In NTSC mode it acts as comb filter for chroma. First or second CVBS ADC or green ADC can be
used. The filter uses four line delays to process the
A switching matrix in front of the color decoder inter- information of three video lines. To have a fixed phase
faces to the 4H comb filter or to the ADC modules. The relationship of the color subcarrier in the three chan-
output signals of the color decoder are fed to the Soft- nels, the digital data is fractionally locked to the color
mix. subcarrier. This allows the processing of all color stan-
dards and substandards using a single crystal fre-
quency.
The digital multistandard chroma decoder decodes The demodulation is followed by a lowpass filter for the
NTSC and PAL signals with a subcarrier frequency of color difference signals for PAL/NTSC. SECAM
3.58 MHz and 4.43 MHz (PAL B/G/H/I/M/N/60, requires a modified lowpass function with bell filter
NTSC M/44) as well as SECAM signals with automatic characteristic. For SECAM mode, the de-emphasis fil-
standard detection. Alternatively, a standard can be ter can be adjusted by DEEMPFIR and DEEMPIIR. A
forced. The demodulation is done with a regenerated wide band chroma filter can be selected. This filter is
color carrier. intended for high bandwidth chroma signals, e.g.,
S-VHS signal or when comb filter is enabled. The
For use of non-standard crystals or factory adjustment, chroma bandwidth can be adjusted by CHRF (see
the frequency of the free-running regenerated subcar- Fig. 2–7).
rier can be adjusted between ±270 ppm via SCADJ.
For this purpose the crystal deviation (SCDEV) can be
read out via I²C after chroma PLL locking (indicated by Chroma filter
SCOUTEN) and can be stored in µC ROM for SCADJ. 5
Damping (dB)
(YCDEL). 15
CHRF=’001000’
20
CHRF=’001100’
A delay-line is implemented for PAL and SECAM sig- 25
2.2.3. IF-Compensation
With off-air or mistuned reception, any attenuation at Fig. 2–7: Chroma filter characteristics
higher frequencies or asymmetry around the color sub-
carrier is compensated. Five different settings
(IFCOMP) of the IF compensation are possible: 2.2.5. Automatic Standard Recognition (ASR)
– Flat (no compensation)
The ASR supports the following standards:
– 6 dB/octave
– 50 Hz: PAL B/N, SECAM
– 12 dB/octave
– 60 Hz: NTSC M/44, PAL M/60
– 4.4 MHz prefiltering (with or without prefiltering)
The automatic detection can be disabled and single
standards can be forced.
IF Prefilter
10
3.58 4.433
This standard detection process can be set to slow or
5 fast behavior (LOCKSP). In slow behavior, 25 fields
0 IFCOMP=’100’
are used to detect the standard, whereas 15 fields are
IFCOMP=’000’ used in fast behavior. If unsuccessful within this time
5
period the system tries to detect another standard.
Damping (dB)
IFCOMP=’011’
10
For SECAM detection, a choice between different rec-
15
IFCOMP=’001’ ognition levels is possible (SCMIDL, SCMREL) and
20 the evaluated burst position is selectable (BGPOS).
IFCOMP=’010’
25
Color standard (STDET), line standard (LNSTDRD)
30
0 1 2 3 4 5 6
and color killer status (CKSTAT) can be read out.
Frequency (MHz)
Standard CSTAND
+0dB CON
(60 Hz) D6 D5 D4 D3
None 0 0 0 0
PAL60 0 0 0 1
color off
Standard CSTAND
+6dB -4dB
PAL N 0 0 1
Fig. 2–8: Color killer adjustment
PAL B 0 1 0
attenuation [dB]
10
’010’
NOTCHOFF automatically disables or enables the 15
’011’
notch filter depending on color standard. TNOTCHOFF
always disables the notch filter. 20
’001’
25
A simple lowpass-filter is enabled by LPPOST to
reduce high-frequency noise component from the 30
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
CVBS signal. frequency [MHz]
Table 2–7: Notch-filter Fig. 2–10: Filter characteristics for PAL B/G, NTSC44,
PAL60
0 0 Always enabled
characteristic for SECAM (4.25 MHz)
5
0 1 Always disabled
NTCHSEL=
4.25
0
1 0 Depending on color
standard 5
’100’
attenuation [dB]
’000’
1 1 Always disabled 10
’001’
15 ’010’
20
’011’
10
Fig. 2–11: Filter characteristics for SECAM
(SECNTCH=’01’, 4.25 MHz)
15
20
For applications for which a black offset is not desired,
25
controlling may be done using LMOFST (see Fig. 2–
12). The positive or negative offset is added to the Y
30 signal.
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6
frequency [MHz]
2.2.9. Synchronization
multiplication
NSRED
before PLL
(I²C)
phase deviation
adcsel
R/V
Anti V YUV
adc3 Alias Skew Offset RGB
Filter ð
YUV
G/Y
Anti Y
or bypass down
adc4 Alias Skew Offset
Filter sampling
contrast YUV YUV
channel
soft-
brightness mux yuv 4:2:2
4:4:4 mix
Anti saturation ð
B/U U
adc5 Alias Skew Offset tint 4:2:2
Filter a
FB
Anti FB YUV
Offset,
adc6 Alias Skew t Gain
Filter
yuv 4:2:2
from itu656
2.3.1. Signal Magnitudes and Gain Control an additional chrominance lowpass can be enabled by
CHRSF.
Each ADC can be gain adjusted by AGCADJR, AGC-
ADJG, AGCADJB, AGCADJF
RGB-prefiltering
10
2.3.2. Clamping 3
0
attenuation [dB]
10
can be adjusted independently by CLAMP_SYNC, AASEL=1
CLAMP_RGB and CLAMP_CHROMA. Depending on 20
the input signal format (YUV, RGB, sync signal or not)
AASEL=0
these bits must be set accordingly. On the digital side, 30
Fig. 2–17: YPbPr to YCrCb matrix (BTA) 01 x Only RGB/YUV path visible
11 x (Reserved)
Y Pr 0,196 1 0,102
Cb = Y ⋅ – 0,111 0 0,991
Cr Pb 0,988 0 – 0,073 2.3.6.1. Static Switch Mode
In the static mixer mode as well as in the previously PFBL, PG, PR, PB indicate an overflow of the corre-
mentioned static switch mode, the softmixer operates sponding ADC (upper limit: ADC=511) exceeding 5
independently of the analog fast blank input. clock cycles duration. These signals are also set by
overflow and reset by I²C read only.
MIXGAIN ( FB – FBLOFFST ⋅ 2 )
k = ------------------------------------------------------------------------------------ + 64
2
analog fast
blank input
reading I2C
register
FBLSTAT 0 1 1 0 0
FBLRISE 0 1 0 0 0
FBLFALL 0 0 0 1 0
FBLHIGH 0 1 1 1 0
noise
letter box
measure
detection
ment
yuv 4:2:2 to
horizontal 656 encoder
horizontal line
yuv 4:2:2 post-
prescaler memory yuv 4:4:4 to
scaler
display processing
panorama
generator
Hardware Software
LBSLAA
LBTOPTITLE
zooming parameters
horizontal and/or
YUVin YUVout
vertical
resizing
HSYNC
2*LBVWSTUP
VSYNC
2* LBVWENDUP
2*LBVWSTLO
2* LBVWENDLO
4*LBHWST
4* LBHWEND
Fig. 2–24: Image format before memory HINC0...HINC4 define the increment of each segment,
indicating the amount of decimation/expansion. One
LSB is equivalent to an offset of 0.125 to HSCPRESC
The horizontal prescaler reduces the number of input per double pixel. Thus, HINCx alters HSCPRESC in
pixels by subsampling between 1 and 64. To prevent the range from −32...31.875 per double pixel.
the introduction of alias distortion low pass filters are
used for luminance and chrominance processing con- Table 2–10: Examples of Panorama Mode
trolled by HAAPRESC. In case of automatic mode the
filter characteristic is adopted to the prescaler settings Function Normal Extreme Lens
HSCPRESC and HDCPRESC, while in case of
ITU656 input, the lowpass filter must be disabled. HSCPRESC 1536d 1536 1536d
The horizontal postscaler provides a linear or a non- HINC1 14d 32d -16d
linear expansion of the picture.
HINC2 000d 000d 000d
The linear expansion mode is required, for example, to HINC3 -14d -32d 16d
display the center part of a 16:9 picture on a 4:3 tube.
Its setting range is 1...4 in steps of 2 pixel (HSCPOSC) HINC4 -29d -63d 31d
and the horizontal scaling factor is calculated by
4095
HSCALE = ------------------------
HSPOSC
INC_VAL
31.875
HINC0
HINC1
HINC2 output
0 pixels
HINC3
HINC4
-32
HSCALE
4095
compression
3072
expansion
HSCPOSC
(I²C)
1024
output
0 HSEG1 HSEG2 HSEG3 HSEG4 max. pixels
NA No Acknowledge
The VSP is selected by transmitting the VSP device
address. A device address pair is defined as a write DAW Device Address Write
address and a read address.
DAR Device Address Read
S DAW A SUB A DH A P
S DAW A SUB A DH A DL A P
read only register R I2C read registers reflect the status of internal hard-
ware. The take-over from hardware into the I2C regis-
reset after read register R ter can be immediate or synchronized with an internal
vertical sync signal. This is indicated by the sync infor-
mation in the I2C register description (see Table 3–9
3.4. I2C Register Domains on page -33). Registers without sync information have
immediate take-over.
The I2C registers are located in different functional
domains (see Table 3–7). Every domain has an inde- Some I2C read registers have a special update mech-
pendent update mechanism controlled by a set of anism to allow detection of fast and single events.
update registers (see I2C on page -55). These registers behave like a RS flip-flop and are
therefore called “RS type” registers. Whenever the cor-
responding signal has a high level, it sets the register
Table 3–7: I2C register domains to “1”. After being read via I²C bus, the register will
automatically be reset to “0”. These registers have an
Functional Domain Sub- Sync extra note in in the I2C register description (see
Block Domain Table 3–9 on page -33).
color decoder CD CD VS_CD For example, the register FBLACTIVE belongs to the
ADC frontend ADC VS_ADC “RS type” read registers. It indicates activity on the
comb filter COMB VS_COMB fastblank input pin. Reading FBLACTIVE = “1” means
that there was at least one short fastblank pulse since
RGB process- RGB RGB VS_RGB the last reading of this register.
ing
4-28
Table 3–8: I2C Subaddress Index
12.12.2003; 6251-573-4-1AI
h0D CLMPHIGH[7:0] SCMIDL[1:0] CLMPST2S[5:0] h3C19
h0E IFCOMP SECACCL[2:0] CLMPLOW[3:0] ACCLIM[4:0] IFCOMP[2:0] h03A4
STR
h0F SLLTH- VDE- CLMPD2S[3:0] CLMPD1S[3:0] h1F77
DVP TIFS
h10 BELLIIR[2:0] VDETITC[2:0] SECDIV SCMREL[1:0] hF701
h11 DEEMP- BELLFIR[2:0] SLLTHDV[2:0] FLNSTRD[1:0] ISHFT[1:0] NOTCH VLP[1:0] h3005
STD OFF
h12 PALDEL[1:0] TNOTC PALINC PALINC PALIDL CLRANGE[1:0] NOTCHSEL[2:0] TRAP- TRA- h4800
HOFF 1 2 2 BLU PRED
h13 CDYUVI COMBUSEVBI[1:0] CDYUVTINT[8:0] h0000
N
h14 BGSHIF PALDETIDL[1:0] h0004
T
h15 FEMAG[4:0] SDR[1:0] SDB[1:0] ITUSYN ART- h8280
C SYNC
h16 DEEMPFIR[3:0] DEEMPIIR[2:0] AMSTD50[1:0] AMSTD60[1:0] AGCP- AGCTHD[1:0] h5400
WRES
Micronas
ADVANCE INFORMATION
Table 3–8: I2C Subaddress Index, continued
Micronas
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h17 CLMPSIG1[1:0] CLMPSIG2[1:0] YCBYR UNSTA STAB- h0810
BMINT WINRE
D
h18 PWADJCNT[4:0] MINV[7:0]
h19 LPFLD[7:0] NRPIXEL[7:0]
h1A STDET[2:0] SCOUT PALID CKSTAT LNST- INT SCDEV[5:0]
ADVANCE INFORMATION
EN DRD
h1B VFLYM VLENGTH[6:0] AGCADJ[5:0]
D
h1C AM50 AM60 PALDET STAB BAMPL[7:0]
h1D PHERR_AVG[7:0] PHERR_MAX[7:0]
Volume 4: Video Processor
12.12.2003; 6251-573-4-1AI
h26 MVPSP MVAGC MVC- MVC- MVAGC MVRESULT[1:0]
ULSE PULSE STRIPE STRIPE PRO-
T CESS
h28 TRIM_FILTER1[4:0] AGCADJ1[5:0] VINSEL1[3:0] h4A00
h29 TRIM_FILTER2[4:0] AGCADJ2[5:0] VINSEL2[3:0] h4A0F
h2A AGCADJVBI[5:0] h0200
h2B CLAMP CLAMP CLAMP CLAMP h0000
_SHUT _SYNC1 _RGB1 _CHRO
OFF1 MA1
h2C CLAMP CLAMP CLAMP CLAMP h0000
_SHUT _SYNC2 _RGB2 _CHRO
OFF2 MA2
h2D VOUTSEL3[3:0] VOUTSEL2[3:0] VOUTSEL1[3:0] h0FF0
h2E STAND STAND STAND STAND STAND h0000
BY_VO BY_VO BY_VO BY_AD BY_AD
UT3 UT2 UT1 C2 C1
h2F h0000
h30 h0000
h31
VCT 49xyI, VCT 48xyI
4-29
Table 3–8: I2C Subaddress Index, continued
4-30
Sub Data Bits Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h32
h33 h81AC
h34 h00E4
h36 h00E4
h37 h00E4
h38 h81AC
h39 h81AC
h3A
h3B
VCT 49xyI, VCT 48xyI
12.12.2003; 6251-573-4-1AI
h43 CLAMP CLAMP CLAMP CLAMP CLAMP h0020
_SHUT _SYNC6 _RGB6 _CHRO _FBL6
OFF6 MA6
h44 STAND STAND STAND STAND h000F
BY_AD BY_AD BY_AD BY_AD
C6 C5 C4 C3
h45 YUVMAT[1:0] TINT[6:0] h0000
h46 BRTADJ[7:0] CONADJ[5:0] CHRSF AASEL h0080
h47 FBLDEL[2:0] GOFST[2:0] MIXGAIN[6:0] SELMASTER[1:0] h4018
h48 YFDEL[6:0] UVDEL[6:0] FBLCO h0000
NF
h49 USATADJ[5:0] VSATADJ[5:0] ADC- AABYP h8200
SEL
h4A MIXOP[1:0] h0000
h4B FBLOFFST[5:0] YUVSE SMOP RBOFST[2:0] h8100
L
h4C FBSTAT
Micronas
ADVANCE INFORMATION
Table 3–8: I2C Subaddress Index, continued
Micronas
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h4D FBFALL FBRISE PFBL PG PB PR FBLAC-
TIVE
h50 CFOR- VSIG- H_POL V_POL F_POL EN_656[1:0] h0058
MAT NAL
h51 ADINS ADLINE[4:0] NAPIPPHI[1:0] F_OFFS[1:0] VSREF IMODE[1:0] h0000
h52 HSPPL[7:0] VSLPF[6:0] h0000
ADVANCE INFORMATION
12.12.2003; 6251-573-4-1AI
h6F LBGRADDET[7:0] LBVWENDLO[7:0] h3296
h70 LBHIWHITE[7:0] LBHWEND[7:0] h32B4
h71 LBHISTBLA[7:0] LBHWST[6:0] h1924
h72 LBVWSTLO[6:0] LBFS LBVWENDUP[6:0] hE049
h73 LBGSDEL[4:0] LBGFBDEL[4:0] LBVWSTUP[5:0] h52D4
h74 LBASDEL[4:0] LBACTIVITY[4:0] LBTHDNBNG[4:0] h00AF
h75
h76
h77
h78
h79
h7A
h7B LBFOR- LBSUB- LBTOP-
MAT TITLE TITLE
h7C LBSLAA[6:0] LBELAA[8:0]
VCT 49xyI, VCT 48xyI
4-31
Table 3–8: I2C Subaddress Index, continued
4-32
Sub Data Bits Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h7D
h7E LBD-
STATUS
h82 YBORDER[3:0] UBORDER[3:0] VBORDER[3:0] h1000
h83 FRC_B h0000
GN
h84 HSCPRESC[11:0] h0000
h85 HAAPRESC[1:0] HDCPRESC[3:0] h0000
h86 APPL[9:0] h021C
h87 NAPPLIP[9:0] h005C
VCT 49xyI, VCT 48xyI
Volume 4: Video Processor
12.12.2003; 6251-573-4-1AI
h91 HSEG2[10:0] h0000
h92 HSEG3[10:0] h0000
h93 HSEG4[10:0] h0000
hF0 LOMID- OSDCLKCTRL[1:0] OSD- RGBOF CVB- CLKFE4 ITUIOFF ITUOOF DIS- DEFLO LLPLLO FCLKB2 PLLOFF h07FC
FREQ OFF F SOFF 0OFF F POFF FF FF LL
hF1 PUP- PUPIO PUPDIG
DAC
hF9 DISCPURES[15:0] h0000
hFA h0000
hFB VCTH_ID_SET[4:0] AUTO- h0000
INC
hFC VCTH_ID_RD[4:0] REV[4:0]
hFD VS_OP_ VS_IP_ VS_ITUI VS_RG VS_CD_
STAT STAT _STAT B_STAT STAT
hFE IM_OP IM_IP IM_ITUI IM_RGB IM_CD h0000
hFF VS_OP VS_IP VS_ITUI VS_RG VS_CD h001F
B
Micronas
ADVANCE INFORMATION
ADVANCE INFORMATION VCT 49xyI, VCT 48xyI
Volume 4: Video Processor
Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-573-5-1AI retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Volume 5:
Display and Deflection
Processor
Volume 5: Display and Deflection Processor
Edition 12.12.2003
6251-573-5-1AI
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
Contents
5-4 1. Introduction
5-4 1.1. Chip Architecture
5-4 1.2. Features
5-5 1.3. Overview
Contents, continued
1. Introduction
SPEAKER
TAGC
AOUT
AIN
SIF
VERT
CVBS in Comb Color
Filter Decoder Display & EW
YCrCb in Video Panorama Video
Deflection SVM
RGB in Frontend Scaler Backend
Component Processor RGB out
CVBS out Interface RGB in
SENSE
RSW
I2C Master/
Bus Display I2C
Slicer Slave
Arbiter Generator
Timer
CRT
PWM RESETQ
24 kB CPU Reset & Test
ADC
Char ROM 8051 Logic TEST
UART
Watchdog
RTC
256 kB Memory Clock XTAL1
20 kB XRAM
Prog ROM Interface I/O-Ports Generator XTAL2
1.2. Features – dynamic black stretch (DBS) with peak black and
activity detection and contrast adaption
The DDP contains the entire digital video component
– luma sharpness enhancement (LSE)
and deflection processing, as well as all analog inter-
faces to display the picture on a Cathode Ray Tube – color transient improvement (CTI)
(see Fig. 1–1).
– brightness, contrast, saturation and tint
– programmable YCrCb to RGB matrix
Display Processing
– static black stretch, blue stretch, gamma correction
– dynamic contrast improvement (DCI)
by a programmable Non-linear Colorspace
– dynamic black level expander (BLE) Enhancer (NCE) on RGB
– dynamic horizontal EHT (amplitude/phase compen- Two analog sources can be inserted in the main RGB,
sation with Tc ~ 1 line) controlled by separate fast blank (FBL) signals. Con-
– vertical angle and bow correction trast and brightness are adjusted separately from main
RGB. One internal input is dedicated to RGB for on-
– differential vertical outputs screen display (OSD). The second external RGB input
– vertical zoom via deflection adjustment is processed with a programmable contrast reduction.
– horizontal and vertical protection circuit An integrated processor controls the horizontal and
– black switch-off procedure (BSO) vertical deflection, tube measurement loops and beam
current limitation. It is also used to calculate an ampli-
– soft start/stop of H-drive tude histogram of the displayed image.
– supports horizontal and vertical dynamic focus
The horizontal deflection is synchronized with two
numeric phase-locked loops (PLL) to the incoming
Backend Features sync. One PLL generates the horizontal timing signals,
e.g., blanking and key-clamping. The second PLL
– external analog SCART (RGB/FB) input
adjusts the phase of the horizontal drive pulse with a
– internal analog OSD (RGB/FB/COR) input subpixel accuracy less than 1 ns.
– fast blank priority and monitoring via I2C
Vertical deflection and East/West correction wave-
– analog RGB and SVM current output forms are calculated as 6th order polynomials. This
allows adjustment of an East/West parabola with trap-
– user brightness for main and external RGB signal
ezoidal, pin cushion and an upper/lower corner correc-
– user contrast for analog RGB insertion tion (even for real flat CRTs), as well as a vertical saw-
tooth with linearity and S-correction. Scaling both
– differential vertical sawtooth waveforms, and limiting to fixed amplitudes, performs a
– E/W parabola vertical zoom or compression of the displayed image.
A field and line frequent control loop compensates
– separate ADC for beam current measurement EHT distortions depending on picture content.
The display processing part provides a variety of pic- High-speed D/A converters are used to convert the
ture improvement features, such as automatic contrast digital RGB to analog signals.
improvement, black level expansion, and luma sharp-
ness enhancement in the luminance part, as well as The display processing part operates on a common
transient improvement in the chrominance path (see clock frequency of 20.25 MHz, line-locked, providing a
Fig. 2–1). In addition, it supports the adjustment of frequency headroom for the mentioned high-quality
contrast, brightness, saturation and tint. picture enhancements.
meas-wnd
osd-cor
extrgb
xdfp-if
iref
yuv 4:4:4 Test White
DCI Pattern Drive * R DAC r-dac
std-if Generator BCL
LTI I2C
CTI SVM SVM DAC svm-dac
Peaking Slave
sda clkb20
VSUP1.8DIG GND scl VSUP3.3DAC GNDDAC
dci_tff_2
MEAN
The basic function of DCI is to analyze the picture
framewise and to adjust the parameters of a dual seg-
bl AlP = bl/al
ment transfer function, depending on the analyzed
DCIYLOW al
results for the best subjective picture quality. There-
fore, each image frame is analyzed for three different 0
characteristics (see Fig. 2–2). The image average X
0 MEAN 255
brightness (MEAN) of the input picture, which is
derived from a histogram of the input picture, a dark
and a white sample distribution of the output picture. X luminance Y
transfer
These parameters control the transfer function. The function
dual segment transfer function consists of two seg-
ments with an adaptive pivot point: a lower segment for
dark samples and an upper segment for light samples. Fig. 2–2: DCI basic function
The gain of the lower segment is adaptive to the dark
sample distribution. A higher gain results from fewer
dark samples and a lower gain from a higher number
of dark samples. The gain is limited in a certain range.
The gain of the upper segment is adaptive to the white
sample distribution. Its functionality is the same as for
the lower segment.
out compression
expansion
black
subblack
BLEGAIN } region
BRF X TILT Lin
(picture dependant) (max of range)
Auto-contrast mode
in
Lout
TILT
BLEGAIN
black
BLEGAIN } subblack
region
BRF SBLE TILT Lin
(static value)
Static BLEC mode
2.1.3. Luma Sharpness Enhancer (LSE) The peaking features two selectable center frequen-
cies of 2.5 MHz or 3.2 MHz (see Fig. 2–6). An adjust-
Sharpness is one of the most critical features for opti- able coring threshold prevents the enhancement of
mum picture quality. This important processing is per- small noise amplitudes.
formed in the LSE circuitry of the DDP.
dB
It consists of the dynamic peaking and the luma tran- 20
sient improvement (LTI). The luma input signal is pro- 15
cessed in the peaking and LTI block in parallel. Both 10 CF= 3.2 MHz
output signals are combined depending on the
5
selected LSE characteristics.
0
−5
−15
The dynamic peaking improves the details of a picture −20
using contour emphasis. It adapts to the amplitude and 0 0.1 0.2 0.3 0.4 0.5 f/fclk
−15
−20
dB 0 0.1 0.2 0.3 0.4 0.5 f/fclk
20
15
−5
−10
−15
−20
0 0.1 0.2 0.3 0.4 0.5 f/fclk
H-SYNC
HORPOSP HORWIDTHP
HORPOSC HORWIDTHC
HORPOSG/M HORWIDTHG/M
HORFRAMEG
VERPOSP
V-SYNC
VERPOSG
VERPOSC
VERFRAMEG
Master
VERWIDTHG
VERWIDTHC
VERWIDTHP
M
G
master frame
Background
Curtain
The pixel mixer combines the following additional lay- 2.1.5.1. Picture Frame Generator
ers with the main video (master channel M):
The picture frame generator provides an adjustable
– Picture Frame G
border surrounding the displayed picture, e. g. if the
– Curtain C picture does not fill the full screen. Another possibility
is the insertion of a horizontal or vertical stripe, e. g. for
– Test Pattern and Background P
split-screen applications. Size, position, and active
area are programmable, as well as the frame color.
The position and size of each layer is defined by the
corresponding I2C-register HORPOSx, VERPOSx,
HORWIDTHx, VERWIDTHx, HORFRAME and VER-
FRAME settings (see Fig. 2–8).
The window generator provides a 3-dim window to The test pattern generator provides the following eight
overlay a curtain on top of the displayed picture. video patterns (see Fig. 2–12):
Depending on the window start position and direction
1. colored background (constant luminance and
(open or close window) the size of the window is
chrominance)
increased or decreased in horizontal and /or vertical
direction by every field. 2. geometry (0% and 9.4% overscan grid, as well as
center position grid)
Fig. 2–9 shows the horizontal window function. The
window can be closed or opened. 3. balance (white drive and cutoff reference)
4. Y ramp (Y ampl. = −7...106%, increased by 2 every
clock cycle, Cr = Cb = 0)
close window
open window
center
Fig. 2–10: Vertical windowing
open window
0 YBAGR 0
R MR1M MR2M
CTM SATM 1 CTM
- × ---------------- × ------ × MG1M MG2M × Cb + ÿ ------------- × Yþ
G = ------------
32 32 64 Cr 32
B MB1M MB2M
0 0.7 1.4 2.1 2.8 5.7 8.6 11.4 14.2 17.1 20%
Fig. 2–14: Balance test pattern The Non-linear Colorspace Enhancer NCE has follow-
ing parameters
The size of the test pattern is 1080 pixel x 288 lines. – Gamma correction with 2 selectable gamma base
For a display area greater than 1080 x 288, the sur- functions (common for RGB)
rounding pixels are blanked. – subjective white shaping for R,G and B separately
– Peak White limitation tilt point and gain (common for
2.1.6. Contrast, Brightness, Saturation and Tint RGB)
The luminance signal is multiplied by a contrast value These different functions are cascaded to enable a
between 0 and 2 subdivided into 64 steps. The matrix large palette of non-linear functions.
coefficients are adapted to the contrast value automat-
ically to preserve the selected ratio between contrast
and color saturation.
100IRE
gamma > 0
The digital brightness value shifts the luminance by
(soft)
max. ±100% of its maximal amplitude (contrast gain linear
=1). It is desirable to keep a small positive offset with gamma > 0
the signal to prevent peaking undershoots and/or pic- (native)
ture content below black from being cut.
R 1 0 1.402 Y
G = 1 – 0.345 – 0.713 × Cb
B 1 1.773 0 Cr
Ampl.
0 SWS_SP 100IRE
SVM Yoke
100IRE
Current
DPWL_GAIN (<0)
0 DPWL_SP 100IRE
The digital RGB signals are converted to analog RGB converter (U/I-DAC), and inserted into the main RGB
by three digital to analog converters (DAC). by the fast blank switch.
Each RGB signal has two additional DACs to adjust The analog RGB outputs are current outputs with cur-
analog brightness (40% of the full RGB range) and cut- rent-sink characteristics. The maximum current drawn
off / black level (60% of the full RGB range). An addi- by the output stage is obtained with peak white RGB.
tional fixed current is applied for the blanking level.
The controlling of the white drive/analog brightness
The back-end supports the insertion of two external and also the external contrast and brightness adjust-
analog component signals, e.g., OSD or PIP. These ments is done via the internal XDFP Processor.
signals are clamped, converted by a voltage/current
mux SVMOUT
svm-dac
whitedrive R
int. bright *
cutoff R
r-dac ROUT
mux
whitedrive G
int. bright *
cutoff G
g-dac GOUT
mux
whitedrive B
int. bright *
cutoff B
b-dac BOUT
mux
whitedrive G
whitedrive R
whitedrive B
ext. bright *
ext. bright *
ext. bright *
VRD
DAC PWM
DAC DAC DAC EW
Reference EW
XREF
VERT+
PWM
whitedrive G
whitedrive R
whitedrive B
ext. contr *
ext. contr *
ext. contr *
* BCL
* BCL
RSW1 RIN
timing & control GIN
RSW2 BIN
FBIN
The DDP supports the insertion of: Insertion of transparent text pages or OSD onto the
video picture is often difficult to read, especially if the
– 1 external analog RGB signals (e.g. PIP) and
video contrast is high. The DDP features a contrast
– 1 internal analog RGB signal (OSD). reduction of the video background of 25%, 50% or
75% by means of a contrast reduction signal (COR).
Each component signal is clamped and inserted into This signal is supplied by the display generator of the
the main RGB by the fast blank switch. Both compo- controller. Inside the reduced contrast area the video
nent signals are adjustable independently as regards picture is displayed with reduced contrast, while the
DC level (brightness) and magnitude (contrast). analog component signals are still displayed with full
contrast.
FBFOH2 FBFOL2 FBMON Cutoff and white drive current measurement are car-
ried out during the vertical blanking interval. The cur-
Fig. 2–20: Fast Blank selection logic rent range for cutoff measurement is set by connecting
the sense resistor R1 to the SENSE input. Due to the
fact of a 1:10 relation between cutoff and white drive
Over/underlay of the external component signal and current the range select 2 output (RSW2) becomes
the main RGB signal depends on the fast blank input active for the white drive measurement and connects
signals and the corresponding I2C register (see Fig. 2– R3 in parallel to R1, thus determining the correct cur-
20). Both fast blank inputs must be either active low or rent range. During the active picture, the MADC is
active high. used for the average beam current limiter. Again a dif-
ferent measurement range is selected with active
All signals for analog component insertion (RIN1/2, range select 1&2 outputs (RSW1&RSW2) connecting
GIN1/2, BIN1/2, FBLIN1/2, HCS) must be synchro- R2 in parallel to R3 and R1. The corresponding timing
nized to the digital RGB. is shown in Fig. 2–21 and Fig. 2–22.
The presence of external analog RGB sources is Another method uses two different current measure-
detected by means of a fast blank monitor. The status ments:
of the selected fast blank input is monitored via an I2C
register. There is a 2-bit information, giving static and – The range switch 1 pin (RSW1) can be used as a
dynamic indication of a fast blank signal. The static bit second sense input, selectable by software. In this
is directly reading the fast blank input line, whereas the case, the cutoff and white drive currents are mea-
dynamic bit is reading the status of a flip-flop triggered sured as before at the SENSE input.
by the negative edge of the fast blank signal. – The active picture measurement can be done with
the second sense input (RSW1). The signal may
With this monitor logic it is possible to detect if there is come (via a proper interface) from the low end of the
an external RGB source active and if it is a full screen EHT coil (CRT anode current). In this case, the
insertion or only a box. The monitor logic is connected resistor R2 in Fig. 2–21 has to be removed.
directly to the FBLIN1 or FBLIN2 pin. Selection is done
via I2C register.
The picture tube measurement returns results on (CUT(WDR)_GAIN) the smaller the time constant
every field for: for the adjustment.
– cutoff R – If the automatic mode was once enabled
(CUT(WDR)_GAIN > 0), the control loop can be
– cutoff G
stopped by setting CUT(WDR)_DIS = 1. In this
– cutoff B mode the calculated cutoff and drive values will no
longer be modified and the measurement lines are
– white drive R or G or B (sequentially)
suppressed. Changes of the reference values
(CUT(WDR)_R/G/B) have no effect.
Thus a cutoff control cycle for RGB requires one field
only, while a complete white drive control cycle If one of the calculated red, green, or blue white drive
requires three fields. During cutoff and white drive values exceeds its maximal possible value (WDR_R/
measurement, the average beam current limiter func-
G/B>511), the white balance becomes maladjusted.
tion (see Section 2.2.5.) is switched off. The amplitude
An automatic drive saturation avoidance prevents this
of the cutoff and white drive measurement lines can be
effect (WDR_SAT = 1). If one drive value exceeds the
programmed separately with IBRM and WDRM (see
maximum allowed threshold (MAX_WDR), the ampli-
Fig. 2–22). The start line for the tube measurement
tude of the white drive measurement line will be
(cutoff red) can be programmed via I2C-bus (TML). increased, and decreased, if one of them goes below
the fixed threshold of 475.
The built-in control loop for cutoff and white drive can
operate in three different modes selected by
CUT(WDR)_GAIN and CUT(WDR)_DIS. beam current 2 beam current 1
– The user control mode is selected by setting
CUT(WDR)_GAIN = 0. In this mode the registers SENSE
CUT(WDR)_R/G/B are used as direct control values A
D
for cutoff and drive. If the measurement lines are
enabled (CUT(WDR)_DIS = 0) the user can read MADC
the measured cutoff and white drive values in the R2
RSW1
CUTOFF(WDRIVE)_R/G/B registers. An external
software can now control the settings of the R3
RSW2
CUT(WDR)_R/G/B registers.
– The automatic mode is selected by setting
R1
CUT(WDR)_GAIN > 0 and CUT(WDR)_DIS = 0. In
this mode, the registers CUT(WDR)_R/G/B are
used as reference for the measured values (CUT-
OFF(WDRIVE)_R/G/B). The calculated error is
used with a small hysteresis (1.5%) to adjust cutoff Fig. 2–21: MADC range switch
and drive. The higher the loop gain
2.2.5. Average Beam Current Limiter 2.3.2. Output Data Controller (ODC)
The average beam current limiter (BCL) works on both The ODC generates internal horizontal and vertical
the digital YCrCb input and the inserted analog RGB synchronization signals and defines the position of the
signals by using either the sense input or the RSW1 active video data.
input for the beam current measurement. The BCL
uses a different filter to average the beam current dur- The ODC supports three different modes:
ing the active picture.
– locked mode
The beam current limiter allows the setting of a thresh- – free-run mode
old current, a gain and an additional time constant. If
the beam current is above the threshold, the excess – auto free-run mode
current is low-pass filtered with the according gain and
In free-run mode, the backend part works stand alone
time constant. The result is used to attenuate the RGB
without analyzing the input signal. Thus, input data
outputs by adjusting the white drive multipliers for the
part and output data part are not related to each other.
internal (digital) RGB signals, and the analog contrast
In free-run mode, the output signals of the ODC are
multipliers for the analog RGB inputs, respectively. The
lower limit of the attenuator is programmable, thus a generated depending on I²C-bus settings.
minimum contrast can always be set. If the minimum
In locked mode the video backend part works with a
contrast is reached, the brightness will be decreased
line locked clock. This means that the video frontend
to a programmable minimum as well. Typical charac-
and the video backend depend on each other. The
teristics of the BCL for different loop gains are shown
generation of the controlling signals depends on sig-
in Fig. 2–23; for this example the tube has been
assumed to have square law characteristics. nals from the frontend. This mode is the default mode
for standard TV applications.
beam current
1.5 “H-free-running/ 1 0
gain = 60% V-locked” mode
threshold 1 gain = 90% “H-locked/ 0 1
V-free-running” mode
1 1.5 2 drive “H and V-free-running” 1 1
mode
Fig. 2–23: Beam current limiter characteristics:
beam current output vs. drive
When no or very weak signal is connected to the
CVBS input, the ODC can be configured to automati-
2.3. Synchronization and Deflection cally switch into free-running mode. This stabilizes the
display which may contain OSD information, e.g. dur-
2.3.1. Line-Locked Clock Generator ing channel-tune. The configuration can be effected by
AUTOFRRN.
The clock generation system derives all clocks from
one 20.25 MHz crystal oscillator clock source. Line- During free-run mode the phase offset between the
locked horizontal sync pulses are generated by a digi- generated h/v sync signals and the input h/v sync sig-
tal phase-locked loop. The time constant can be nal is undefined. Thus a switch from free-run to locked
adjusted between fast and slow behavior (KPL, KIL) to mode would causes visible artifacts on the screen and
accommodate different input sources (e.g.: VCR). inside the deflection circuitry. To prevent these distur-
Noisy input signals become more stable when noise- bances the generated h/v syncs are synchronized to
reduction is enabled (HSWIN). the input h/v syncs by modifying the horizontal line
length (PPLOFF) and the number of lines per field
The PLL control can be frozen up to 15 lines before v- (LPFOPOFF) until the h/v syncs are switched to locked
sync (FION) for a duration up to 15 lines (FILE). This mode. NOSYNC disables the synchronization circuit.
may be used to reduce disturbances by h-phase errors
which are produced by VCRs.
The OSC generates a HS and VS signal to support the The number of lines per field can be adjusted by soft-
insertion of external RGB signals (e.g. PIP). The polar- ware (LPFD). This number is used to calculate the ver-
ity of the sync signals is programmable. tical raster. The deflection processor (DP) synchro-
nizes only to a vertical sync within a programmable
detection window (LPFD ± VSYNCWIN). If there is no
2.3.4. Deflection Processing vsync the DP runs with maximum allowed lines and if
the vertical frequency is to high it runs with minimum
The deflection processing generates the signals for the allowed lines. The smaller the detection window the
horizontal and vertical drive (see Fig. 2–24) and com- slower the DP gets synchronized to the incoming verti-
prises the following blocks: cal sync. In case of an interlaced input signal it is pos-
sible to display both fields at the same raster position
– PLL3 adjusts the phase of the horizontal drive pulse
by setting R_MODE to 1 or 2.
and compensates for the delay of the horizontal out-
put stage.
An automatic field length adaptation can be selected
– The Soft-Start guarantees a progressive energy (VA_MODE). In this case the vertical raster will be cal-
ramp-up of the horizontal power stage culated according to the counted number of lines per
field instead from LPFD. This is useful for video
– The vertical sync, sawtooth and East/West circuitry
recorder search mode when the number of lines per
field does not comply with the standard, or if a com-
mon value of LPFD for PAL and NTSC is desired (e.g.:
2.3.5. Soft Start/Stop of Horizontal Drive
LPFD = 290; VSYNCWIN = 54).
In order to increase the energy supply of the horizontal
deflection stage smoothly, a soft start decreases the
drive frequency from 27 kHz to 15.625 kHz within
85 ms. The high time stays constant at 32 µs. This
means the duty factor decreases from 86% to 50%
(see Fig. 2–26).
Deflection Processing
- H-PLL3
E/W EW
- flyback control
hsync - soft start/stop
- vertical/east/west deflection
vsync - EHT compensation
- beam current limiter VERT+
- cutoff/whitedrive
Vertical
- histogram calculation
- horizontal & vertical protection incl. BSO VERT-
2.3.7. Vertical and East/West Deflection The vertical sawtooth signal will be generated from a
differential current D/A converter and can drive a DC
The calculations of the Vertical deflection and East/ coupled power stage. In order to get a faster vertical
West correction waveforms are done in the DP. They retrace timing, the output current of the vertical D/A-
are described as polynomials in x, where x varies from converter can be increased during the retrace for a
−0.5•zoom to +0.5•zoom for one field. For zoom>1, programmable number of lines (FLYBL). The range
the range is limited between −0.5 and +0.5. between the end of the flyback and the beginning of
the raster is also programmable (HOLDL).
The vertical deflection waveform is calculated as fol-
lows (without EHT compensation): The East/West deflection waveform, generated from a
single ended D/A converter, is given with the equation:
2 2
V = vpos + ampl ( x + lin ( x – offset ) + scor ⋅ x ( x – offset ) )
2 4
E ⁄ W = width + trapez ⋅ x + cush ⋅ x + corner ⋅ x
– VPOS defines the vertical raster position
– AMPL is the vertical raster amplitude – WIDTH is a DC value for the picture width
(zoom ≥ 1) – TRAPEZ is the trapezoidal correction
– LIN is the linearity coefficient – CUSH is the pincushion correction
– SCOR is the coefficient for S-correction – CORNU is the upper corner correction
– OFFSET is an internal parameter – CORNL is the lower corner correction
Vertical amplitude
E / W amplitude
-0.5 -0.3 -0.1 0.1 0.3 0.5 x -0.5 -0.3 -0.1 0.1 0.3 0.5 x
85 ms
...
tH = 32µs ... ... tH = 32µs
With vertical zoom it is possible to display different Picture tube and drive stage protection is provided
aspect ratios of the source signal on tubes with 4:3 or through the following measurements:
16:9 aspect ratio by adapting the corresponding raster.
– Vertical protection input: this pin watches the verti-
cal sawtooth signal. In every field the sawtooth must
descend below the lower threshold A and ascend
above the upper threshold B. In this case the protec-
tion flag is set (sawtooth o.k.). If an error occurs the
vertical
protection flag is cleared.
sawtooth
After a programmable number of fields with cleared
Start flag the RGB drive signals are blanked. The blank-
Stop ing is cancelled if the flag is set a programmable
number of lines (see Fig. 2–28)
East/West – Drive shutoff during flyback: this feature can be
parabola selected by software (EFLB)
– Safety input pin: this pin has two thresholds. The
lower threshold A watches for a positive edge in
normal zoom
every line, and the upper threshold B must not be
Fig. 2–27: Vertical zoom overshoot, otherwise the RGB signals are blanked
and a soft stop can be performed (HPROT_SS).
Both thresholds have a small hysteresis.
2.3.9. EHT Compensation
The vertical deflection waveform can be scaled 2.3.11. General Purpose D/A Converter
according the average beam current. This is used to
compensate the effects of electric high tension There are two D/A converters using pulse width modu-
changes due to beam current variations. EHT compen- lation. The resolution is 8 bit and the clock frequency is
sation for East/West deflection is done with an offset 20.25 MHz. The outputs are of the push-pull type. For
corresponding to the average beam current. The time a ripple-free output voltage a first order lowpass filter
constant of this process is free programmable with a with a corner frequency < 120 Hz should be applied.
resolution of 18 bit. Both corrections can be enabled
separately. The maximum scaling coefficient for verti- The D/A converters are adjusted via the I2C bus. They
cal deflection is 1±x and the maximum offset for East/ can be used to generate two DC voltages, for example
West is y, where x, y are adjustable from 0 to 0.25. The for horizontal raster position, raster tilt or just as
horizontal phase at the output HOUT can be influ- switching outputs, when the values 0 and 255 are
enced according to the average beam current in a selected.
range of ±1.5 µs.
accu
-1
~10 fields ~40 fields
blanking
t
3.1. I2C Bus Interface Basically there are two classes of I2C registers in the
DDP. The first class are directly addressable I2C Reg-
Communication between the DDP and the TVT (or ister. They are embedded in the hardware. These reg-
external controller) is done via I2C bus. The I2C bus isters are 16 bits wide and support read/write opera-
interface of the DDP acts as a slave receiver and as a tion.
slave transmitter. I2C clock synchronization is used to
slow down the I2C bus if required. The interface sup- The second class are XDFP-Register, which are part
ports the normal 100 kHz transmission as well as the of the on-chip risc processor named “XDFP”. These
high-speed 400 kHz transmission. registers are 16 bits wide and support read/write oper-
ation. Communication with these registers requires I2C
telegrams with a 16 bit register subaddress and 16 bit
SDA register data.
1
0 The I2C bus interface uses one level of subaddress.
SCL First the device address selects the DDP, then a sub-
S P address selects one of the internal registers. They
have 16-bit data size. All 16-bit registers are accessed
S = I2C-Bus Start Condition by reading/writing two 8-bit data words. Writing is done
P = I2C-Bus Stop Condition by sending the device address first followed by the
subaddress byte and two data bytes. For reading, the
Fig. 3–1: I2C-Bus protocol (MSB first, data must be read address has to be transmitted first by sending the
stable while clock is high) device write address followed by the subaddress a
second start condition with the device read address
and reading two bytes of data. Fig. 3–2 shows the I2C
The DDP is selected by transmitting the DDP device register protocol for read and write operations. The
address. A device address pair is defined as a write read operation requires an extra start condition and
address and a read address. repetition of the device address with read bit set.
S BChex Ack subaddr. Ack highbyte data Ack lowbyte data Ack P
S BChex Ack subaddr. Ack S BDhex Ack highbyte data AM lowbyte data Nak P
The following register types are defined in the detailed I2C write registers change the behavior of internal
I2C register description (see Table 3–6 on page 5-29): hardware. It is often required to synchronize these
changes so that they cause no visible artifacts on the
screen.
Table 3–2: I2C register types
The take-over from the I2C-bus telegram into the regis-
Register Types Dir ter can be either disabled or immediate or synchro-
nized with an internal vertical sync signal. This is con-
readable write register RW trolled by the I2C register bits VS_DP, VS_DEFL and
VS_ODC for vertical update and IM_DP, IM_DEFL
write only register W and IM_ODC for immediate update.
read only register R Registers without sync information in the I2C register
description (see Table 3–6 on page 5-29) have imme-
reset after read register R diate take-over.
3.7. XDFP Control and Status Registers Table 3–4: XDFP read/write address
S BChex Ack F2hex Ack highbyte data Ack lowbyte data Ack P
S BChex Ack F3hex Ack S BDhex Ack highbyte data AM lowbyte data Nak P
3.8. I2C Register Block Name Page Name Page Name Page
Index
FION[3:0] 30 MB2M[9:0] 37 VERWIDTHG[9:0] 36
FKOI 32 MG1M[9:0] 37 VERWIDTHP[9:0] 36
FKOIHYS 32 MG2M[9:0] 37 VFRAMEM[3:0] 36
Name Page
FMOD 29 MR1M[9:0] 37 VOUTFR 33
BLE 34
FRAME 34 MR2M[9:0] 37 VOUTPOL 33
CTI 35
FRAMEDIMM 36 NAPPLOP[8:0] 32 VS_DEFL 38
DAC 37
FRZLIMLR 32 ON 33 VS_DEFL_STAT 38
DCI 33
GSTGAIN[1:0] 34 OSDSYNCMODE 37 VS_DP 38
DEFL 37
GSTYE[3:0] 34 PATTDISCHROMA 36 VS_DP_STAT 38
I2C 38
GSTYG[1:0] 34 PATTINVERSE 36 VS_ITUO 38
LLPLL 29
GSTYR[1:0] 34 PATTMODE[2:0] 36 VS_ITUO_STAT 38
LTI 35
GSTYS[3:0] 34 PKCF[1:0] 35 VS_ODC 38
LUMAMATCH 34
HAUTOFRRN 33 PKCOR[4:0] 35 VS_ODC_STAT 38
LUMAMIX 35
HCROP[3:0] 34 PKNEG[3:0] 35 WHITE_LEVEL_L[7:0] 33
MATRIX 37
HORFRAMEG[4:0] 36 PKPOS[3:0] 35 WHITE_LEVEL_U[7:0] 33
ODC 32
HORPOS[10:0] 32 PPLOFF[4:0] 33 WHITE_TH[7:0] 33
OSC 33
HORPOSG[10:0] 36 PRIOC[2:0] 36 WINDHDR 36
PEAKING 35
HORPOSP[10:0] 35 PRIOF[2:0] 36 WINDHON 36
PIXMIX 35
HORWIDTH[10:0] 33 PRIOG[2:0] 36 WINDHSP[1:0] 35
SCE 34
HORWIDTHG[10:0] 36 PRIOM[2:0] 36 WINDHST 35
SVM 37
HORWIDTHP[10:0] 36 PRIOP[2:0] 36 WINDVDR 35
VIF 33
HOUTDEL[9:0] 33 PRIOS[2:0] 36 WINDVON 35
XDFP 37
HOUTFR 33 SAFETYMODE 37 WINDVSP[1:0] 35
HOUTPOL 33 SAT[5:0] 37 WINDVST 35
2 HOUTSTR 37 SBLE[2:0] 34 XDFPBUSY 37
3.9. I C Register Index
HPROTLIM[7:0] 37 SCETOG 34 XDFPRDA[15:0] 37
HRES 29 SHPULLIN 33 XDFPRDBUSY 37
Name Page HSWIN[3:0] 29 SLLWIN[1:0] 32 XDFPRDD[15:0] 37
ALP_UL[7:0] 34 IM_DEFL 38 STABLL 32 XDFPWRA[15:0] 37
AUP_UL[7:0] 34 IM_DP 38 STANDBYDAC 37 XDFPWRBUSY 37
BLACK_LEVEL_L[7:0] 33 IM_ITUO 38 STCANG[1:0] 34 XDFPWRD[15:0] 37
BLACK_LEVEL_U[7:0] 34 IM_ODC 38 STCGAIN[1:0] 34 YBAGR[3:0] 36
BLACK_TH[4:0] 33 KIL[4:0] 30 STCYG[1:0] 34 YBAGR2[3:0] 36
BLEFORCE 34 KINL[4:0] 32 STCYS[3:0] 34 YCUR[3:0] 36
BLEGAIN[1:0] 34 KOIH[1:0] 29 SVCORR[3:0] 37 YDELMATCH[2:0] 34
BLEMODE[1:0] 34 KOIWID[1:0] 29 SVDEL[3:0] 37 YFRAMEM[3:0] 36
BRF[2:0] 34 KPL[4:0] 31 SVDIFF[2:0] 37 YHIGH[7:0] 33
BRIGH[8:0] 37 KPNL[4:0] 31 SVGAIN[5:0] 37 YLOW[4:0] 33
BSTGAIN[1:0] 34 LIMEN 29 SVLIM[5:0] 37
BSTYG[1:0] 34 LIMHI 29 TILT[3:0] 34
BSTYS[3:0] 34 LIMII[7:0] 30 TINT[5:0] 37
CONTR[5:0] 37 LIMIP[7:0] 30 UBAGR[3:0] 36
CSYEN[1:0] 33 LIMLR[3:0] 32 UCUR[3:0] 36
CTIBW 35 LMIXGAIN[1:0] 35 UFRAMEM[3:0] 36
CTICOR[3:0] 35 LMIXOFS[4:0] 35 VAUTOFRRN 33
CTIGAIN[3:0] 35 LNL 29 VBAGR[3:0] 36
CTILP 35 LPFOP[8:0] 32 VCROP[3:0] 34
DEMO 34 LPFOPOFF[3:0] 33 VCUR[3:0] 36
DEMOMODE 33 LTICOR[2:0] 35 VERFRAMEG[4:0] 36
DISRES 29 LTIEN 35 VERPOS[9:0] 33
FHPULLIN 33 LTIGAIN[3:0] 35 VERPOSG[9:0] 36
FIELDEN 37 LTIGAIN2 35 VERPOSP[9:0] 36
FILE[3:0] 30 MB1M[9:0] 37 VERWIDTH[10:0] 33
5-26
Table 3–5: I2C Subaddress Index
12.12.2003; 6251-573-5-1AI
h1C VERPOS[9:0] h0001
h1D VERWIDTH[10:0] h0139
h1E HOUTDEL[9:0] h0116
h1F VAUTOF HAUTOF VOUTFR HOUTFR h0000
RRN RRN
h20 FHPUL- SHPUL- PPLOFF[4:0] LPFOPOFF[3:0] h138F
LIN LIN
h28 CSYEN[1:0] HOUT- VOUT- h0000
POL POL
h29 h0000
h2A h0000
h2B h0000
h2C h0000
h32 h0001
h33 YHIGH[7:0] DEMO- ON YLOW[4:0] hFF10
MODE
h34 WHITE_TH[7:0] BLACK_TH[4:0] hF010
Micronas
ADVANCE INFORMATION
Table 3–5: I2C Subaddress Index, continued
Micronas
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h35 WHITE_LEVEL_L[7:0] BLACK_LEVEL_L[7:0] h0101
h36 WHITE_LEVEL_U[7:0] BLACK_LEVEL_U[7:0] h0808
h37 AUP_UL[7:0] ALP_UL[7:0] hC0C0
h38 h0225
h39 h0000
ADVANCE INFORMATION
12.12.2003; 6251-573-5-1AI
h49 PKCF[1:0] h0008
h4A CTIBW CTILP CTIGAIN[3:0] CTICOR[3:0] h02A1
h50 WINDVSP[1:0] WIND- WIND- WIND- HORPOSP[10:0] h00C8
VST VDR VON
h51 WINDHSP[1:0] WINDHS WINDHD WIND- HORWIDTHP[10:0] h0438
T R HON
h52 VERPOSP[9:0] h0001
h53 VERWIDTHP[9:0] h0139
h54 VCUR[3:0] UCUR[3:0] YCUR[3:0] h0001
h55 YBAGR2[3:0] VBAGR[3:0] UBAGR[3:0] YBAGR[3:0] h2001
h56 VFRAMEM[3:0] UFRAMEM[3:0] YFRAMEM[3:0] h0001
h57 h0001
h58 HORPOSG[10:0] h00C8
h59 HORWIDTHG[10:0] h0000
h5A HORFRAMEG[4:0] VERPOSG[9:0] h0001
h5B VERFRAMEG[4:0] VERWIDTHG[9:0] h0000
h5C h00C8
VCT 49xyI, VCT 48xyI
5-27
Table 3–5: I2C Subaddress Index, continued
5-28
Sub Data Bits Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
h5D h0000
h5E h0001
h5F h0000
h60 PATT- PATTIN- PATTMODE[2:0] FRA- h1811
DIS- VERSE MEDIMM
CHROM
A
h61 PRIOF[2:0] PRIOS[2:0] PRIOG[2:0] PRIOM[2:0] PRIOC[2:0] h3977
h62 PRIOP[2:0] h0002
h64 MR1M[9:0] h0000
h65 MR2M[9:0] h0056
VCT 49xyI, VCT 48xyI
12.12.2003; 6251-573-5-1AI
h82 STAND- h0000
BYDAC
hD2 SAFET- OSDSY FIELDE HOUT- HPROTLIM[7:0] h06C0
YMODE NCMOD N STR
E
hF0 XDFPWRA[15:0] h0000
hF1 XDFPRDA[15:0] h0000
hF2 XDFPWRD[15:0] h0000
hF3 XDFPRDD[15:0]
hF4 XDF- XDFP- XDFP-
PRD- WRBUS BUSY
BUSY Y
hF5 h0000
hFD VS_DEF VS_ITU VS_ODC VS_DP_
L_STAT O_STAT _STAT STAT
hFE IM_DEF IM_ITUO IM_ODC IM_DP h0000
L
hFF VS_DEF VS_ITU VS_ODC VS_DP h000F
L O
Micronas
ADVANCE INFORMATION
ADVANCE INFORMATION VCT 49xyI, VCT 48xyI
Volume 5: Display and Deflection Processor
Note: For compatibility reasons every undefined bit in a writeable register should be set to “0”. Undefined bits in a
readable register should be treated as “don’t care”!
dynamic windowing:
The window starts with +/- 32µs and is reduced each time a
H-sync appeared inside the window (+/- 28µs; +/- 24µs; +/-
20µs; +/- 16µs; +/- 12µs; +/- 8µs; +/- 4µs;). If there is no H-
sync inside the window it is increased by one step.
Note: If PPLIP<1076d only "0101" or "0110" are allowed
LNL h03[2] RW 0 0,1 Linear or Non-Linear Mode
dynamic time constant control
0: linear mode
1: non linear mode
DISRES h03[1] RW 0 0,1 Disable Reset of LLPLL Watchdog
0: reset disable
1: reset enable
LIMHI h03[0] RW 0 0,1 Limit HDTO Increment
0: 2047 < HINCR < 524288
1: 2047 < HINCR < 393216
5-40
Table 3–7: XDFP-RAM Subaddress Index
hF2-006B CUTMEAS_R[8:0]
12.12.2003; 6251-573-5-1AI
hF2-006C CUTMEAS_G[8:0]
hF2-006D CUTMEAS_B[8:0]
hF2-010E h0000
hF2-010F h0000
hF2-0110 h0000
hF2-01C3 CUTREF_R[8:0] h0000
hF2-01C4 CUTREF_G[8:0] h0000
hF2-01C5 CUTREF_B[8:0] h0000
hF2-01C6 CUT_GAIN[8:0] h0000
hF2-006E WDRMEAS_R[8:0]
hF2-006F WDRMEAS_G[8:0]
hF2-0070 WDRMEAS_B[8:0]
hF2-0101 h03FC
hF2-0102 h03FC
hF2-0103 h03FC
Micronas
ADVANCE INFORMATION
Table 3–7: XDFP-RAM Subaddress Index, continued
Micronas
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hF2-01C7 WDR_GAIN[8:0] h0000
hF2-01C8 WDRREF_R[8:0] h0000
hF2-01C9 WDRREF_G[8:0] h0000
hF2-01CA WDRREF_B[8:0] h0000
hF2-01CB h0000
ADVANCE INFORMATION
hF2-004F BC[11:0]
hF2-01CD PWL_TC[8:0] h0000
hF2-01CE PWL_LIM[8:0] h0000
hF2-01CF BCL_BRTRED[8:0] h0000
hF2-01D0 BCL_GAIN[8:0] h0000
hF2-01D1 BCL_THRES[12:0] h0000
hF2-01D2 BCL_TC[8:0] h0000
hF2-01D3 BCL_TCUP[8:0] h0000
hF2-01D4 BCL_MIN_C[8:0] h0000
hF2-01D5 h0000
hF2-01D6 BC_MIN[11:0]
hF2-01D7 BC_MAX[11:0]
hF2-01DA PIC_TC[8:0] h0000
Volume 5: Display and Deflection Processor
12.12.2003; 6251-573-5-1AI
hF2-0071 HB1[14:0]
hF2-0072 HB2[14:0]
hF2-0073 HB3[14:0]
hF2-0074 HB4[14:0]
hF2-0075 HB5[14:0]
hF2-0076 HB6[14:0]
hF2-0077 HB7[14:0]
hF2-0078 HB8[14:0]
hF2-01E9 HISTO_ WDR_S h0000
EN AT
hF2-0131 HBST[10:0] h0502
hF2-0132 HBSO[10:0] h00D0
hF2-013B VBST[15:0] h0136
hF2-013A VBSO[8:0] h0018
hF2-0133 CLAMPSTART[7:0] h0000
hF2-0134 h0000
VCT 49xyI, VCT 48xyI
5-41
Table 3–7: XDFP-RAM Subaddress Index, continued
5-42
Sub Data Bits Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hF2-0135 h0001
hF2-0136 DFHB[10:0] h01F4
hF2-0137 DFHE[10:0] h0384
hF2-0000
hF2-0001
hF2-0002
hF2-0080
hF2-0081
hF2-0082
VCT 49xyI, VCT 48xyI
hF2-0083
hF2-0084
hF2-0085
hF2-0180 HPROT HPROT HOUT_ RAMP_ EFLB VPROT h0000
_SS _BL STOP EN _BL
hF2-0181 HDRV[5:0] h0020
hF2-0182 POFS3[15:0] hFFF4
hF2-0183 h0474
hF2-0184 h0592
hF2-0185 PKP3[8:0] h4000
Volume 5: Display and Deflection Processor
12.12.2003; 6251-573-5-1AI
hF2-0188 BOW[9:0] h0000
hF2-013D h050F
hF2-0190 VAMPL[9:0] h0000
hF2-0191 VZOOM[8:0] h4000
hF2-0192 VPOS[9:0] h0000
hF2-0193 VLIN[9:0] h0000
hF2-0194 SCORR[9:0] h0000
hF2-0195 VSYNWIN[6:0] h0020
hF2-0196 LPFD[9:0] h0138
hF2-0197 HOLDL[9:0] h000A
hF2-0198 FLYBL[9:0] h0005
hF2-01E2 h0000
hF2-01E3 R_MODE[1:0] h0000
hF2-01E4 h0000
hF2-01E8 VA_MO h0000
DE
Micronas
ADVANCE INFORMATION
Table 3–7: XDFP-RAM Subaddress Index, continued
Micronas
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hF2-01EB BSO_E h0000
N
hF2-019A WIDTH[8:0] h0000
hF2-019B TCORR[9:0] h0000
hF2-019C CUSH[9:0] EWPW h0080
M
ADVANCE INFORMATION
hF2-00C1 h0010
12.12.2003; 6251-573-5-1AI
hF2-00C2 h0010
hF2-00C3 h0010
hF2-0105 h0100
hF2-0106 h0100
hF2-0107 h0100
hF2-0108 h0100
hF2-0109 h0100
hF2-010A h0100
hF2-010B h03FC
hF2-010C h03FC
hF2-010D h03FC
hF2-0111 h0040
hF2-0112 h0040
hF2-0113 h0040
hF2-01DB EXT_CONTR[8:0] h0000
hF2-01DC EXT_BRT[9:0] h0000
VCT 49xyI, VCT 48xyI
5-43
Table 3–7: XDFP-RAM Subaddress Index, continued
5-44
Sub Data Bits Reset
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
hF2-01DD INT_BRT[9:0] h0000
hF2-01DE CORLEV[1:0] FBMON FBPOL FBPRIO FBFOL2 FBFOH FBFOL1 FBFOH h0000
2 1
hF2-00D1 PWM_VHS[7:0] h0010
hF2-00D2 PWM_CTRL[2:0] h0000
hF2-0020 VERSION[15:0]
VCT 49xyI, VCT 48xyI
Volume 5: Display and Deflection Processor
12.12.2003; 6251-573-5-1AI
Micronas
ADVANCE INFORMATION
ADVANCE INFORMATION VCT 49xyI, VCT 48xyI
Volume 5: Display and Deflection Processor
Note: For compatibility reasons every undefined bit in a writeable register should be set to “0”.
Undefined bits in a readable register should be treated as “don’t care”!
Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-573-5-1AI retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Volume 6:
Controller, OSD and Text
Processing
Volume 6: Controller, OSD and Text Processing
Edition 14.11.2003
6251-573-6-1AI
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
Contents
6-7 1. Introduction
6-7 1.1. Chip Architecture
6-8 1.2. Features
6-9 1.3. Overview
6-9 1.4. Block Diagram
Contents, continued
Contents, continued
Contents, continued
Contents, continued
1. Introduction
SPEAKER
TAGC
AOUT
AIN
SIF
VERT
CVBS in Comb Color
Filter Decoder Display & EW
YCrCb in Video Panorama Video
Deflection SVM
RGB in Frontend Scaler Backend
Component Processor RGB out
CVBS out Interface RGB in
SENSE
RSW
I2C Master/
Bus Display I2C
Slicer Slave
Arbiter Generator
Timer
CRT
PWM RESETQ
24kB CPU Reset & Test
ADC
Char ROM 8051 Logic TEST
UART
Watchdog
RTC
256kB Memory Clock XTAL1
20kB XRAM
Prog ROM Interface I/O-Ports Generator XTAL2
VSUP3.3EIO
Port Controller Pulswidth Capture Interpolation
UART
Multiplexer ADC Modulator Reload Timer Filter
GNDEIO
ADB ROM
Acquisition
DB 256k x 8
PSENQ
PSWEQ External
Memory IF XRAM
RDQ 20k x 8
WRQ
XROMQ Memory
8051 Bus
Management
Core Arbiter
Unit
Charact.
ALE ROM
OCF Extension 24k x 8
iRAM Interrupt
STOPQ Emulation IF Stack
256 x 8 Controller
ENEQ 128 x 8 Display
hsync
EXTIFQ Generator
vsync
Scan Path
MBIST CLUT
FIFO
Reset Reset Test
DACs
2. Functional Description
VSUP3.3IO
VSUP1.8DIG
DTO pixclk
GND
hflb
2.1.1. General Function Before the PLL is switched to power save mode
(PLLS = 1), the software has to switch the clock
The on-chip clock generator provides the TVT with its source from 648 MHz PLL-clock to the 20.25 MHz
basic clock signals that controls all activities of the oscillator-clock (SFR bit CLK_src = 1). In this mode
hardware. Its oscillator runs with an external crystal the Slicer, Acquisition, DAC and Display Generator are
and appropriate oscillator circuitry. switched off.
The on-chip phase locked loop (PLL) which is inter- To switch back, the software has to end the PLL power
nally running at 648 MHz is fed by the oscillator or can save mode (SFR-bit PLLS = 0), reset the PLL for
be bypassed to reduce the power consumption. If it is 10 µs (3 machine cycles, SFR bit PLL_res = ‘1’, then
not required to wake up immediately the PLL can also ‘0’ again), then wait 150 µs (38 machine cycles) and
be switched off. From the output frequency of the PLL switch back to the PLL clock (SFR-bit CLK_src = 0).
two clock systems are derived:
If Power Down Mode is activated, PLL and Oscillator
are send to sleep (SFR bit PDS = 1; refer to
2.1.2. System Clock Section 2.4.).
The 40.5 MHz system clock (fCPU) provides the pro- Furthermore, there are additional possibilities to dis-
cessor, all processor related peripherals, the sync tim- able the clocks for the peripherals. Please refer to
ing logic, the A/D converters, the slicer, the DG and Section 2.4.
the CLUTs.
2.1.3. Pixel Clock sition control etc. Many locations in the SFR address
space are addressable as bits.
The second clock system is the pixel clock (fPIX),
which is programmable in a range from 5 … 38 MHz. It
serves the output part of the display FIFO and the D/A Note: Reading from unused locations within data
converters. The pixel clock is derived from the high fre- memory will yield undefined data.
quent output of the PLL and line by line phase shifted
to the positive edge of the horizontal sync signal (nor-
mal polarity). Because the final display clock is derived Conditional branches are performed relative to the
from a DTO (digital time oscillator) it has no equidistant 16 bit program counter. The register-indirect jump per-
clock periods although the average frequency is exact. mits branching relative to a 16-bit base register with an
The pixel clock can also be inserted by an external offset provided by an 8-bit index register. Sixteen-bit
source which has a fixed and stable phase to an exter- jumps and calls permit branching to any location in the
nal horizontal sync. This pixel clock generation system memory address space.
has several advantages:
The processor has five methods for addressing source
– The frequency of the pixel clock can be pro-
operands: register, direct, register-indirect, immediate,
grammed independently from the horizontal line
and base register plus index register-indirect address-
period.
ing.
– Because the input of the PLL is already a signal with
a relative high frequency, the resulting pixel fre- The first three methods can be used for addressing
quency has an extremely low jitter. destination operands. Most instructions have a ‘desti-
nation, source’ field that specifies the data type,
– The resulting pixel clock follows the edge of the H- addressing methods and operands involved. For oper-
sync impulse without any delay and has always the ations other than moves, the destination operand is
same quality than the sync timing of the deflection also a source operand.
controller.
Registers in the four 8-register banks can be accessed
through register, direct, or register-indirect addressing;
2.1.4. Register Description the lower 128 bytes of internal data RAM through
direct or register-indirect addressing, the upper
see Section 3.4. on page 6-101 128 bytes of internal data RAM through register-indi-
rect addressing; and the special function registers
through direct addressing. Look-up tables resident in
2.2. Microcontroller program memory can be accessed through base regis-
ter plus index register-indirect addressing.
2.2.1. Architecture
2.2.2.3. Internal Data RAM 2.2.2.6. Program Status Word Register (PSW)
The internal data RAM provides a 256-byte scratch The PSW flags record processor status information
pad memory, which includes four register banks and and control the operation of the processor. The carry
128 direct addressable software flags. Each register (CY), auxiliary carry (AC), two user flags (F0 and F1),
bank contains registers R0 … R7. The addressable register bank select (RS0 and RS1), overflow (OV)
flags are located in the 16-byte locations starting at and parity (P) flags reside in the program status word
byte address 20H and ending with byte location 2FH of register. These flags are bit-memory-mapped within
the RAM address space. the byte-memory-mapped PSW. The CY, AC, and OV
flags generally reflect the status of the latest arithmetic
In addition to this standard internal data RAM the pro- operations. The CY flag is also the Boolean accumula-
cessor contains an extended internal RAM. It can be tor for bit operations. The P-flag always reflects the
considered as a part of an external data memory. It is parity of the A-register. F0 and F1 are general purpose
referenced by MOVX instructions (MOVX A, @DPTR), flags which are pushed onto the stack as part of a
the memory organization is explained in Section 2.6. PSW save. The two register bank select bits (RS1 and
RS0) determine which one of the four register banks is
selected as follows:
2.2.2.4. Arithmetic/Logic Unit (ALU)
The arithmetic section of the processor performs many Table 2–1: Register bank selection
data manipulation functions and includes the Arith-
metic/Logic Unit (ALU) and the A-, B- and PSW regis- RS1 RS0 Register Register Location
ters. The ALU accepts 8-bit data words from one or Bank
two sources and generates an 8-bit result under the
control of the instruction decoder. The ALU performs 0 0 0 00H … 07H
the arithmetic operations of add, subtract, multiply, 0 1 1 08H … 0FH
divide, increment, decrement, BCD-decimal-add 1 0 2 10H … 17H
adjust and compare, and the logic operations of and, 1 1 3 18H … 1FH
or, exclusive-or, complement and rotate (right, left, or
nibble swap).
2.2.2.7. Stack Pointer (SP)
The A-register is the accumulator, the B-register is
dedicated during multiply and divide and serves as The 8-bit stack pointer contains the address at which
both a source and a destination. During all other oper- the last byte was pushed onto the stack. This is also
ations the B-register is simply another location of the the address of the next byte that will be popped. The
special function register space and may be used for SP is incremented during a push. SP can be read or
any purpose. written to under software control. The stack may be
located anywhere within the internal data RAM
address space and may be as large as 256 bytes.
2.2.2.5. Boolean Processor
The Boolean processor is an integral part of the pro- Note: For memory above 64K, memory extension
cessor architecture. It is an independent bit processor stack is used, refer to Section 2.6.5.
with its own instruction set, its own accumulator (the
carry flag) and its own bit-addressable RAM and I/O.
The bit manipulation instructions allow the direct
addressing of 128 bits within the internal data RAM 2.2.2.8. Data Pointer Register (DPTR)
and several bits within the special function registers.
The special function registers which have addresses The 16-bit Data Pointer Register DPTR is the concate-
exactly divisible by eight contain directly addressable nation of registers DPH (high-order byte) and DPL
bits. (low-order byte). The DPTR is used in register-indirect
addressing to move program memory constants and to
The Boolean processor can perform, on any address- access the extended data memory. DPTR may be
able bit, the bit operations of ‘set’, ‘clear’, ‘comple- manipulated as one 16-bit register or as two indepen-
ment’, ‘jump-if-set’, ‘jump-if-not-set’, ‘jump-if-set then- dent 8-bit registers DPL and DPH.
clear’ and ‘move to/from carry’. Between any address-
able bit (or its complement) and the carry flag it can Eight data pointer registers are available, the active
perform the bit operation of logical AND or logical OR one is selected by a special function register (DPSEL).
with the result returned to the carry flag.
Note: Any Slow-down mode should only be used if 2.2.4.2. Direct Addressing
teletext reception and the display are disabled.
Otherwise processing of the incoming text data Direct byte addressing specifies an on-chip RAM loca-
might be incomplete and the display structure tion (only low part) or a special function register. Direct
will be corrupted. For disabling acquisition and addressing is the only method of accessing the special
display generator refer to Section 2.4.. function registers. An additional byte is appended to
the instruction opcode to provide the memory location
address. The highest-order bit of this byte selects one
of two groups of addresses: values between
2.2.4. Addressing Modes 00H … 7FH access internal RAM locations, while val-
ues between 80H … 0FFH access one of the special
There are five general addressing modes operating on function registers.
bytes. One of these five addressing modes, however,
operates on both bytes and bits:
2.2.4.3. Register-Indirect Addressing
– Register
– Direct (both bytes and bits) Register-indirect addressing uses the contents of
either R0 or R1 (in the selected register bank) as a
– Register-indirect
pointer to locations in the 256 bytes of internal RAM.
– Immediate Note that the special function registers are not acces-
sible by this method.
– Base register plus index-register indirect
Execution of PUSH and POP instructions also use reg-
The following list summarizes, which memory spaces ister-indirect addressing. The stack pointer may reside
may be accessed by each of the addressing modes: anywhere in internal RAM.
Register Addressing
2.2.4.4. Immediate Addressing
R0 … R7
ACC, B, CY (bit), DPTR Immediate addressing allows constants to be part of
the opcode instruction in program memory.
Direct Addressing An additional byte is appended to the instruction to
hold the source variable. In the assembly language
RAM (low part) and instruction set, a number sign (#) precedes the
Special Function Registers value to be used, which may refer to a constant, an
expression, or a symbolic name.
Register-indirect Addressing
Immediate Addressing
Program Memory
2.2.4.5. Base Register plus Index Register-Indirect In ports P1, P3 and P4 the output drivers provide
Addressing source current for one system clock period if, and only
if, software updates the bit in the output latch from a
Base register plus index register-indirect addressing ‘zero’ to an ‘one’. Sourcing current only on ‘zero to
allows a byte to be accessed from program memory one’ transition prevents a pin, programmed as an
via an indirect move from the location whose address input, from sourcing current into the external device
is the sum of a base register (DPTR or PC) and index that is driving the input pin.
register, ACC. This mode facilitates accessing to look-
up table resident in program memory. Secondary functions can be selected individually and
independently for the pins of Port 1 and 3. Further
information on Port 1's secondary functions is given in
2.2.5. Ports and I/O-Pins Section 2.11.. P3 generates the secondary control sig-
nals automatically as long as the pin corresponding to
There are three 8-bit ports P1, P2, and P3 available. the appropriate signal is programmed as an input, i. e.
Each pin can be individually and independently pro- if the corresponding bit latch in the P3 special function
grammed as input or output and each can be config- register contains a ‘one’.
ured dynamically. 4 pins of P1 can be used as analog
input.
Read Modify-Write Feature
An instruction that uses a port's bit/byte as a source
operand reads a value that is the logical AND of the ‘Read-modify-write’ commands are instructions that
last value written to the bit/byte and the polarity being read a value, possibly change it, and then rewrite it to
applied to the pin/pins by an external device (this the latch. When the destination operand is a port or a
assumes that none of the processor's electrical specifi- port bit, these instructions read the latch rather than
cations are being violated). An instruction that reads a the pin. The read-modify-write instructions are listed in
bit/byte, operates on the content, and writes the result Table 2–2.
back to the bit/byte, reads the last value written to the
bit/byte instead of the logic level at the pin/pins. Pins The read-modify-write instructions are directed to the
comprising a single port can be made a mixed collec- latch rather than the pin in order to avoid a possible
tion of inputs and outputs by writing a ‘one’ to each pin misinterpretation of the voltage level at the pin. For
that is to be an input. Each time an instruction uses a example, a port bit might be used to drive the base of a
port as the destination, the operation must write ‘ones’ transistor. When a ‘one’ is written to the bit, the transis-
to those bits that correspond to the input pins. An input tor is turned on.
to a port pin needs not to be synchronized to the oscil-
lator. If the CPU then reads the same port bit at the pin
rather than the latch, it will read the base voltage of the
All the port latches have ‘one’ s written to them by the transistor and interpret it as a 0. Reading the latch
reset function. If a ‘zero’ is subsequently written to a rather than the pin will return the correct value of ‘one’.
port latch, it can be reconfigured as an input by writing
a ‘one’ to it. Timer/Counter 0 Mode 3: Two 8-Bit Counters
1) Instruction reads the port byte (all 8 bits), modifies the addressed bit, then writes the new byte back to the latch.
The assembly language uses the same instruction set addr 16 – Destination address for LCALL & LJMP
and the same instruction opcodes as the 8051 micro- may be anywhere within the program
computer family. memory address space.
1) not applicable
Table 2–8: Instruction Opcodes, continued Table 2–8: Instruction Opcodes, continued
5D 1 ANL A, R5 83 1 MOVC A, @A + PC
5E 1 ANL A, R6 84 1 DIV AB
Table 2–8: Instruction Opcodes, continued Table 2–8: Instruction Opcodes, continued
9D 1 SUBB A, R5 C3 1 CLR C
9E 1 SUBB A, R6 C4 1 SWAP A
A4 1 MUL AB CA 1 XCH A, R2
A5 – reserved – CB 1 XCH A, R3
E7 1 MOV A, @R1
2.3.2. Interrupt Sources
E8 1 MOV A, R0
The TVT processor is capable of handling 24 interrupt
E9 1 MOV A, R1
sources. Two external sources via the INT0 and INT1
EA 1 MOV A, R2 pins and two additional external interrupts INTX0 and
INTX1 are provided. Peripherals also use interrupts.
EB 1 MOV A, R3
One from each of the two internal counters, one from
EC 1 MOV A, R4 the analog-to-digital converter and one from UART. In
addition there are four acquisition related interrupts,
ED 1 MOV A, R5
two display related interrupts and one interrupt indicat-
EE 1 MOV A, R6 ing change of channel, two interrupts are generated by
WDT and PWM overflow in timer mode.
EF 1 MOV A, R7
FB 1 MOV R3, A
FC 1 MOV R4, A
FD 1 MOV R5, A
FE 1 MOV R6, A
FF 1 MOV R7, A
Highest
Priority
Level
Interrrupt Request
IEN0.x Lowest
Priority
Level
Interrrupt Request P
o
IEN1.x l
l
i
n
g
Interrrupt Request
IEN2.x S
e
q
u
e
n
Interrrupt Request c
e
IEN3.x
Interrupts are enabled through a set of Interrupt All the interrupts except for timer 0, timer 1, external
Enable registers (IEN0, IEN1, IEN2, IEN3). interrupt 0, external interrupt 1, external extra interrupt
0 and external extra interrupt 1 are generated by the
Bits 0 to 5 of the Interrupt Enable registers each indi- respective blocks and are positive edge triggered.
vidually enable/disable a particular interrupt source. They are sampled in a central interrupt source register,
Overall control is provided by bit 7 of IEN0 (EAL). corresponding bit must be cleared by the software
When EAL is set to ‘0’, all interrupts are disabled: after entering the interrupt service routine.
when EAL is set to ‘1’, interrupts are individually
enabled or disabled through the other bits of the Inter-
rupt Enable Registers. EAL may however be overrid- 2.3.5. Interrupt Priority
den by the DISINT signal which provides a global dis-
able signal for the interrupt controller. For the purposes of assigning priority, the 24 possible
interrupt sources are divided into groups determined
by their bit position in the Interrupt Enable Registers
2.3.3.1. Interrupt Enable Registers (IEN0, IEN1, and their respective requests are scanned in the order
IEN2, IEN3) shown below.
The processor has 4 Interrupt Enable registers.The Each interrupt group may individually be assigned to
details of the registers are as follows. For each bit in one of four priority levels by writing to the IP0 and IP1
these registers, a 1 enables the corresponding inter- Interrupt Priority registers at the corresponding bit
rupt and a 0 disables it. position.
If two interrupts of the same priority level occur simul- Interrupts are sampled at S5P2 in each machine cycle
taneously, the order in which the interrupts are ser- and the sampled interrupts polled during the following
viced is determined by the scan order shown below machine cycle. If an interrupt is set when it is sampled,
????. it will be serviced provided:
– An interrupt of an equal or higher priority is not cur-
rently being serviced
2.3.5.1. Interrupt Priority Registers (IP0 IP1)
– The polling cycle is not the final cycle of a multi-
The Interrupt Priority registers are structured as fol- cycle instruction, and
lows.
– The current instruction is neither a RETI nor a write
either to one of Interrupt Enable registers or to one
2.3.6. Interrupt Vectors of the Interrupt Priority registers.
Interrupt Source Vector Interrupt Enable Flag Interrupt Request Flag Group
Address
# Name (hex) Register Bit Register Bit
The interrupt request flags IE0, IE1, TF0 and TF1 are
cleared when the processor transfers control to the
first instruction of the interrupt service program.
2.4. Power Saving Modes still operational. Leaving idle mode brings them to their
original power save configuration (See Section 2.4.4.).
The controller provides four modes in which power
consumption can be significantly reduced.
2.4.3. Power-Down Mode
– Idle mode: The CPU is gated off from the oscillator.
All peripherals except WDT (in watch dog mode) are
Entering the power-down mode is done by two con-
still provided with the clock and are able to work.
secutive instructions immediately following each other.
– Power-down mode: Operation of the controller is The first instruction has to set bit PDE (PCON.1) and
turned off. This mode is used to save the contents of must not set bit PDS (PCON.6). The following instruc-
internal RAM with a very low standby current. tion has to set bit PDS (PCON.6) and must not set bit
PDE (PCON.1). Bits PDE and PDS will automatically
– Power-save mode: In this mode Display Generator,
be cleared after having been set.
Slicer, CADC, CADC_wakeup, PWM, CRT, WDT,
OSD-DAC and PLL can individually be turned off.
This double-instruction sequence is implemented to
– Slow-down mode: In this mode the CPU clock fre- minimize the chance of unintentionally entering the
quency is divided by 4. power-down mode. The following instruction sequence
may serve as an example:
All modes are entered by software. Special function
register is used to enter one of these modes. ORL PCON,#00000010B ;Set bit PDE, bit
PDS must not be set.
2.4.1. Power-Save Mode Registers ORL PCON,#01000000B ;Set bit PDS, bit
PDE must not be set.
2.4.2. Idle Mode
The instruction that sets bit PDS is the last instruction
Entering the idle mode is done by two consecutive executed before going into power-down mode.
instructions immediately following each other. The first
instruction has to set bit IDLE (PCON.0) and must not Concurrent setting of the enable and the start bits does
set bit IDLS (PCON.5). The following instruction has to not set the device into the respective power saving
set bit IDLS (PCON.5) and must not set bit IDLE mode.
(PCON.0). Bits IDLE and IDLS will automatically be
cleared after having been set. This double-instruction If idle mode and power-down mode are invoked simul-
sequence is implemented to minimize the chance of taneously, the power-down mode takes precedence.
unintentionally entering the idle mode. The following
instruction sequence may serve as an example: The only exit from power-down mode is a hardware
reset. The reset will redefine all SFRs, but will not
ORL PCON,#00000001B ;Set bit IDLE, change the contents of internal RAM.
bit IDLS must not be set.
Concurrent setting of the enable and the start bits does Note: Power-save mode is independent of Idle and
not set the device into the respective power saving power-down mode. In case of idle mode, blocks
mode. which are in power save mode remains in
power-save mode.
The idle mode can be terminated by activation of any
enabled interrupt (or a hardware reset). The CPU-
operation is resumed, the interrupt will be serviced and Entering the power down mode with power-save mode
the next instruction to be executed after RETI-instruc- is possible. However leaving the power down mode
tion will be the one following the instruction that set the (reset) would initialize all the power save register bits.
bit IDLS. The port state and the contents of SFRs are
held during idle mode.
Note: Power-save mode has a higher priority then idle
Entering idle mode disables Slicer, Display, CADC and mode.
OSD-DAC. However note that CADC Wake up unit is
Setting the SD bit in PCON register divides the system All blocks are initialized to a known state. CPU, acqui-
frequency by 4. During the normal operation TVT is sition and display will not have any pending bus
running with 40.5 MHz and in SD mode TVT runs with requests after reset.
10.125 MHz. In slow-down mode Slicer and Display
Generator are disabled regardless of power-save
mode or other modes. All the pending request to the 2.5.6. RAMs
bus by these blocks are masked off. Leaving slow-
down mode restores the original status of these Reset hardware does not initialize any RAMs.
blocks.
2.5.9. Ports
2.5.2. Reset Filtering
With the reset all ports are set to input mode.
The RESETQ pin uses a filter with delay element,
which suppresses the jitter and spikes in the range of
25 ns to 75 ns. 2.5.10. Initialization Phase
2.5.10.1. Acquisition
2.5.3. Reset Duration
After reset the acquisition will not generate any mem-
With the active edge of the RESETQ an internal signal ory accesses to the RAM, as ACQON bit is initialized
resets all the flip flops asynchronously. The internal to 0. The CPU should then initialize the VBI buffer and
signal is released synchronously to the internal clock set the ACQON bit. The acquisition will also not gener-
when it is stable as described below. ate any accesses to the RAM if the synchronization is
not achieved.
Duration of the external reset depends on the time
required for crystal oscillator to stabilize and is depen-
dent on the crystal used. 2.5.10.2. Display
During the period when the RESETQ pin is held low, After the reset DAC will output a fix value as defined by
the PLL is initialized and it gets locked. The high going EN_DG_OUT, which is reset to 0. COR_BLA is reset
reset pulse then initiates a sequence which requires to a level indicating COR = 0 and BLank = 1.
one machine cycle (12 clock cycles) to initialize the
processor and all other registers and peripherals. Processor should initialize the display memory and set
the EN_DG_OUT (OCD_CTRL) bit.
2.5.4. Registers
The processor has separate Program and Data mem- Controller registers are also located in IRAM. Four
ory space. Memory spaces can be further classified banks of eight registers each occupy locations 0
as: through 31. Only one of these banks may be enabled
at a time through a two-bit field in the PSW.
– Program Memory
– Internal Data Memory 256 Bytes (CPU RAM)
Bit addressable RAM Area
– Internal Extended Data Memory (XRAM)
128-bit locations of the on-chip RAM are accessible
A 16-bit program counter and a dedicated banking through direct addressing.These bits reside in internal
logic provide the processor with 1 MByte addressing data RAM at byte locations 32 through 47.
capability (for ROM-less versions, up to 20 address
lines are available).
Stack
The program counter allows the user to execute calls
The stack can be located anywhere in the internal data
and branches to any location within the program mem-
RAM address space. The stack depth is limited only by
ory space.
the available internal data RAM, thanks to an 8-bit re-
locatable stack pointer. The stack is used for storing
Data pointers allows to move data to and from
the program counter during subroutine calls and may
Extended Data RAM.
also be used for passing parameters. Any byte of inter-
nal data RAM or special function registers accessible
There are no instructions that permit program execu-
through direct addressing can be pushed/popped. By
tion to move from the program memory space to any of
default Stack Pointer always has a reset value of 07H.
the data memory space.
The controller provides four additional address lines There are two modes for MOVC instructions. The
A[19:16]. These additional address lines are used to mode is selected by MM bit in MEX2.
access program and data memory space up to
1 MByte. The extended memory space is split into
MOVC with Current Bank
16 banks of 64 kByte each. The address lines A[19:16]
are therefore called bank address.
When MM = ‘0’, MOVC will access the current bank.
The CB[19:16] bits will appear on address lines
The additional address lines A[19:16] are delivered
A[19:16] during MOVC instructions.
with the same timing as normal address lines A[15:0].
The functionality for memory extension is provided by MOVC with Memory Bank
the Memory Management Unit (MMU) which includes
the four SFR registers: MEX1, MEX2, MEX3, and When MM = ‘1’, MOVC will access the memory bank.
MEXSP (see MEX1 on page 6-103). The MB[19] and MB[18:16] bits will appear on
address lines A[19:16] during MOVC instructions.
These registers can be read and written through MOV
instructions like any other SFR registers. Except for
CB bits in MEX1, which are read only, they can only be Note: MEX1 is not destroyed.
written by MMU. During normal operation, the user
must not write in the MEXSP.
The following instructions depend on memory exten- 2.6.5.3. Memory Banking for MOVX Instruction
sion settings:
There are two modes for MOVX instructions. The
– LJMP
mode is selected by MXM bit in MEX3.
– MOVC
– MOVX MOVX with Current Bank
– LCALL
When MXM = ‘0’, MOVX will access the current bank.
– ACALL The CB[19:16] bits will appear on address lines
A[19:16] during MOVX instructions.
– RET
– RETI MOVX with Data Memory Bank
After reset the bits for current bank CB[19:16] and Fig. 2–4 shows an assembler program run, performing
interrupt bank IB[19:16] are set to zero. This makes the following actions:
sure that the interrupt vector is taken from bank 0.
1. Start at bank 0 at 00000.
When the interrupt service routine is linked into 2. Set ISR-page to bank 2.
another bank, the software has to change the bits
3. Jump to bank 1 at address 25.
IB[19:16] to the appropriate bank address before
enabling interrupt. 4. Being interrupted to bank 2 ISR.
When an interrupt is serviced, the MEX1 register is 5. Call a subprogram at bank 2 address 43.
pushed onto extension stack. IB[19:16] is copied into 6. After return read data from bank 2.
CB[19:16] and NB[19:16] and the interrupt vector is
taken from bank IB[19:16]. The return from interrupt
(RETI) instruction restores MEX1 from extension stack 2.6.5.6. ROM and ROMless Version
and returns to CB[19:16].
The XROM pin determines the on-chip or off-chip
Memory Extension Stack ROM access.
For interrupts and calls the memory extension stack is If no internal ROM is to be used, then the XROM pin
required. The stack pointer MEXSP addresses (in ROMless version) should be driven low. The CPU
128byte on-chip extension stack. No indication for then accesses external ROM only. In ROM version this
stack full is provided. The programmer is responsible pin is internally pulled high, indicating no external
to read MEXSP to determine the status of the stack. ROM.
MOVC
The serial port is full duplex, meaning it can transmit 11 bits are transmitted (through TxD) or received
and receive simultaneously. It is also receive-buffered, (through RxD): a start bit (0), 8 data bits (LSB first), a
meaning it can commence reception of a second byte programmable 9th data bit, and a stop bit (1). On trans-
before a previously received byte has been read from mission, the 9th data bit (TB8 in SCON) can be
the receive register (however, if the first byte still hasn’t assigned the value of 0 or 1. Or, for example, the parity
been read by the time reception of the second byte is bit (P, in the PSW) could be moved into TB8. On
complete, one of the bytes will be lost). The serial port reception, the 9th data bit goes into RB8 in the special
receive and transmit registers are both accessed at function register SCON, while the stop bit is ignored.
special function register SBUF. Writing to SBUF loads The baud rate is programmable via SFR-Bit SMOD.
the transmit register, and reading SBUF accesses a
physically separate receive register.
2.8.1.4. Mode 3
The frequencies and baud rates depend on the inter-
nal system clock, used by the serial interface. 11 bits are transmitted (through TxD) or received
(through RxD): a start bit (0), 8 data bits (LSB first), a
programmable 9th data bit and a stop bit (1). In fact,
2.8.1. Modes mode 3 is the same as mode 2 in all respects except
the baud rate. The baud rate in mode 3 is variable.
The serial port can operate in 4 modes:
Two independent general purpose 16-bit timers/ Mode 1 is the same as mode 0, except that the timer/
counters are integrated for use in measuring time counter 0 register is being run with all 16 bits.
intervals, measuring pulse widths, counting events,
and causing periodic (repetitive) interrupts. Either can
Mode 2
be configured to operate as timer or event counter.
Mode 2 configures the timer/counter 0 register as an
In the ‘timer’ function, the registers TLx and/or THx
8-bit counter (TL0) with automatic reload. Overflow
(x = 0, 1) are incremented once every machine cycle.
from TL0 not only sets TF0, but also reloads TL0 with
Thus, one can think of it as counting machine cycles.
the contents of TH0, which is preset by software. The
reload leaves TH0 unchanged.
A machine cycle consists of 12 oscillator periods.
The use of the timer/counter is determined by two 8-bit Capture control timer is a 16 bit up counter, with spe-
registers, TMOD (timer mode) and TCON (timer con- cial features suited for easier infrared decoding by
trol). The input to the counter circuitry is from an exter- measuring the time interval between two successive
nal reference (for use as a counter), or from the on- trigger events. Trigger events can be positive, negative
chip oscillator (for use as a timer), depending on or both edges of a digital input signal (INT0 and INT1
whether TMOD's C/T-bit is set or cleared, respectively. on Port Mux). A built in Spike Suppression Unit (SSU)
When used as a time base, the on-chip oscillator fre- can be used for suppressing pulses with obviously too
quency is divided by twelve or six before being used small or too long time duration at the beginning of an
as the counter input. When TMOD's GATE bit is set expected telegram, thereby relieving the FW of pro-
(1), the external reference input (T1, T0) or the oscilla- cessing corrupted telegrams. This is especially useful
tor input is gated to the counter conditional upon a sec- in idle mode.
ond external input (INT0), (INT1) being high. When the
GATE bit is zero (0), the external reference, or oscilla-
tor input, is unconditionally enabled. In either case, the 2.10.1. Input Clock
normal interrupt function of INT0 and INT1 is not
affected by the counter's operation. If enabled, an Input clock is fCCT is same as system clock frequency
interrupt will occur when the input at INT0 or INT1 is divided by two. In normal mode system frequency is
low. The counters are enabled for incrementing when 40.5 MHz (fCCT = 20.25 MHz) and in slow down mode
TCON's TR1 and TR0 bits are set. When the counters (SD mode) 10.125 MHz (fCCT = 5.0625 MHz).
overflow, the TF1 and TF0 bits in TCON get set, and
interrupt requests are generated. PR prescaler bit when set divides the input clock fur-
ther by 2, PR1 divides further by 8.
The counter circuitry counts up to all 1's and then over-
flows to either 0's or the reload value. Upon overflow, Internal to the block change in SD mode is detected
TF1 or TF0 is set. When an instruction changes the and frequency is adjusted accordingly so that maxi-
timer's mode or alters its control bits, the actual mum time resolution of 15.73 ms or 251.66 ms is
change occurs at the end of the instruction's execu- achieved depending on Prescaler PR bits.
tion.
When counter is started (RUN), 16 bit reload value is Normal capture mode is started by setting the RUN bit
automatically loaded in the 16 bit counter. (0 --> 1) and PLG = 0, start = 0. Setting RUN bit will
reload the counter with reload value and reset the
overflow bit and counter will start to count.
Note: REL bit is irrelevant in case of RUN function.
Setting run bit resets the FIRST and OV bit. Upon event on the selected port pin, contents of the
counter are copied to the capture registers CRT_caph
and CRT_capl.
All the control bits PR, PLG, REL, RUN, RISE, FALL,
SEL, Start, Int_Src, SD can be changed anytime dur- In capture mode if REL bit is set counter is automati-
ing the operation, these changes take immediate effect cally reloaded upon event with the reload value and
there is no protected mode when counter is running. starts to count. If however REL bit is not set then
counter continues to count from the current value.
Mode START PLG Note: In this mode any event at selected port pin is
ignored. Upon overflow OV bit is set.
Normal capture mode 0 0
For each mode selection it is recommended to reset 2.10.3.8. Capture Mode with Spike Suppression at
the RUN bit (if it is not already at 0), set the appropri- the Start of a Telegram
ate mode bit and then start the counter by setting the
RUN bit. This mode is specially been implemented to prevent
false interrupt from being generated specially in idle
For each of the capture mode the event is captured mode while waiting for a new infrared telegram.
based on the CRTCON0 (RISE) and CRTCON0
(FALL).
This mode is entered by setting the START bit to 1 (edge triggered) and IRCON (EX1R or EX0R)
(PLG = 0). Software sets Start bit to indicate it is must be set to 1 and IRCON(EX1F or EX0F) must be
expecting a new telegram. Setting RUN bit will reload set to 0.
the counter with reload value and reset the overflow bit
and start the counting. For further information on interrupts please refer to
Section 2.3.
On occurrence of second capture event, counter value In idle mode CRT continues to function normally,
is captured and interrupt is triggered if the capture unless it has been explicitly shut off by PSAVEX
value exceeds the value in the Min_Cap register and (PERI) bit.
the OV bit is not set. First bit is reset. Counter will now
continue in the normal capture mode. Software may In power-down mode CRT is shut off.
reset the START bit if the capture value is a valid pulse
of a telegram.
2.10.5. Registers
If the pulse was invalid then software must stop the
counter and start again (Run bit first reset and then The RELL and RELH are the reload registers (SFR
SET) with start bit set to wait for a new telegram. address B7H and B9H), CAPH and CAPL are corre-
sponding capture registers (SFR address BAH and
If Capture value is less then or equal to MIN_CAP BBH). MIN_CAPL and MIN_CAPH (BC, BB) are Mini-
value or OV bit has been set, that is spike has been mum capture registers. CRTCON0 (E5H) and
detected and Interrupt is suppressed. OV bit would be CRTCON1 are the control registers.
reset counter would be reloaded with reload value
(regardless of REL bit).
RELOAD
RUN
PR
fcct
16 bit Ctr
Div 2
1 bit 1 bit
Ctr Ctr
SD
RISE
P3.3 RISE
FALL
P3.2 FALL CAPTURE
SEL
Int
IntSrc1
IntSrc0
Compare
Min_Cap
Spike Supression Unit
First Start
Int0 Int1
The Pulse Width Modulation unit consists of 6 quasi 2.11.4.1. 8-Bit PWM
8 bit and 2 quasi 14 bit PWM channels. PWM channels
are programmed by special function registers and The base frequency of a 8 bit resolution channel is
each individual channel can be enabled and disabled derived from the overflow of a six bit counter.
individually.
On every counter overflow, the enabled PWM lines
would be set to 1. Except in the case when compare
2.11.1. Reset Values value is set to zero.
All the PWM unit registers PWME, PWCOMP8 0-5, In case the comparator bits (7 … 2) are set to 1, the
PWCOMP14 0-1, PWMCOMPEXT14 0-1, PWML and high time of the base cycle is 63 clock cycles. In case
PWMH are by default reset to 00H. all the comparator bits (7 … 0) including the stretching
bits are set to 1, the high time of the full cycle (4 base
cycles) is 255 clock cycles.
2.11.2. Input Clock
The corresponding PWCOMP8x register determines
Input clock to PWMU FPWM is derived from fsys. fsys is the duty cycle of the channel. When the counter value
40.5 MHz in normal mode and in slowdown mode is equal to or greater than the compare value then the
10.125 MHz. In normal mode fsys is divided by 2 and in output channel is set to zero. The duty cycle can be
slow down mode it is directly fed to the PWMU. There- adjusted in steps of FPWM as mentioned in Table 2–
fore PWM unit is counting at 16.5 MHz in normal mode 14.
and 8.25 MHz in slow down mode. If PR bit
PCOMPEXT14 0 (bit 0) is set the then the counting In order to achieve the same resolution as 8-bit
frequency is half of that. counter, the high time is stretched periodically by one
clock cycle. Stretching cycle is determined based on
In addition PWM_direct bit makes it possible to run the two least significant bits in the corresponding
PWM counter at system frequency, ignoring PR bit and PWCOMP8x register.
the built in divide by 2 prescaler.
The relationship for stretching cycle can be seen in
To reduce electromagnetic radiation, the different Table 2–14 and Fig. 2–6.
PWM-channels are not switched on simultaneously
with the same counter value, but delayed each with
one clock cycle to the next channel: Table 2–14: Stretching cycle corresponding to register
PWCOMP8X
Channel 0: 0 clock cycles delayed, Channel 1: 1 clock
cycle delayed, …, Channel 5: 5 clock cycles, …, PWCOMP8X Cycle Stretched
PWM14_0: 6 clock cycles, PWM14_1: 7 clock cycles
delayed. Bit 1 1, 3
Bit 0 2
2.11.3. Port Pins
PWM Slow Down PWM_ PWM_ fsys Counting Rate Base Cycle Full Cycle
Resolution (SD) PR direct [MHz] [MHz] Time Time
[µs] [µs]
0 0 0 33.33 16.66 3.84 15.37
1 0 0 8.33 8.33 7.68 30.73
PWM unit uses a single 14 bit timer to generate sig- All control register for PWM are mapped in the SFR
nals for all 8 channels. Timer is mapped into SFR address space. Their address and bit description is
address space and hence is readable by the controller. given below.
Timer is enabled (running) if one of the PWM channels
is enabled in PWME. If all the channels are disabled
counter is stopped. Enabling one of the channels will Note: The controller can write any time into these reg-
reset the timer to 0 and start. isters. However registers PWM_COMP8_X,
PWM_CPMP14_X and PWM_CPMPEXT14_X,
including the bits PWM_direct and PWM_PR
Note: This reset is done for the first enabled channel. are double buffered and values from shadow
All other channels enabled later will drive the registers are only loaded into the main register
output from the current value of the counter. in case timer overflows or timer is stopped
(PWME = 00H) of 8 bit counter.
D _R
D _Ctr D _R
8
D _Rst
2
M M
D _Lw D_
r__/ It
12 8
D _I D _r
WDT_Rel D RE _7 D RE _6 D RE _5 D RE _4 D RE _3 D RE _2 D RE _1 D RE _0
2.12.1. Input Clock counter upon start, refresh or watchdog reset (if
WDT_nARST is set).
Input clock fwdt is same as CPU clock fsys divided by
12 (i.e. machine cycle) is fed to the WDT either as
divide-by-2 or divide-by-128. Divide factor is deter- Note: Counter registers are read only and cannot be
mined by WDT_In (WDT_ctrl) equal 0 and 1 respec- directly written by the controller.
tively. WDT_In has the same functionality in both
watch dog mode and timer mode.
2.12.3. Refresh
2.12.2. Starting WDT
Once WDT is started it cannot be stopped by software.
WDT can be started if the WDT unit is in the Watch
dog mode (WDT_Tmr = 0).
Note: While WDT is running any change to WDT_tmr
WDT is started by setting the bit WDT_Start in the bit would be ignored.
WDT_Ctrl register. Immediately after the start (1 clock
cycle) the reload value from WDT_Rel register is cop-
ied to the WDT_High. WDT_Low is always reset to 0 A refresh to the WDT is required before the counter
upon start. overflows. Refreshing WDT requires two instruction
sequence whereby first instruction sets WDT_Ref bit
Value can be written to WDT_Rel any time during nor- and the next instruction sets the WDT_Start bit. (For
mal controller operation. Value is only loaded to the example if there is NOP between these two instruc-
tions, refresh would be ignored). This double instruc-
tion refresh minimize the chances of unintentional Based on 33.33 MHz system clock minimum time
reset of the watchdog timer. Once set, WDT_Ref bit is period and maximum time period are as defined in
reset by the hardware after three machine cycles. Table 2–17.
If software fails to refresh the WDT before the counter Min. 33.33 0 FFH 184.3 µs
overflows after FFFFH, an internally generated watch- MHz
dog reset is entered.
Max. 33.33 1 00H 3.02 s
MHz
Watchdog timer reset differs only from the normal
reset in that during normal reset all the WDT relevant
bits in the three registers WDT_Rel, WDT_Refresh,
WDT_control are reset to 00H. Counter gets initialized 2.12.7. WDT as General Purpose Timer
to 0000H.
WDT counter can be used as a general purpose timer
In case of watchdog reset, WDT_Start and in timer mode and the associated load register can be
WDT_nARST are not reset. Bit WDT_Rst (read only) used either as load register or independent scratch
is set to indicate the source of the reset. In addition the register for the programmer. This is achieved by set-
WDT reset does not reset the PLL and clock genera- ting WDT_Tmr bit.
tor.
WDT_Tmr bit can only be set before starting the WDT
If the WDT_nARst bit is set then the values in the timer. Once watchdog timer is started it is not possible
WDT_Rel are retained after the WDT reset and to switch to general purpose timer mode.
counter starts with the same pre-scaler (WDT_in) and
reload configuration as before reset. If WDT_nARst is If WDT_Tmr bit is set then timer can be started using
not set then upon watchdog reset, WDT_Rel is reset to WTmr_Strt bit.
00h and WDT_In to 0.
When timer is started it
After the WDT reset counter starts again and must be – Resets the WTmr_OV overflow flag.
refreshed by the processor in order to avoid further
WDT resets. – Loads the preload value from WDT_Rel and starts
counting up.
Duration of the WDT reset is sufficient to ensure
proper reset sequence. Upon overflow WDT_Rst bit is not set neither is inter-
nal watchdog reset initiated. Overflow is indicated by
the bit WTmr_Ov (r/w). Overflow also sets the interrupt
2.12.5. Power-Down Mode source bit CISR0 (WTmr). Both of these bits are set by
hardware and must be cleared by software. If corre-
WDT is shut off during power down mode along with sponding watchdog timer interrupt enable IE1 (EWT)
the rest of the peripherals. bit is set then upon overflow interrupt is initiated.
In idle mode the WDT (in watchdog mode) is frozen, in After overflow timer starts to count from WDT_Rel. It is
timer mode it continues it’s operation.In power save possible for the processor to stop the timer by resetting
mode PSAVE (PERI) watchdog continues it’s opera- the WTmr_strt bit any time.
tion any write to this bit is ignored. If in timer mode the
timer can be frozen by setting this bit. While timer is running, WDT_Tmr bit cannot be tog-
gled any write to this bit is ignored. To reset the
WDT_Tmr bit, either timer is stopped (WTmr_Strt).
2.12.6. Time Period However, it is possible to stop the timer (WTmr_Strt)
and toggle (WDT_Tmr) with the same instruction.
The period between refreshing the watchdog timer and
the next overflow can be determined by the following
formula.
3 MHz RTC_INT
RTC_T14INT
RTCR Interrupt Subnode
RTCCON RTC Control Register RTCH RTC Timer Count Register, High Word
T14REL Timer T14 Reload Register RTCL RTC Timer Count Register, Low Word
T14 Timer T14 Count Register RTCISNC RTC Interrupt Sub Node Control Register
RTCRELH RTC Timer Reload Register, High Word
RTCRELL RTC Timer Reload Register, Low Word
UEA11139
Micronas
Port Input Output I2C
Addr Pin Port RXD TIM0 TIM1 INT0 INT1 INTX0 INTX1 ITUI CADC P-P O-D TXD PWM8 PWM14 DFVBL PWMV HSYNC VSYNC ITUO SCL SDA
FIELD CSYNC
0 P10 0 1 2 3 4 5 6 7 9 10 11 12.0 13.0 8 14
1 P11 0 1 2 3 4 5 6 7 9 10 11 12.1 13.1 8 14
2 P12 0 1 2 3 4 5 6 7 9 10 11 12.2 13.0 8 14
3 P13 0 1 2 3 4 5 6 7 9 10 11 12.3 13.1 8 14
4 P14 0 1 2 3 4 5 6 7 8.0 9 10 11 12.4 13.0 14
ADVANCE INFORMATION
12.12.2003; 6251-573-1-1AI
22 P32 0 1 2 3 4 5 6 7 9 10 11 12.0 13.0 8 14
Volume 6: Controller, OSD and Text Processing
SFR-Register
Addr Nam e Short Reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
92 Port Mux 1 PMUX1 0 Port Addr 0-11 Port Mode 0-15 Port Mode 15 enables read back of port pin configuration
4 Port Addr 12 = Config1 Ext. MSP DPS VSP 0=enable I2C slave, 1=disable I2C slave (disabling Ext. enables Test slave)
4 Port Addr 13 = Config2 Ext. Port TVT TVT slave 0=enable I2C master, 1=disable I2C master
0 Port Addr 14 = Config3 Test not used DPS VSP 1=reset I2C slave
93 Port Mux 2 PMUX2 0 Port Addr 16-27 Port Mode 0-15 Port Mode 15 enables read back of port pin configuration
VCT 49xyI, VCT 48xyI
6-49
VCT 49xyI, VCT 48xyI ADVANCE INFORMATION
2.16. Slicer and Acquisition controller. The microcontroller starts to process the
data in the VBI buffer. That means, the data is error
2.16.1. General Function checked by software and stored in the memory.
TVT provides a full digital data slicer including digital To improve the signal quality the slicer control logic
H/V-sync separation and digital sync processing. The generates horizontal and vertical windows in which the
acquisition interface is capable to process all known reception of the framing code is allowed. The framing
data services transmitted between line 6 to line 23 code can be programmed for each line individually, so
(TTX, VPS, CC, WSS). Digital signal processing algo- that in each line a different data service can be
rithms are applied to compensate various disturbance received. For TTX, CC and VPS the framing code is
mechanisms which exist on TV channels. These are hardwired. Additionally a sequence of 8 or 16 bits can
be programmed to be compared with the incoming
– Noise measurement and compensation.
data. In a special mode the framing code can be
– Frequency attenuation measurement and compen- bypassed, so that all incoming data are stored in the
sation. VBI buffer and are further processed by the microcon-
troller. All follow up acquisition tasks are performed by
– Group delay measurement and compensation.
the microcontroller, so in principle, the data of every
data service can be acquired.
The digital CVBS input signal is taken from the CVBS
frontend of VSP (see Section 2.2. on page 4-10). An
interpolation filter is used to adapt to the different clock
2.16.2. Slicer Architecture
frequency of the slicer.
The slicer is composed of three main blocks:
The sliced data is synchronized to the clock frequency
given by the clock-run-in (CRI) of the actual data ser- – data slicer
vice and to the framing code (FC) of the data stream.
– sync separation
After a successful framing code check the sliced data
is written to a programmable VBI buffer. After line 23 is – acquisition interface
received an interrupt request is delivered to the micro-
Acquisition Interface
to
Noise, FC-Check Memory
CVBS Frequency, D-PLL & Address
Group-Delay Decoder
Compensation Ser/Par
Converter
Noise,
Parameter
Frequency,
Buffer
Group-Delay
Measurement
2.16.2.1. Distortion Processing All of the above filters can be individually disabled,
forced or set to an automatic mode via control regis-
After A/D conversion the digital CVBS bit stream is ters.
applied to a circuitry which corrects for transmission
distortion. In order to apply the right algorithm for cor-
recting, a signal measurement is done in parallel. This 2.16.2.2. Data Separation
measurement device can detect the following distor-
tions. Parallel to the signal analysis and distortion compen-
sation a filter is calculating the slicing level. The slicing
level is the mean-value of the CRI. As the teletext is
2.16.2.1.1. Noise coded using the NRZ format, the slicing level can not
be calculated outside the CRI and is therefore frozen
The noise measurement unit incorporates two different after CRI. Using this slicing level the data is separated
algorithms. Both algorithm are using the value from the digital CVBS signal. The result is a stream of
between two equalizing pulses which corresponds to zeros and ones. In order to find the logical zeros and
the black level. As the black level is known to the sys- ones which have been transmitted, the data clock
tem a window is placed between two equalizing pulses needs to be recovered as well. Therefore a digital data
of line 4. The first algorithm compares successive PLL (D-PLL) is synchronized to the data clock during
samples inside a window placed in line 4. The differ- CRI using the transitions in the sliced data stream.
ence between this samples is measured and a flag is
set as soon as this difference over several TV lines is The operating frequency of the D-PLL is programma-
greater than a specified value. This algorithm is able to ble using the line parameter DINCR.
detect higher frequency noise. The second algorithm
measures the difference between the black value and DINCR = fdata * 218 / 40.5MHz
the actual sampled value inside this window. As soon
as this difference over several TV lines is greater than
a specified value a second flag is set. This algorithm is Table 2–19: Sampling rate for data services
sensitive against low frequency noise as it is known
from co-channel distortion. Both flags can be used to Service fdata [MHz] DINCR
optimize the correcting circuit characteristic in order to
achieve best reception performance. WST 6.9375 44904 AF68h
42 byte Data
Line 23
Slicer
4 byte Status
007Bh
42 byte Data
Line 7
4 byte Status
9 byte Parameter
0044h
42 byte Data
Line 6
001Ah
4 byte Status 0016h
9 byte Parameter
000Dh
4 byte Status 0009h
Field
0000h
NORM 0 1 2 3 4 5 6 7
FC_SEL 2 6 3 0 5 7 0 6
MLENGTH 0 0 2 1 7 7 7 0
ALENGTH 2 2 2 2 2 2 2 2
CLK_DIV 0 0 0 2 5 5 6 0
HS_WIN 2 2 2 2 2 2 2 2
EVCR BVCR
SDH
VLR Variable
Border Character Display Area Height
(25 rows)
EHCR
BHCR
HPR
H-Sync
The number of displayable pixels on the screen is Characters and their attributes which are displayed
defined by the pixel frequency (which is independent inside this area are programmable according to the
from horizontal frequency), the line period and number specifications of the display generator (see
of lines within a field. The screen is divided into three Section 2.17.). The size of that area is defined by
different regions. attributes inside the gobal display word (see
Section 2.17.5.). The start position of that area can be
shifted in horizontal and vertical direction by program-
2.17.2.1.1. Blacklevel Clamping Area ming the horizontal and vertical sync delay registers
(SDH and SDV).
During horizontal and vertical blacklevel clamping, the
black value (RGB = 000) is delivered on output side of Registers which allow setting up the screen and sync
TVT. Inside this area the BLANK pin and COR pin are parameters are given in Table 2–23.
set to the same values which are defined as transpar-
ency for subCLUT0 (see Section 2.17.5.8.). This area User has to take care of setting PCLK and SDH so that
is programmable in vertical direction (in terms of lines) SDH/PCLK is greater than 2 µs.
and in horizontal direction in terms of 40.5 MHz clock
cycles.
Note: Pixel clock (PCLK) must be appropriately
selected to the nearest value in the registers
2.17.2.1.2. Border Area PCLK 0 and PCLK 1.
Number of Lines / Field VLR 1 line 1024 lines 1 line 625 lines
Beginning Of Vertical Clamp Phase BVCR 1 line 1024 lines 1 line line 0
End Of Vertical Clamp Phase EVCR 1 line 1024 lines 1 line line 4
Table 2–24 serves as an example, the free program- 2.17.2.4. Vertical Field Detection
ming feature of pixel clock between 10 to 32 MHz
makes it possible to adjust and fine-tune the display as To realize the odd/even detection of a field next to VSU
per the application requirement. a second vertical setup time VSU2 is defined by the
VSU2 register bits. This horizontal delay is used to rec-
ognize the VSYNC to another time than it is recog-
Table 2–24: Pixel clock and display modes nized at VSU. The field detection is realized by detect-
ing if in between these two latching-points the VSync is
Character PCLK TCharacter display area rising or stable.
Display Mode
If VSYNC became active for both VSU and VSU2, an
40 × 25 12 MHz 40 µs odd field is detected. If VSYNC became active only for
VSU an even field is detected.
64 × 25 16 MHz 48 µs
40 × 25 24 MHz 20 µs H
................
64 × 25 32 MHz 24 µs
V
................
:
2.17.2.3. Sync Register Description
H
The clamp phase area has higher priority than the ................
screen background area or the character display area
V
and can be shifted independent from any other regis-
................
ter.
OSD RGB Fig. 2–15: Field detection with inverted VSU and
VSU2
H period
2 DISPOINT
2.17.4.1.2. Address Range from 768d to 1023d
+ F0H
Character Display Area The address range from 768d to 1023d is reserved to
+i∗3
address the DRCS characters. This range is split into
… … three parts for 1-bit DRCS, 2-bit DRCS and 4-bit
DRCS. The boundary between 1-bit DRCS and 2-bit
23 DISPOINT DRCS as well as the boundary between 2-bit DRCS
and 4-bit DRCS are defined by two boundary pointers
+ AC8H
inside the global display word (see Section 2.17.5.).
+i∗3
24 DISPOINT
+ B40H
+i∗3
6 CHAR.6
7 CHAR.7
0 CHAR.8 Italics
1 CHAR.9 Underline
2 FLASH Control of flash modes Section 2.17.4.2.
3 UH Upper half double height Section 2.17.4.3.
1
4 DH Double height Section 2.17.4.3.
5 DW Double width Section 2.17.4.4.
6 BOX Control for Boxes Section 2.17.5.7.
7 CLUT.0 subCLUT subCLUT subCLUT Section 2.17.5.8.
select select select
0 CLUT.1
1 CLUT.2 Char2x2
2 FG.0 Foreground color vector Section 2.17.5.8.1.
3 FG.1
2
4 FG.2
5 BG.0 Background color vector Section 2.17.5.8.1.
Section 2.17.4.2.
6 BG.1
7 BG.2
2.17.4.2. Flash
Table 2–28: Character display depending on DH and
Bit FLASH inside character display word (CDW; see UH bit settings
also Section 2.17.4.) is used to enable Flash for a
character. DH UH Display
0 X
Table 2–27: FLASH bit
FLASH Description
1 1
0 steady (flash disabled)
1 flash
1 0
For flash rate control refere to the global attribute 2.17.4.4. Character Individual Double Width
"FLRATE" in the global display word (see
Section 2.17.5.6.). Bit DW (double width) marks the left half of a character
with double width. The character to its right will be
overwritten by the right half.
2.17.4.2.1. Flash for ROM and 1-Bit DRCS Charac-
ters If the DW bit of the following character (here the ‘X’) is
also set to ‘1’; the right half of the ‘A’ is overwritten by
For ROM characters and 1-bit DRCS characters the left half of the ‘X’.
enabled flash causes the foreground pixels to alternate
between the foreground and background color vector. If a character is displayed in double width mode the
attribute settings of the left character position are used
to display the whole character.
2.17.4.2.2. Flash for 2-Bit and 4-Bit DRCS Charac-
ters
Table 2–29: Character display depending on DW bit
For these characters enabled flash causes the DRCS settings
pixels to alternate between the 2-bit/ 4-bit color vector
and the background color vector which is defined by DW Display
the BG attribute inside the character display word
(CDW). Char ’A’ Char ’X’
0 0
2.17.4.3. Character Individual Double Height
0 1
9 4 FLRATE.1
5 HDWCLUTCOR Defines the level of COR for the colors of the hard- Section 2.17.5.8.
wired CLUT.
6 HDWCLUTBLANK Defines the level of BLANK for the colors of the Section 2.17.5.8.
hardwired CLUT.
7 --- Reserved.
The selection of ROM or DRCS depends on the follow- 768d 847d 1-bit DRCS area
ing settings in the GDW:
848d 991d 2-bit DRCS area
Table 2–31: Character access modes 928d 1023d 4-bit DRCS area
CHAAC Description
Table 2–34: Example2: DRCSB1=5, DRCSB2=5
0 Normal mode:
Address range 0d - 767d is used to Character Address Description
access ROM characters.
From To
1 Enhanced mode:
768d 847d 1-bit DRCS area
Address range 0d - 767d is used to
access 1-bit DRCS characters. 848d 1023d 4-bit DRCS area
… …
… …
Table 2–38: Character display position (horizontal)
15 48 columns setting
3 Horizontal shift of 3
2.17.5.3. Cursor
… …
The 2-bit color vector matrix of the cursor is stored in
11 Horizontal shift of 11
the XRAM. A programmable pointer is used, so that
the matrix can be stored at any location inside the >11 not allowed
XRAM (see also Section 2.17.7.3.).
Table 2–39: Character display position (vertical) The cursor is handled as a layer above the character
setting, continued display area. Pixels of the 2-bit cursor bitplane which
are set to ‘00’ are transparent to the OSD/Video layer
below. So the cursor can be transparent to the OSD (in
CURVER Description
case of no transparency of OSD) or to video (in case of
14 Vertical shift of 14 transparency of OSD).
10d
pixel-shift:
Table 2–40: Cursor position (horizontal) setting horizontal: 7d
vertical: 6d 11d
POSHOR Description
character-row/column:
0 Horizontal character column 0 horizontal: 5d
vertical: 10d
1 Horizontal character column 1
Fig. 2–16: Positioning of HW Cursor
… …
62 Horizontal character column 62 One out of 8 subCLUTs is used to display the cursor.
The parameter CURCLUT is used to select the sub-
63 Horizontal character column 63 CLUT which is used for color look up of the cursor.
POSVER Description
2.17.5.4. Border Color
0 Vertical character row 0
Next to the character display area in which the charac-
1 Vertical character row 1 ters are displayed there is a area which is surrounding
the character display area. The visibility of this border
2 Vertical character row 2 area depends on the width and height of the character
display area. The global attribute BRDCOL in the glo-
3 Vertical character row 3 bal display word GDW is used to define the color vec-
tor of this border (see Section 2.17.5.8.).
… …
In double height mode user may want to start the pro- Table 2–42: Full screen double height, continued
cessing of the display at row 12 and not at row 0. To
decide this, three bits are used as a global attribute.
GDDH Display Area
FLRATE Description
2.17.5.7. Transparency of Boxes Transparency definition for characters for which BOX
is set to 1 and which are using subCLUT0:
For characters which are using subCLUT0 the trans-
parency which is defined for the whole CLUT (see
Section 2.17.5.8.) can be overruled for foreground or Table 2–45: BOX1 transparency setting
background pixels. There are two different definitions
for two box areas to define this overruling. Which of GLBT_ Description
these two box transparencies is used, is selected char- BOX1
acter individual inside the bit BOX in CDW (see
Section 2.17.4.). 0 or 4 Box transparency is disabled for BOX1.
Transparency definition for characters for BOX0: 1 Box transparency is enabled for BOX1 for
foreground pixels of ROM characters.
Table 2–44: BOX0 transparency setting 2 Box transparency is enabled for BOX1 for
foreground pixels of 1-bit DRCS charac-
ters.
GLBT_ Description
BOX0 3 Box transparency is enabled for BOX1 for
foreground pixels of ROM and 1-bit DRCS
0 or 4 Box transparency is disabled for BOX0.
characters.
For all pixels the global defined transpar-
ency of subCLUT0 is used. 5 Box transparency is enabled for BOX1 for
background pixels of ROM characters.
1 Box transparency is enabled for BOX0 for
foreground pixels of ROM characters. 6 Box transparency is enabled for BOX1 for
background pixels of 1-bit DRCS charac-
2 Box transparency is enabled for BOX0 for ters.
foreground pixels of 1-bit DRCS charac-
ters. 7 Box transparency is enabled for BOX1 for
background pixels of ROM and 1-bit DRCS
3 Box transparency is enabled for BOX0 for characters.
foreground pixels of ROM and 1-bit DRCS
characters.
Box0 transparency levels of COR and BLANK are
5 Box transparency is enabled for BOX0 for
overruled by the global attributes COR_BOX0 and
background pixels of ROM characters.
BLA_BOX0.
6 Box transparency is enabled for BOX0 for
background pixels of 1-bit DRCS charac- Box1 transparency levels of COR and BLANK coming
ters. from subCLUT0 are overruled by the global attributes
COR_BOX1 and BLA_BOX1.
7 Box transparency is enabled for BOX0 for
background pixels of ROM and 1-bit DRCS The cursor (see Section 2.17.5.3.) is not affected by
characters. the transparency bits.
The RGB values of the CLUT entries from 16 to 63 are 3 subCLUT3 subCLUT3
programmable. The RGB values of the CLUT are
4 subCLUT4 subCLUT0
organized in the TVT XRAM in an incremental serial
order. CLUT locations inside XRAM which are not 5 subCLUT5 subCLUT1
used for OSD can be used for any other storage pur-
poses. 6 subCLUT6 subCLUT2
CLUT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Within a ROM or 1-bit DRCS character matrix a 1-bit
Addr. background/foreground information is available for
each pixel. This 1-bit information selects either the
+0 Green Blue foreground “FG” or the background “BG” attribute
inside the character display word CDW to address 1
+1 reserved COR Blank Red
out of 8 subCLUT entries.
The CLUT is divided in 8 subCLUTs with 8 entries for 2.17.5.8.2. CLUT Access for 2-Bit DRCS Characters
1-bit DRCS and ROM characters. For 2-bit DRCS
characters the CLUT is divided in 8 subCLUTs with 4 Within a 2-bit DRCS character matrix a 2-bit color
entries. For 4-bit DRCS characters the CLUT is information is available for each pixel. This 2-bit infor-
divided in 4 subCLUTs with 16 entries. mation selects 1 out of 4 subCLUT entries.
CLUT CLUT subCLUT No for ROM subCLUT No for subCLUT No for 2-Bit subCLUT No for 4-Bit CLUT Data
Address Entry and 1-Bit DRCS Cursor DRCS Character DRCS Character
Offset to Character
CLUTPOINT
No. Entry No. Entry No. Entry No. Entry R G B
00H 16 0 0 0 0 programmable
(see Table 2–46)
02H 17 1 1 1 1
0 0
04H 18 2 2 2 2
06H 19 3 3 3 3
2
08H 20 4 0 0 4
0AH 21 5 1 1 5
1 1
0CH 22 6 2 2 6
0EH 23 7 3 3 7
1
10H 24 0 0 0 8
12H 25 1 1 1 9
2 2
14H 26 2 2 2 10
16H 27 3 3 3 11
3
18H 28 4 0 0 12
1AH 29 5 1 1 13
3 3
1CH 30 6 2 2 14
1EH 31 7 3 3 15
CLUT CLUT subCLUT No for ROM subCLUT No for subCLUT No for 2-Bit subCLUT No for 4-Bit CLUT Data
Address Entry and 1-Bit DRCS Cursor DRCS Character DRCS Character
Offset to Character
CLUTPOINT
No. Entry No. Entry No. Entry No. Entry R G B
20H 32 0 0 0 0
22H 33 1 1 1 1
4 4
24H 34 2 2 2 2
26H 35 3 3 3 3
4
28H 36 4 0 0 4
2AH 37 5 1 1 5
5 5
2CH 38 6 2 2 6
2EH 39 7 3 3 7
2
30H 40 0 0 0 8
32H 41 1 1 1 9
6 6
34H 42 2 2 2 10
36H 43 3 3 3 11
5
38H 44 4 0 0 12
3AH 45 5 1 1 13
7 7
3CH 46 6 2 2 14
3EH 47 7 3 3 15
40H 48 0 0 0 0
42H 49 1 1 1 1
not available not available
44H 50 2 2 2 2
46H 51 3 3 3 3
6
48H 52 4 0 0 4
4AH 53 5 1 1 5
not available not available
4CH 54 6 2 2 6
4EH 55 7 3 3 7
3
50H 56 0 0 0 8
52H 57 1 1 1 9
not available not available
54H 58 2 2 2 10
56H 59 3 3 3 11
7
58H 60 4 0 0 12
5AH 61 5 1 1 13
not available not available
5CH 62 6 2 2 14
5EH 63 7 3 3 15
The character matrix of DRCS characters can be If shadowing is enabled the ROM characters and 1-bit
adjusted in vertical direction from 9 lines up to 16 lines. DRCS characters of the characters are displayed by
In horizontal direction the character matrix is fixed to west shadow or east shadow. The color vector of the
12 pixels. shadow is defined by software. The shadow color vec-
tor has a width of 6 bit.
The character matrix of the ROM characters can also
be adjusted in vertical direction from 9 lines up to 16 The shadow feature is enabled by the bit SHEN and
lines. In horizontal direction the ROM character matrix can be set into 2 modes by the bit SHEAWE.
is fixed to 12 pixels:
1 10 lines
Table 2–51: Shadow options
2 11 lines
6 15 lines
shadowed pixel
background pixel
foreground pixel
This feature is useful for TV-devices in which a frame The following examples are proceeded on the
consists of 1 field with 625 lines instead of 2 fields with assumption that a height of 11 character lines is
312.5 lines each. selected. The memory organization behaves the same
for any other count of lines.
For this TV-fields the RGB-output lines can be
repeated twice by enabling the progressive scan fea- Each character starts at a new byte address. This
ture. This repetition of lines in vertical direction is only causes, that for odd heights nibbles may be left free.
processed for lines inside the character display area.
PIXEL10
PIXEL11
Table 2–52: Progressive scan support
PIXEL0
PIXEL7
PIXEL8
PIXEL4
PIXEL6
PIXEL9
PIXEL1
PIXEL2
PIXEL3
PIXEL5
Progress Description LINE0
Char Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1 DRC1POINT LINE 0
+ 00H PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5 PIXEL 6 PIXEL 7
DRC1POINT LINE 1
+ 02H PIXEL 4 PIXEL 5 PIXEL 6 PIXEL 7 PIXEL 8 PIXEL 9 PIXEL 10 PIXEL 11
… …
2 DRC1POINT LINE 0
+ 11H PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3 PIXEL 4 PIXEL 5 PIXEL 6 PIXEL 7
… … …
Char Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1 DRC2POINT LINE 0
+ 00H PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3
DRC2POINT LINE 0
+ 01H PIXEL 4 PIXEL 5 PIXEL 6 PIXEL 7
DRC2POINT LINE 0
+ 02H PIXEL 8 PIXEL 9 PIXEL 10 PIXEL 11
… …
DRC2POINT LINE 10
+ 20H PIXEL 8 PIXEL 9 PIXEL 10 PIXEL 11
Char Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
2 DRC2POINT LINE 0
+ 21H PIXEL 0 PIXEL 1 PIXEL 2 PIXEL 3
… … …
Char Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
1 DRC4POINT LINE 0
+ 00H PIXEL 0 PIXEL 1
DRC4POINT LINE 0
+ 01H PIXEL 2 PIXEL 3
DRC4POINT LINE 0
+ 02H PIXEL 4 PIXEL 5
… …
DRC4POINT LINE 10
+ 41H PIXEL 10 PIXEL 11
2 DRC4POINT LINE 0
+ 42H PIXEL 0 PIXEL 1
… … …
2.17.7. Memory Organization one hand and that the definition is optimized so that no
memory is wasted, on the other hand. The length of
The memory organization concept of the OSD is the global display word is fixed to 10 byte and the
based on a flexible pointer concept. All display mem- length of the CLUT is fixed to 2 × 48 byte. The length
ory registers reside in the internal XRAM only. of all the other areas depend on the OSD requirements
(see Section 2.17.7.1. to Section 2.17.7.4.).
6000h 24k Char ROM Each pointer in the pointer array has a width of 16 bits
and uses 2 bytes inside the XRAM. They are stored
low byte first.
User Data
6 = low byte ROMPOINT
7 = high byte
VBI Buffer
0000h 0000h
Fig. 2–19: Memory Organization of On-Screen Display 2.17.7.1. Character Display Area
These 2 pointer arrays in XRAM contain pointers to the The array is sorted in a incremental serial order com-
start addresses of the following memory areas: ing from the top left character throughout the bottom
right character of the character display area. For fur-
– Start address of character display area memory ther information see Section 2.17.3..
– Start address of CLUT
The length of this display memory area depends on
– Start address of 1-bit DRCS character matrices the parameter settings of DISALH.
– Start address of 2-bit DRCS character matrices
– Start address of 4-bit DRCS character matrices
– Start address of 1-bit ROM character matrices
– Start address of global display word / cursor matrix
3.1. SFR Register Block Name Page Name Page Name Page
Index
CNT0 102 EXX1R 107 MASTEN 105
CNT1 102 F0 103 MASTER 105
CY 103 F1 104 MB[18:16] 103
Name Page
DEVID[6:0] 105 FALL 110 MB[19] 103
CADC 112
DHS 109 FAST 105 MINH[7:0] 110
CRT 110
DIS_BLANK 116 FIRST 110 MINL[7:0] 110
DISPLAY 113
DIS_COR 116 FIRSTB 105 MM 103
I2C 104
DIS_FILTER 105 FIT_STVAL 116 MSP 109
INTERRUPT 106
DISP 113 FULL 105 MX[19] 103
MEMORY 116
DPH[7:0] 101 G0P0 108 MX[19] 103
MICRO 101
DPL[7:0] 101 G0P1 107 MXM 103
PATCH 106
DPSEL[2:0] 101 G1P0 108 MXSP[7:0] 103
PORT 101
DVS 109 G1P1 107 NB[19:16] 103
PWM 111
E24 107 G2P0 108 NMIEN 108
RESET 112
EAD 106 G2P1 107 NOMAP 116
RTC 104
EADW 106 G3P0 108 ODD_EVEN 115
SLICER 113
EAH 106 G3P1 107 OV 103
UART 104
EAL 106 G4P0 108 OVFLOW 110
WATCHDOG 109
EAV 106 G4P1 107 P 104
ECC 106 G5P0 108 P1[7:0] 101
3.2. SFR Register Index EDH 106 G5P1 107 P2[7:0] 101
EDV 106 GATE0 102 P3[7:0] 101
EHCR[7:0] 114 GATE1 102 P4[7:0] 101
Name Page EI2C 107 GF0 102 PATAB[3:0] 106
A[7:0] 104 EMPTY 105 GF1 102 PATAH[7:0] 106
AC 103 EMSP 106 HP 114 PATAL[7:0] 106
ACQ_STA 113 EN_DG_OUT 116 HPR0[7:0] 115 PATCH 116
ACQON 113 EN_FIT 116 HPR1[3:0] 115 PATD[7:0] 106
ADC 108 EN_IT 116 I2C 109 PATEN 106
ADW 109 EN_LD_GDW 116 I2CDATA[7:0] 105 PATSUB[3:0] 106
ADWULE 112 EN_SS 116 IB[19:16] 103 PC140[7:0] 111
AHS 109 EPW 106 IDLE 102 PC141[7:0] 111
AVS 108 ERTC 106 IDLS 101 PC80[7:0] 111
B[7:0] 104 ESS 107 IE0 102 PC81[7:0] 111
BHCR[7:0] 114 ET0 106 IE1 102 PC82[7:0] 111
BIT[7:0] 104 ET1 106 IEX0 109 PC83[7:0] 111
BOTTOM 116 EU 106 IEX1 109 PC84[7:0] 111
BUSERROR 105 EVCR0[7:0] 115 IGNACK 105 PC85[7:0] 111
BVCR0[7:0] 115 EVCR1[1:0] 115 INT 114 PCLK0[7:0] 113
BVCR1[1:0] 114 EWT 106 INTEN 105 PCLK1[3:0] 113
CADC 113 EX0 106 INTSRC0 116 PCX140[7:2] 111
CADC0[7:0] 112 EX0F 107 INTSRC1 116 PCX141[7:2] 111
CADC1[7:0] 112 EX0R 107 ISP 116 PDE 102
CADC2[7:0] 112 EX1 106 IT0 102 PDOWN 105
CADC3[7:0] 112 EX1F 107 IT1 102 PDS 101
CAPH[7:0] 110 EX1R 107 L24 108 PLG 110
CAPL[7:0] 110 EXX0 106 LASTB 104 PMUX1[7:0] 101
CAPTION_DIS 104 EXX0F 107 LOSS 105 PMUX2[7:0] 101
CB[19:16] 103 EXX0R 107 M0[1:0] 103 POINT0_0[7:0] 115
CC 109 EXX1 106 M1[1:0] 102 POINT0_1[7:0] 115
CLK_SRC 113 EXX1F 107 MAST 114 POINT1_0[7:0] 115
Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication and
to make changes to its content, at any time, without obligation to notify
any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-573-5-1AI retrieval system, or transmitted without the express written consent of
Micronas GmbH.
Video-Controller-Text-IF-Audio IC Family
Micronas GmbH All information and data contained in this data sheet are without any
Hans-Bunte-Strasse 19 commitment, are not to be considered as an offer for conclusion of a
D-79108 Freiburg (Germany) contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
P.O. Box 840 and delivery are exclusively subject to our respective order confirmation
D-79008 Freiburg (Germany) form; the same applies to orders based on development samples deliv-
Tel. +49-761-517-0 ered. By this publication, Micronas GmbH does not assume responsibil-
Fax +49-761-517-2174 ity for patent infringements or other rights of third parties which may
E-mail: docservice@micronas.com result from its use.
Internet: www.micronas.com Further, Micronas GmbH reserves the right to revise this publication
and to make changes to its content, at any time, without obligation to
notify any person or entity of such revisions or changes.
Printed in Germany No part of this publication may be reproduced, photocopied, stored on a
Order No. 6251-573-1AI retrieval system, or transmitted without the express written consent of
Micronas GmbH.