MEDISON SA-9900 Service Manual PDF

SonoAce 9900 Medison Co.Ltd.,
Contents
Table of Contents
Chapter 1 BASIC INFORAMTION
1. Pre-installation
1.1 Inspection
1.2 Unpacking instructions
2. Instruction
2.1 Notes to users
2.2 Safety precautions
2.2.1 Physical safety precautions
2.2.2 Mechanical safety precautions
2.2.3 Electrical safety precaution
2.2.4 Safety symbols
2.3 Maintenance and protection
2.3.1 Cleaning
2.3.2 Cleaning for general purpose probe
2.3.3 Using probe correctly
2.3.4 Protect circuit : fuse replacement
2.4 System components
3. Installation Guide for SA9900
3.1 System location and check-out
3.2 Making the connections
3.2.1 Install & connecting the monitor
3.2.2 Connecting the probe
3.2.3 Connecting external system
3.2.4 Connecting the AC power cords
3.2.5 Installing hdd
Preventive Maintenance Procedure for SA9900
Sa9900 preventive maintenance check list
Chapter 2 Description of System
1.DBF
1.1 Board specification
1.2.Block diagram
1.3 Signal definition
1.4 Details
1.4.1 Tx pulser
Service Manual Published by SERTECH

Table of Contents
1.4.2 Receive Channel

1.4.3 Switch(RX) & Limiter
1.4.4 TGC amp & Amplifier
1.4.5 LPF
1.4.6 TGC curve
1.4.7 A/D Block
1.4.8 TX Pulse
1.5 Timing Chart
1.6 Wave Form
2.CW BOARD
2.1 Board Specification
2.2.BLOCK DIAGRAM
2.3 Signal Definition
2.4 Details
2.4.1 LPF & HPF
2.4.2 CLOCK DRIVE(61.6Mhz PART)
2.4.3 TX POWER CONTROL
2.4.4 HV MUX CONTROL
2.4.5 TX FOCUSING
2.4.5 PULSER
2.4.6 PRE-AMP
2.4.7 RX SWITCHING (SELECT)
2.4.8 POST MIXER FILTER/AMPLITER
2.4.9 MIXER DRIVE
2.4.10 MIXERS
2.4.11 BAND PASS FILTER
2.4.12 ADC(ANALOG DIGITAL CONVERT)
2.5 Timing Chart
2.6 Wave Form
3.DSC BOARD
3.2.BLOCK DIAGRAM
3.3.1 Pin Discription

Table of Contents
3.4 Details
3.4.1 Input Controller
3.4.2 Azimuth/Pixel/Frame Interpolator
3.4.3 FI MUX
3.4.4 Memory Controller Part
3.4.5 DSC DSP
3.4.6 RTC DSP
3.4.7 RTC FPGA
3.5 Timing Chart
3.6 WAVE FORM
4.DSP BOARD
4.2 BLOCK DIAGRAM
4.4 Details
4.4.1 MOTHER BUFFER
4.4.2 PRE-MID FGGA
4.4.3 MGA015A
4.4.4 MGA016 PIN DIARAM & BLOCK DIAGRAM
4.4.5 DOPPLER PART -
4.5 Timing Chart
4.6 Wave Form
5.VIDEO MANAGER
5.1Board Specification
5.2 BLOCK DIAGRAM
5.4 Details
5.4.1 VIDEO & IMAGE PART
5.4.2 VCR INPUT
5.4.3 SCAN DOUBLER (AL251)
5.4.4 B,C,D,ECG INPUT (DSC INPUT)
5.4.5 IMAGE GRABBER
5.4.6 FIELD MEMORY
5.4.7 VIDEO KEY
5.4.8 NON-INTERLACE DAC

Table of Contents
5.4.9 Interlace Output

5.4.10 SOUND I/O
5.5 Timing Chart
5.6 Wave Form
6.KEY MATRIX BOARD
7.KEY INTERFACE BOARD
7.1 BLOCK DIAGRAM
8.MOTHER BOARD
9.PC BOARD
9.1 ROM BIOS setting
9.1.1 Enter in ROM BIOS
9.1.2 STANDARD CMOS SETUP setting
9.1.3 BIOS FEATURES SETUP setting
9.1.4 CHIP FEATURES SETUP setting
9.1.5 POWER MANAGEMENT SET UP setting
9.1.6 PNP/PCI CONFIGURATION setting
9.1.7 INTEGRATED PERIPHERALS setting
9.2 I/O Map PORT ADDRESS MAP
9.3 INTERRUPT CONTROLLER
10.PSA(PROBE SELECT ASSEMBLE)
10.1 General Description
10.2 Cannon Connector
10.3 Probe Switching
11.REAR PLATE
12 .REVISION HISTORY
12.1 H/W_S/W COMPATIBLE MATRIX
12.2 Revision History Each Board
12.2.1 DBF BOARD
12.2.2 CW BOARD
12.2.3 DSC BOARD
12.2.4 DSP BOARD
12.2.5 ECG BOARD
12.2.6 KEY INTERFACE BOARD
12.2.7 K/M BOARD

Table of Contents
12.2.8 MOTHER BOARD

12.2.9 PC BOARD
12.2.10 PSA BOARD
12.2.11 REAR L BOARD
12.2.12 REAR M BOARD
12.2.13 REAR R BOARD
12.2.14 UPDOWN B/D
12.2.15 V/M B/D
12.2.16 SOFTWARE HISTORY
Chapter 3 SUB-APPARATUS
1.POWER SPECIFICATION
1.1 GENERAL
1.2 FUNCTION
1.3 ELECTRONIC CHARACTERISTICS
1.3.1 INPUT CHARACTERISTICS
1.3.2 OUT PUT CHARACTERISTICS
1.3.3 SAFETY
1.3.4 ENVIRONMENT
1.3.5 MISC.
1.4 CIRCUIT DESCRIPTION
1.4.1 Input Circuit
1.4.2 AC Output Circuit
1.4.3 DC Output Circuit
1.4.4 AC OFF TIME DELAY CIRCUIT(OFF2000)
1.4.5 PROTECTION CIRCUIT
1.4.6 SA9900 CIRCUIT EXPLANATION 1
2. MOD
2.1 MCD3130AP : Magneto-Optical Drive characteristics
2.2 MOD SPEC
2.3 MOD JUMPER SETTING
3. CR R/W.
3.1 CD R/W Driver characteristics
3.2 CD R/W using recommendation disk
3.3 CD R/W SPEC.

Table of Contents
4.HDD
4.1 HDD SPEC(.FIREBALL LCT10-20.4GBYTE)
4.2 DISK DRIVE ORGANIZATION
4.3 CAPACITY SPEC
4.4 POWER SPEC.
4.5 JUMPER SETTING
5. MONITOR
5.1 CONTROLS & FUNCTION
5.1.1 Information About the Timing (Resolution) Setting
5.1.2 Adjustment in Main Menu
5.1.3 Description of Each Menu
5.2. ADVANCED FUNCTIONS.
5.3 COLOR MANAGER
5.4 USER MODE SUB MENU
5.5 OSD MANAGER MENU
5.6 TECHNICAL DATA
5.7 TROUBLE SHOOTING
5.7.1 No Picture (No Self Test Pattern)
5.7.2 One Horizontal Bar
5.7.3 Power Supply Problem
5.7.4 Power Saving Problem
5.7.5 No Picture (Power SW NG)
Chapter 4 DIAGRAMS
1. Assembling Diagrams
2 Cable Diagram
Chapter 5 ADITIONAL INFORMATION
1.Specification
1.1 Technical Specification
1.2 Measurement Range and Accuracy
1.2.1 B-Mode Range and Accuracy
1.2.2 M-Mode Range and Accuracy
1.2.3 DOPPLER Mode Range and Accuracy
1.3 Safety Standardization
2.SA990 Compatibility Matrix

SonoAce 9900 Section 1-1. Pre-Installation
1. PRE-INSTALLATION
1.1 INSPECTION
Upon arrival, inventory the shipment with the carrier’s driver.
§ Carefully inspect the packing material for obvious signs of damage such as crushed, punctured,
torn, broken, wet or rattling packages.
§ If damage is not evident, sign and stamp a bill of lading “condition of contents unknown –subject to
inspection.”
§ If damage is evident, contact your Purchasing Department for action, have the carrier’s driver
indicate the damage on the damage on the freight bill, and sign all copies of the bill.
During formal inspection, you should :
§ Open all packages within 15 days of receipt for a complete inspection of the consignment.
§ Report concealed damage to the carrier within 15 days of receipt or the carrier may not
accept liability.
1.2 UNPACKING INSTRUCTIONS
The SA9900 Ultrasound system and its accessories are shipped in two cartons.
To unpack the unit :
2-1 To unpack the 15” VGA monitor

§ Remove or cut the binder tape.
§ Carefully lift the 15” VGA monitor and place it on a flat, secure surface.
§ Take out the accessory and set it in a safe place.
2-2 To unpack the unit

§ Remove or cut the binder tape.
§ Carefully lift the main console, Probe box from the carton and place it on a flat, secure surface.
§ Take out the accessory kit and set it in a safe place.
§ Save all shipping materials in case the unit case the unit requires additional transportation.
☞ NOTE
MEDISON or local distributor will make available on request circuit diagrams, componets part
list, descriptions, calibration instructions or other information which assist your appropriately
qualified technical personnel to repair those parts of equipment which are designed by
Medison as repairable
Service Manual Published by Customer Service Department

SonoAce 9900 Section 1-2. Instruction
2. INSTRUCTION
2.1 NOTES TO USERS
Thank you for purchasing the SA9900 Ultrasound system. To ensure safe operation and long
term performance stability, it is essential that you fully understand the functions, operation and
maintenance instructions by reading this manual before operating your equipment.
n Incorrect operation, or failure of the user to maintain the equipment relieves the manufacturer or
his agent of the system's non-compliance with specifications or of responsibility for any damage or
injury.
n The following conventions are used throughout the manual to denote information of special
emphasis.
WARNING !
“Warning” is used to indicate the presence of a hazard which can cause
severe personal injury, death, or substantial property damage if the
warning is ignored.
CAUTION !
“Caution” is used to indicate the presence of a hazard which will or can
cause minor personal injury or property damage if the warnings ignored.
NOTE
“Note” is used to notify the user of installation, operation, or maintenance
information which is important but not hazard-related. Hazard warnings
should never be included under the Note signal word.

2.2 SAFETY PRECAUTIONS
2.2.1 Physical Safety Precautions
① The following is a public statement by the one of United States Ultrasound Association, AIUM, on
the safety of ultrasound diagnosis.
② Ultrasound has been in use since the 1950's. AIUM declares the clinical safety of ultrasound
scanning and acknowledges its effectiveness as a type medical equipment and its possible use for
diagnosis of pregnant women.
③ There has been no case which shows cause of any physical damage to either patient or user
during properly performed diagnosis with an ultrasound scanner. Although it might be possible that
unknown effects of ultrasound may come to light in the future, so far the benefits far outweigh any
unproved danger.
④ Theoretically, there are two possible ways that ultrasound could have negative affect on the
human body. One is the heat generated by ultrasound as it passes through the human body.
Doppler produces the most heat, and is followed by color and B-mode imaging. However, even in
the case of Doppler the amount of heat is so minor that there is no equipment which can measure
it.
⑤ The other one is the possible formation of a cavity by the ultrasound. However, there has been no
clear evidence that this can actually occur in the human body.
⑥ In conclusion, no negative biological effects of ultrasound have been proven thus far.
2.2.2 Mechanical Safety Precautions
☞ WARNING !
The system is quite heavy, therefore be careful when moving the equipment, especially going
up and down stairs. Normally, as many as four adults are required to move the system
manually on stairs. In case of monitor, it is a possible to separate from the system.
Therefore you can move after disconnecting as necessity requires.
① Equipment brake system

There is a break in the front wheel of the system. To move the system, lock or unlock the break by
foot. If you want to move the system, you should unlock the break by your foot.
② Moving the equipment

The wheels are designed mainly for back and forth movement. Turning around can be done
by repeated movements of back and forth. When something strange is defected after moving
the system, please contact our service personnel immediately. On rare occasion problems
have been caused by a disconnected board inside the system. From the beginning of the
production boards are installed securely and can withstand considerable shock, but
excessive shock may cause some connection problems.

2.2.3 Electrical Safety Precaution
n Before starting to use the system, check the following .
① Whether the power supply line is suitable with that of the system. Do this before turning power
ON (110~120Vac or 200~240Vac). After checking the power, connect the power cord in the rear
of the system. If connecting peripheral equipment(VCR, Video Printer, Monitor), please check
that the output voltage (120Vac or 230Vac) is compatible and that total output current is within
3.0A(120Vac) or 1.5A(230Vac) maximum. Three appliance outlets are provide one located in the
front basket and two in rear-bottom position.
☞ CAUTION !
In order to prevent electromagnetic noise emissions please do not use AUXILARY POWER
CORDs of length greater than 2 meters.
② Whether all the connection parts (power line and optional equipment) are connected with the
system properly. See the Connection Chapter on 3.2 for the correct connections.
③ whether the system is fully grounded. (If not, noise can occur.)
④ Turn off the power before probe is connected.
☞ CAUTION !
EQUIPOTENTIAL BONDING :
In the hospital, doctors and patients are subject to dangerous, uncontrollable compensating currents.
These currents are due to the potential differences between connected equipment and touchable
conducting parts as found in medical rooms. The safest solution to the problem is accomplishing
consistent equipotential bonding. Medical equipment is connected with connecting leads made up
with angle sockets to the equipotential bonding network in medical room.
Connection Lead
(Socket)
M
Ground A
I
Connector N
Earth in Medical Room B
O
~
~
D
Y
Detail 2. SA9900 Main Console Safety Ground
The SA-9900 is classified as Class I type-BF against electric shock. To safe, please
follow matters that require attention below.

☞ WARNING !
Do not open the safety cover of equipment ; There is dangerous voltage in the equipment.
Medison Service Engineer should be charged with repairing the inside of equipment and
replacement of parts.
Avoid place where the equipment is exposed to inflammable gas or narcotic gas.
There is a possibility of dangerous explosion.
Inspect the equipment before operating it to prevent electric shock.
Inspect the housing equipment of damage such as crushed, punctured, broken,
wet or cable is worn out. If damage is evident, stop using the equipment .
To prevent electric shock, when the equipment clean always pull a plug out of the socket.
The equipment does not provide ECG monitoring function. Therefore the equipment does not
provide measure is recognize incongruent ECG signal. A patient should be isolated from the all
equipment for patient contact (For instance, probe, ECG lead) before pressure pulse of high
voltage.
Do not use ECG electrode HF equipment for operation. There is a possibility of dangerous fire is
caused by damage of HF equipment for operation
Do not use ECG electrode during use pace maker or other electrode. In this case, it is a possible
to be a patient in danger.
Do not use ECG electrode and lead line in operating room.
To prevent electric shock, never submerge the probe cable or connector in the solution. Since
probe surface has watertight -proof (IPX7) but lit is limited only for the probe as shown in the
above figure, please care about using acoustic coupler gel and cleaning /disinfecting the probe
surface. See the Maintenance and Protection Chapter on 1.3 for the correct Maintenance and
Protection.
To prevent electric shock and a fire, whether the power supply line is suitable with that of the
system. After checking the power, connect the power cord in the rear of the system. Please
take care of them from damage.
To prevent electric shock, external system to be connected digital interface have to use
manufactures to pass IEC standardization of manufactures(I.e. data processing unit is
IEC60950/EN60950, medical unit is IEC60601-1/EN60601-1). In addition, the composition part
of all machine have to obey the system standard IEC60601-1-1/EN60601-1-1. Everyman to add
external system to signal input or output part of medical unit, have to confirm to obey the
standard IEC60601-1-1/EN60601-1-1
Don’t contact the patient and signal input/output part the same time. It may happen range over
current.
☞ CAUTION !
This system certificated EMI/EMC. If this system use at electro field, it happen electro damage or
occurrence of poor image. If there is problem that the ultrasound image is very poor, check the
source of electronic wave at the environment to use MEDESON system. These electronic wave
may happen in same or nearing space. The main cause to occur electronic wave is cellular
phone, radio, TV, or microwave machine.
If the system occur any trouble, you have to transfer other place to isolate from EMI.
Electrostatic discharge (ESD) is usually happened for impulse by static electricity. It is common
phenomenon in nature. The condition to occur ESD the most is in dry condition. When you turn
on the heater or air conditional, become this condition. In dry condition, static electricity usually
occur by object to include a person. In ESD condition, static electricity occur when a person
contact an iron-ring handle, file cabinet, computer system, and other person. Static electricity or
ESD occur when the object to charge by electricity is insufficiency charging or in process to
charge no charging object. Static electricity to occur from system operator or patient may give
the impact to ultrasound or probe. Following notice is to protect damage by ESD. A spray to
protect static electricity sprinkle on carpet and Linoleum, or use a mat to protect static electricity,
or contact grounding earth between the system, patient table, and bed.

2.2.4 SAFETY SYMBOLS
The International Electrotechnical Commission (IEC) has established a set of symbols for medical electronic
equipment, which classify a connection or warm of any potential hazards.
The classifications and symbols are shown below.
Isolated patient connection (IEC 601-1-Type BF)
Foot Switch
I and O on power switch represent ON and OFF, respectively.
!
This symbol identifies a safety note. Ensure you understand the function of this control before
using it. Control function is described in the appreciate operation manual.
Identifies equipotent ground (located next to ground stud on the rear panel)
(IEC 417-5021)
Identifies high voltage components operating above 1000 VAC or 1500 VDC.
Identifies the point where the system safety ground is fastened to the chassis.
VGA Output port or Parallel port
Modem or RS232 Input/Output port
Left/Right Audio Input or Video Input port
Left/Rig Left/Right Audio Output or Video Output port
Print Remote Output
ECG Connector

Watertight equipment
Drip-proof equipment
PROBE CONNECTOR
2.3 MAINTENANCE AND PROTECTION
2.3.1 CLEANING
To disinfect clean surface of system as following :
☞ WARNING !
To wash or disinfect the whole of system, should wear mask and gloves always.
☞ CAUTION !
To disinfect surface of system, should do by antiseptic solution is provided by Medison.
CLEANING
① Shut off the power supply of system and pull a plug out of the socket.
② To clean surface of system, rub them smoothly with a soft cloth dampened with a mild soap or
neutral detergent solution.
DISINFECTION
① Mix an antiseptic solution according to suitable solution intensity. Suggest an antiseptic solution to
consent by America FDA 510(k)
② Polish the system surface according to suitable level of solution intensity and contact time. It is on
notice label of an antiseptic solution. You must confirm, if it is suitable solution intensity and contact
time. According to notice data on label of antiseptic solution, dry up in air condition, or polish to use
dry towel

2.3.2 CLEANING FOR GENERAL PURPOSE PROBE
CLEANING
☞ WARNING !
To wash or disinfect the whole of system, should wear mask and gloves always.

☞ CAUTION !
After using probe, it is cleaned certainly. To clean the probe is to do surely an important step
before disinfect ion.
When you use an antiseptic solution, should do by an explanatory note. Do not touch probe or
cable with sharp object such as mess for surgical operation.
☞ CAUTION !
Do not use when clean the probe for surgery. Be careful a soft brush can damage the probe too.
Dry up all part of probe when the probe sterilize and clean. At this time, you must handle that the
wet part of probe lower than not wet part of probe. This is to protect probe from invasion
component of solution at not waterproofing part of probe.
Selecting probe is the most part of image quality. The most suitable image can get with accurate probe.
The system can maintenance the most condition according to select probe .
① Separate the probe from system.

② Separate the sheath, biopsy guard adapt, or biopsy needle guard. (biopsy guard adapt can reuse
and sterilization).
③ Separate the protect-cover. (The protect-cover is throwaway)
④ To remove bad matter on probe and cable, use soft tissue to wet cleansing solution or soft soap.
⑤ To remove bad matter to subsist constantly, wash out after soak in water until waterproofing part.
⑥ If the water remains on probe and cable, polish it with dry soft towel after polish wet soft tissue.
⑦ Mix an antiseptic solution according to suitable solution intensity. Suggest an antiseptic solution to
consent by America FDA 510(k)
⑧ Soak the probe in antiseptic solution like picture following page
⑨ Control the time to soak probe, according to notice data on label of antiseptic solution. Don’t soak
over 1 hour, if the probe can not sterilization.
⑩ Wash out the probe after soak process, according to notice data on sterilization solution or antiseptic
solution label. And dry the probe in air condition, or polish it with clean dry towel. (If the probe is
antiseptic, use the asepsis towel.
⑪ Check the probe, if the probe has crack, break, leak of solution, sharp corner, the damage by
projection. If you can detect any damage, stop to use the probe, and ask the problem to area
customer service center.
Sterilization and antiseptic

-6
Sterilization method can be application just EC4-9ES, VDW5-8B probe. To reduce Pathogens as 10 ,
you have to sterilization like following method in this explanatory pamphlet, and use antiseptic solution to
recommend by MEDISON. Following sterilization solution is suitable sterilization solution at MEDISON
ultrasound system. (Certification by America FDA 510(k))
Sterilization Manufacture Form Solution FDA 510(k)

solution Country
Cidex USA Liquid gluteraldehyde K934434
Cidex Plus USA Liquid gluteraldehyde K923744

☞ WARNING !
If you use mixed solution before, have to check expire term. The level of sterilization solution to need
equipment is differed according to kind of body tissue to contact with equipment. Try to apply suitable
intensity of sterilization solution and contact time. And when it use, must confirm usage book of
manufacture company.
☞ CAUTION !
If you use sterilization solution to do not recommend, unsuitable intensity of sterilization solution,
soak the probe deeper than method to recommend, soak the probe during long time, the probe is
damaged. In this case, you can not receive the warranty .
Do not soak the probe to can not antiseptic over 1 hour. It may be damaged because soak it during
long time.
Use liquid solution to sterilize probe. It can be damaged by Autoclave, EtO gas, and unsuitable
sterilization and antiseptic. In this case, you can not receive the warranty.

2.3.3 Using Probe Correctly
n To increase their life span and to get the best possible performance, handle probes carefully and do
the following:
① Inspect the probe cables and connectors regularly to find any defects.
② Do not drop probes on the floor or against hard objects or surfaces. Bumping may affect their
performance.
③ Probes should be returned to the probe holder for storage when not in use.
④ Do not heat probes. If they are below room temperature, allow them to warm up naturally before
using them.
⑤ Do not bend or pull probe cables. It may disconnect some of the lines inside the cable.
⑥ Use approved ultrasound gel only. Other lubricants or lotions, particularly mineral oil could
eventually damage probes and probe cables. Apply scanning gel only to the heads of probes and
wipe it from probes after each use. When probes are not in use, carefully store them in the case to
prevent damage.
2.3.4 Protect Circuit : Fuse Replacement
① Open the fuse drawer on the upper side of the appliance inlet, there will be the two small fuse
holder.
② Push the fuse holder toward the arrow direction, and Pull the fuse holder toward the upper side of
the appliance inlet.
③ Remove the old fuse by pulling up.
④ Install the new fuse by pushing to the fuse holder.
⑤ Insert the fuse holder to the appliance inlet. At this time, the arrow direction on the upper side of the
fuse holder should be in accordance with that on the fuse draw. Also, the same method is used to
exchange the other fuse holder.
⑥ Close the fuse drawer
Regular Fuse Electricity
Input Electricity Fuse Electricity

100-120VAC 10.0A / 250V
200-240VAC T5.0AL/250V

Kauttu. Box Fuse

Drawer
Nur Sicherung 250V
Use Only With A 250V Fuse
Employer Uniquement Avec
Fusible De 250V
AC
INLET
Figure-A. Appliance INLET
Close
x 2EA
Open
Fuse Holder Fuse
Figure-B. Side view of Figure-C. Inserting Fuse and

Appliance INLET Fuse Holder @ s.h.kim 1996 Feb

2.4 SYSTEM COMPONENTS
n Standard Components
The following is a list of standard components, and is for your reference only.
Your kit may be different depending on specific order requests or customer requirements.
Part Name Description Qty.

215-Z-712A SET COVER SA9900 1
271-Z-006A EXPORT ACCESSARY BOX 1
271-Z-058A BOX HDD SA9900 1
CBL-GROUND-NEW GROUND CABLE 1
CORD-316-MNT MNT PWR CORD 1.4M KKP1603 1
CORD-PWR-3-250V EUROPE AC CORD 250V 1
FUSE-50T10L 50T10L250V(SCHURTER)0034.3127 4
FUSE-50T5L TRIAD 50T T5L250V 4
GEL-0.25L SONO GEL 0.25L 1
RU-48P-BNC CAP CAP BNC 4800HD 1
S/W-WIN-2000 WINDOWS 2000 1
CD/ROM-E041B CD ROM R/W 1
MO/ROM-KR1G3W1S MO DISK 1
WH-322-SIG-20-0 BW PRINTER REMOTE CABLE 1

SonoAce 9900 Section 1-3. Installation Guide
3. Installation Guide for SA9900

3.1 System location and check-out
Avoid the following environments for operation or storage
① Where the equipment is exposed to water vapor.

② Where the equipment is exposed to direct sunlight.
③ Where the equipment is exposed to dust.
④ Where the equipment is exposed to high humidity.
⑤ Where there is a ventilation problem.
⑥ Where the equipment is exposed to a salty atmosphere.
⑦ Where the equipment is exposed to chemicals or gas.
Maintain following temperature and humidity.

Using temperature : 10°C ~ 35 °C (Recommend temperature : 17°C ~ 23°C), When transfer or storage :
-25°C ~ 60°C
Using humidity : 30% ~ 75%, When transfer or storage : 20% ~ 90%
Avoid strong impact or the place to exist oscillation.
☞ NOTE : Try to place the system far from power generators, X-ray machines, broadcasting
stations, and transmission line to avoid electrical noise during scanning. Otherwise, abnormal
images may result. An independent circuit and a safely grounded outlet are strongly
recommended for the SA-9900. Poor or abnormal images may occur if the system shares a
power source with other electrical or electronic equipment.
n Before using the system for the first time, do the following:
1) check that the capacity and voltage of the power source are suitable for the
system(110V/220V).
2) Check that all connectors are securely plugged into their proper location.
3) Check that the system is completely grounded with the ground cable. Otherwise, noise
may be generated.
4) Check that the power switch is turned OFF before connecting probes

3.2 MAKING THE CONNECTIONS.
3.2.1 INSTALL & CONNECTING THE MONITOR
A 4 C
B
A B
C
4 3
① Put up the monitor on base after fit the hole A,B,C.

② Fix the monitor by screw 1,2,3,4.
③ Connect the monitor power cable and signal cable.

3.2.2 Connecting the probe

① Connect the probe connector receptacle located at the front side of the system. Linear or
Convex probes may be connected as desired in the Probe 1, Probe 2 and Probe 3 connectors.
Three probes can be connected simultaneously.
② Carefully connect probes, making sure that the connecting cables of linear or convex
probes face upward.
n Turn the locking lever on the probe connector CLOCKWISE about 90 degrees to connect. Turn the
locking lever on the probe connector COUNTER CLOCKWISE about 90 degrees to disconnect a
linear or convex probe
n When the system is turned on, SA9900 automatically lists the active probe by type and frequency
on the screen.
PROBE 1 PROBE 3
LOCK OPEN
PROBE 2
Foot Switch

3.2.3 Connecting external system.
AUDIO INPUT
Monitor 1
(Main) PATIENT MONITOR IMAGE OUTPUT
PATIENT MONITOR POWER

Monitor 2
(External)
B/W PRINTER IMAGE OUTPUT
INC-JET
VCR INPUT
PRINTER
PRINTER REMOTE PORT
AUDIO OUTPUT
PC RGB OUTPUT
Telephone Line
(Can not use present)
Microphone INPUT
USB Port
VCR OUTPUT
(Printer/ZIP)
LAN DVD INPUT

(Can not use present)

3.2.4 Connecting the AC power cords
Monitor Power
Wall Inlet Power
VCR Powe r
110/220V Power Select Switch
Confirm the power cable if it is suitable that system. Confirm the voltage before connect the power source if it
is 100~120Vac or 200~240Vac. After confirm the power, connect the power cable behind equipment. If you
use VCR, Video Printer and Monitor, you have to confirm input power voltage of external system. After
confirm input power voltage if it is 100~120Vac or 200~240Vac, setting the switch to can select 110V or 220V.
After setting the switch, you can use that equipment with best condition.
☞ CAUTION !
Please do not use Auxiliary Power Cord of which is more than 2 meters because the
electromagnetic noise of power cord must be prevented

3.2.5 Installing HDD
HDD has to be installed before start system operation.
How to install HDD
1. Push HDD into HDD slot. At that time lift handle as below.
2. Locate handle to original position and push down lock button as below. Then HDD is fixed.
3. Lock HDD by key.

Preventive Maintenance Procedure for SA9900

This procedure should be completed using the same environment that is used when the customer is
performing daily exams, for example: Use the same examination room, the same wall outlet, and
especially during image quality evaluation, the same room background lighting conditions.
A. Functional Operation & Test

1. Press the Power On switch on the main side panel and confirm the following :
a. Keyboard lights up.
b. LED on monitor lights up green color.
c. At first the MEDISON logo will appear and then the System executes up in the standard B-mode
format.
2. On the Display Monitor, confirm the following :

a. Adjustment of the monitor brightness and contrast controls from the minimum to maximum results in
no distortion(blooming) on the display.
b. Display is centered on the screen, with good vertical and horizontal resolution (linearity).
c. There is no tearing or bedding at the corners.
B. Probe Test
1. For each Probe attached to the system, perform the following tests, and confirm proper operation :
a. Visually Inspect the head of the probe to insure that there are no cracks, separation, or peeling of the
insulating material on the face of the probe.
b. Knife test : With a light coating of Echo Gel on the face of the probe, slowly scan across the elements
with a thin flat blade, while observing the display for the resulting bright columns of echoes, with no
blank lines that would indicate missing or faulty channels in the probe.
B
Screen image
c. Examine the probe cable and confirm that there are no cuts, crimps, or tears in the insulation.
d. Inspect the connector housing and confirm that screws, fasteners and clamps are all secure.

2. For each Mechanical Sector Probe attached to the system, confirm the following :
a. Observe that the nose cone is not marred, scratched, or peeling.
b. Observe that there are no air bubbles(smaller than 3 mm in size are acceptable) visible in the face
of the probe.
c. Observe that there are no signs of fluid leakage around the seals or nose cone. Obtain a suitable
image on the display and confirm the following :
d. There are no missing lines of information (drop out) in the sector.
e. The motor runs smoothly and quietly with no abnormal knocking sounds.
f. Examine the probe cable and confirm that there are no cuts, crimps, or tears in the insulation.
g. Inspect the connector housing and confirm that screws, fasteners, and clamps are all secure.
C. Operational Mode Tests
Perform the following functional tests for each of the available probes attached to the system.
1. B - B/B - B/M - M - D - B/D - M/D - B/D/M - B/C/D-B/C/M

1) Mode control
2D GAIN DIAL : Turns the scanning mode into B mode pressing this dial and modifies the strength of
echo by dialing
C GAIN DIAL : Turns the scanning mode into C mode pressing this dial and modifies the strength of echo
by dialing
D GAIN DIAL : Turns the scanning mode into D mode pressing this dial and modifies the strength of echo
by dialing
M GAIN DIAL : Turns the scanning mode into M mode pressing this dial and modifies the strength of echo
by dialing
PD GAIN DIAL : Turns the scanning mode into M mode pressing this dial and modifies the strength of
echo by dialing
2) Menu select and Adjust

[ Change Menu ] : Specifies a function or item by moving the menu dial in four directions. pressing this key
once more enables the use to exit the chosen item and choose another item by menu
dial.
[Menu dial] : selects menu items at left side. use this dial when trying to change the values at a chosen
item.
3) Track ball keys operation

[Set] : Select what the track ball cursor points to : value, spot or item.
Auto run start or stop in cine function.
[Change] : Change the current track ball function into another one.
[distance] : Enables distance measurements according to the current scanning mode
[area] : Enables area measurements according to the current scanning mode.
[volume] : Enables volume measurements according to the current scanning mode.
[calc] : Activates a variety of menus for complex measurements and calculations depending on the part of
body currently being scanned.
[Indicator] : Moves the arrow mark.
[User] : A user can define this key’s function as he wants.
[Clear] : Erases characters, body marks, or other calculation figures.
[Exit] : Exit a function
4) Scanning Mode

[Zoom] : magnifies the body part under scanning.

[update] : Changes the direction of the probe without actually moving the probe.
[Depth] : left key to view a deeper portion, right key to view a lower portion.
[Base line] : Moves baseline in either B/W Doppler or Color Doppler.
[scale] : Enables to change the minimum velocity value in B/W Doppler or Color Doppler.
[Speed] : Modify the sweep speed in either M and Doppler mode. select detail mode or fast mode in B
mode.
[Focus] : The two keys on the left side increase or decrease the number of focusing. The two keys on the
right side can move up and down focusing zone.
[Freeze] : Suspends the current screen. when frozen, the cine function can be used.
[Print] : Prints the current screen.
2. ECG Trigger : With an appropriate ECG trace on the screen, Select ECG Trigger and vary the cursor
position along the R wave, confirm that the images update according to the cursor location.
3. SonoView : an image management system for ultrasound images such as store, view, repor and transfer
images. And enables to send and receive DICOM images over the DICOM network.
[SonoView] : Pressing this button shifts from scan mode to SonoView mode.
[Exam List] : provide a list of all the exams stored in local hard disk.
[View Mode] : tab controls for easy and quick navigation between exams or images.
[Exam Mode]: provide a quick and easy method of paging through the images in and exam.
[Compare Mode]: useful for image comparing.
4. 3D mode
[3D] : Pressing this button shifts from scan mode to 3D mode.
[Vol Start] : In 3D mode, Pressing this button starts the calculation of 3D Volume.

SA9900 Preventive Maintenance Check List

Date : Name of Distributor :
Name of Hospital System Serial #
Name of User Version #
Address Warranty
Expiration
Phone #
Instructions :
All of this information is necessary for the warranty.
Check appropriate box below upon the completion of each section of the procedure.
Items Good Bad Remarks

Ι. Check the packing items (compare with packing list) ¨ ¨
ΙΙ. System exterior cleaning procedure ¨ ¨
ΙΙΙ. Probe appearance ¨ ¨
A. Functional operation & test (system initialization state)
1. Power on Sequence and system diagnostics ¨ ¨
2. Monitor display ¨ ¨
3. Key Board Test ¨ ¨
B. Probe test (with each probe)
1. Appearance Condition ¨ ¨
2. Knife test ¨ ¨
C. Operational Mode Tests
1. 2D Mode ¨ ¨
C Mode ¨ ¨
D Mode ¨ ¨
M Mode ¨ ¨
PD Mode ¨ ¨
2. Measurement Test ¨ ¨
3. Zooming & Cine memory Function Test ¨ ¨
4. Image Filing Function Test ¨ ¨
5. 3D Test
D . Electrical Test & Calibration
1. Power Supply ¨ ¨
2. System Calibration ¨ ¨
3. Power Cord/Plug and 110/220 switch ¨ ¨
E. Mechanical operation
1. Circuit boards, plugs, jacks, and connectors seated ¨ ¨
2. Handles & probe holders, monitor, metal panels and wheels ¨ ¨
3. Seating & connection of cables & cords to peripherals ¨ ¨
F. Echo printer, External monitor, Multi-form camera, VCR ¨ ¨
Please send this form to MEDISON by FAX or Air Mail after Fill out the above boxes completely,
Confirmation Signature
Name of Distributor

Service Representative Customer

SonoAce9900 Section 2-1. BDF
1.DBF
The Beamformer module covers from Analog Front -end to Digital Beamforming part. The
Beamformer module is composed of the four Beamformer boards. Each Beamformer board is in
charge of 16 channels in the active aperture (64 channels). The 192 elements probe could be
used in this board without additional circuit. It supports the Linear and Convex probe for 128
elements and the function of Synthetic Aperture and Trapezoidal in the Linear probe for 192
element too. And you can disable all the Beamformer board or BFIC for PW. It also supports RX
dynamic Aperture (the maximum of 64 steps) and Apodization and has the 16 TX Focal point to
the maximum. In addition, RX apodization could have the different curve for each Mode(B,C,D)
and TX aperture also could have the different Aperture ratio for each Mode. The DBF can read
the version of PCB and Board when you version up the S/W. Because the version is the CPLD
of the board, you should modify the inner part of the CPLD to change version
- 48/32 TX pulser/board
- 16 limiter/board
- 16 TGC amp/board
- 16 A/D converter/board
- Bipolar TX pulses
- Synthetic Aperture support
- Trapezoidal imaging support
- RX Dynamic Aperture function (Max. 64step)
- RX Apodization function (different curve support is available per Mode)
- Max. 16 of TX Focal point support
- Board version include in Board.
- Each BFIC function control is available
- Max. 4 of Multi-line receiving support

1.2 BLOCK DIAGRAM

Fig. 1. is the Block diagram of the Beamformer. As this picture, the Beamformer is
composed of the Analog path Block, A/D Block, BFIC (Beamforming IC) , TGC Control part,
Clock part, and Control logic part which controls all the board. The Analog path Block and
A/D Block have respectively 4 Analog path and 4 A/D converter and 4 buffer which takes
place of A/D during the board testing. (There is the room for buffer in the PCB, but actually
is not used and undoubtedly attached to it. The Analog path is mainly composed of Pulser,
Limiter(the sign of -0.6V~+0.6V passes), TGC amp (AD604), and LPF (cutoff : 19.9Mhz).
# The Pulser makes bipolar pulse signal is made of Hybrid IC.

# The Limiter protects the large signal. Small signal (-0.6V~+0.6V) can be passed.
# The TGC amp(AD604) changes the gain according to depth.
# The LPF cut the high frequency noise.
The Fig. 2. is the Block Diagram of Analog path.
The Fig.3. is the Block Diagram of the Control part in the TGC amp.
/Master_ck 61.6MHZ
Clock
/ETRG Buffer /EX_TRG
Control CPU Control Signal

Logic
BFIC Con trol Signal
(XC95108XL)
RF data, Header,
TX pulse
Data_en
Analog Path Block #3 AD Block #3 Block #3
RX switch select signal

T G C
TX pulse
Analog Path Blo ck # 2 AD Block #2 Block # 2

T G C
TX pulse
Analog Path Block # 1 AD Block #1 Block # 1

T G C
TX pulse
Analog Path Block # 0 AD Block #0 Block # 0

T G C
TGC Control Logic

Fig. 1. Beamformer Block Diagram
48/32 16 16 16 1 6
RX s/w Limiter T G C LPF
Pulser
select signal
Fig. 2. Analog path block
FROM : DSP
TGC data 8
8 8
D/A buffer
TGC_CLK
TGC curve
Fig. 3. TGC control

Definition I/O Description

ECHO[0...31] I/O Pulser output & Limiter input
PRE_SEL[0..31] internal Limiter on/off control (Low : OFF , High : ON)
TGC[0..7] internal AD604 TGC curve
A/D converter Enable
/AD_EN I
(Low : A/D Enable , High : A/D Disable)
AD_CLK[0..3] internal A/D clock
AD0_DI[0..7] ~ AD15_DI[0..7] internal A/D outputs
MVP5 I Analog +5V
MVN5 I Analog -5V
MVP12 I Analog +12V
MVN12 I Analog -12V
MVPVAR I Analog 0 ~ +80V
MVNVAR I Analog 0 ~ -80V
MVCC I Digital +5V
MVCC33 I Digital +3.3V
61.6MHz I 61.6MHz
/EX_TRG I Exciting Trigger
B_TEST_D[0..7] I MCB014A Test input data
Beamformer board number
0 : channel 0~15 , 1st B/D
1 : channel 16~31 , 2nd B/D
BD_ID[0..2] I
2 : channel 32~47 , 3rd B/D
3 : channel 48~63 , 4th B/D
4 ~ 7 : Reserved
EXT_A[0..20] I/O MCB014A IN/OUT
EXT_B[0..20] O/I MCB014A OUT/IN
Freeze
Freeze I Low : Pulser enable
High : Pulser disable
No probe
No_PRB I Low : Pulser enable
High : Pulser disable
DATA_EN_A
I/O BFIC internal FIFO read enable signal
DATA_EN_B

Beamforming Direction
0 : EXT_A & DATA_EN_A & HEADER_A
are input.
EXT_B & DATA_EN_B & HEADER_B
BD_DIR Internal are output
1 : EXT_A & DATA_EN_A & HEADER_A
are output
EXT_B & DATA_EN_B & HEADER_B
are input
Scanline number & Control signal
SCAN[0..9] : Scanline
SCAN[0..12] I SCAN10 : Synthetic Aperture ON/OFF
SCAN11 : Steering ON/OFF
SCAN12 : Reserved
FOCAL[0..3] I TX focal point
00X : B , M mode
01X : D mode
Line type[0..2] I
10X : C mode
11X : /OF & NULL
CPU_DATA[0..15] I/O CPU Data
ADDRESS[0..11] I CPU Address
/BCPU_WR I CPU Write
Definition I/O Description
/BCPU_RD I CPU Read
HEADER_A
I/O Header signal for MCB014A
HEADER_B
MTCK I
MTDO O
For JTEG writer
MTDI I
MTMS I
CPU CS for PCI bus
0 : 8bit port out
/B CPU_CS[0..3] I 1 : 16bit port out
2 : 16bit port out(Slow read)
3 : 32bit port out
B_TGC_CLK I TGC Data latch clock

TX pulse masking signal

/TX_MASK Internal Low : Pulser disable (default)
High : Pulser enable

1.4 Details
1.4.1 TX PULSER
The high voltage switch is not used for SA9900. The SA9900 has the Pulser as many as
element because it supports the probe with 192 elements. So, the SA9900 should have
the 48(32) Pulser for one Beamformer board though it has the active aperture of 64
channel. (192 element probe support). The Pulser is made with Hybrid IC.(MHIC9064).
There are 2 Pulser on the Hybrid IC in the MHIC9064. So there should be 3 MHIC9064
for receive channel.
The pin assignment of MHIC9604 and inner circuit diagram are as the following pictures.
The exciting pulse from MCB014A is inputted into the EX and /EX in the MHIC9604. First
the Q1 is ON by EX, and then Q4 is ON. The firing pulse, PUL, falls to –80V and rises up
to 0V. Afterwards, Q2 and Q3 are ON by /EX, the PUL rises +80V and falls 0V again. As
this high bipolar pulse is generated, passed to each element on transducer.
1 GND
EXPLS1 2 I1
/EXPLS1 3 /I1
EXPLS0 4 I2
/EXPLS0 5 /I2
VP12A 6 +LV
ECHO1 7 OUT 1
8 GND
ECHO2 9 OUT 2
VPVARA 10 +HV
Fig. 4. Pin Assignment of MHIC9604
+12V
+80V
150
Q3 D5
C1 T1
EX Q1 D3
200 D1 C3 PUL
D4 5.1K
C2 Q4 D6
150
/EX Q2
-80V
200 D2

Fig. 5. Circuit Diagram of MHIC9604
1.4.2 Receive Channel

There are the 16 Analog Receive Channel for each Beamformer board. The channel is
composed as following.
#. 3 Limiter
#. Simple diode circuit
#. TGC amp
#. 8dB Amplifier
#. Low-Pass Filter (LPF)
Echo(x) Switch
PRE_SEL(x)
Low-Pass To
Echo(x+16) Switch Limiter Amp.
Filter A/D Converter
PRE_SEL(x+16) TGC Amp.
Echo(x+32) Switch
PRE_SEL(x+32)
Fig. 6. Block Diagram of Receive Channel

1.4.3 Switch(RX) & Limiter

Each channel has the 3 RX switch to support the probe with 192 elements. The RX switch
cuts off the signal of the inactive element by diode and PRE SELx. It functions as primary
limiter at the same time. By using the second limiter consisted of 2 diode, the –
0.6V~+0.6V signal is generated and passed to TGC Amp.
+3.3V
PRE_SEL Q1
-5V
D2
D2
D1 D1
ECHO Limiter_out
R1
L1 R2 R2 L1
R1
-5V
Fig. 7. RX switch by using Diode
#. PRE_SEL is the BFIC output(3.3V level)

#. L1 is the coil for Zero-bias
#. R1 is the resistance for Impedance matching. To avoid the damage, The R1 is
arranged with electrical series each other when high Pulse enters. The input
resistance to the Limiter is (2R1 // (R2//R2)).
PRE_SEL D2 D1 Limiter Signal
High(3.3V) OFF ON ON Pass

Low(0V) ON OFF OFF No pass
Table 1. Limiter State Table2.4 Switch(RX) & Limiter

1.4.4 TGC amp & Amplifier

AS604 is used for TGC amp. There are 2 variable gain amp in AD604, and the 2 channels
of TGC amp are consisted by using them. In this stage, it compensates ultrasound signal
to be transmitted from medium to variable gain according to time(progress distance). This
ultrasound signal is amplified up to Max.48[dB] by AD604.
VINP BOUT AD812

Limiter_out
AD604 LPF + A/D input
R1
Fig. 8. TGC amp & Amplifier
In general, AD604 is 20~ 54[dB] Voltage Gain Controllable Amplifier. The rear amplifier
could amplify up to 8dB when IC is attached to PCB, but is bypassed in real PCB.
1.4.5 LPF
The Low-pass Filter is the last stage of Analog Receive Channel. LPF reduces noise
suppression in stop band which is beyond ultrasound range and takes charge of Anti
Aliaing Filter. Anti aliasing filter is protect aliaing to can happen in 7.5 Mhz probe by
limiting sampling clock at the Digital Beamforming IC. The A/D clock is 61.6Mhz, and the
probe with center frequency up to 10Mhz could be used. This filter is a 4 pole Butterworth
filter to reduce ringing and 3dB cut off frequency is 19.9Mhz.

1.4.6 TGC curve
TGC_D[0..8] R1
8 Non inverting
74HC 8 DAC0808
TGC_CLK 574 TGC_curve OP 8
TGC[0..7]
Amp
2.49k
TGC_REF inverting Non inverting
+5V
Fig. 10. TGC curve
DAC0808 reference voltage is +5V and resistance of reference is 2.49k. So, Max of each
curve is 5V/2.49k ×´ 1.4k ≅ 2.8V. TGC curve is 0 ~ 2.8V. A user can control the TGC
curve by slide volume. CDP board gives the TGC Curve Data. TGC Curve could have
different curve according to Line type.
1.4.7 A/D Block

Each A/D Block is composed of 4 AD , 4 Buffer and connector. The Buffer is used when
Board testing. The connector is used when reading the RF data by Daughter board. There
is no room for buffer and connect because they aren’t used actually.
AD92833-80 from analog devices Co. is used for A/D and inner reference of AD is used
for reference. Analog input accepts signal without offset

1.4.8 TX Pulse
MCB014A can generates TX pulse and RX switch select signal where MCB014A is
charge of. Each TX and RX can undertake the Max.12 signals when TX Apodization
function is not used (TX apodization TX pulse, and RX switch select signal belong to pin).
So, they control the probe with 192 element without additional circuit. The Digital
Beamforming will be introduced before MDB014A (BFIC). How to Beamform is divided
into Analog Beamforming and Digital Beamforming .
The Fig. Fillowing the structure of Beamforming.
Focused
signal
target
Transducer delay line
Fig. 18. Analog Beamforming
Focused
signal
target
Transducer memory
Fig. 19. Digital Beamforming (uniform sampling)
Focused
signal
target
Transducer Sampling memory

Fig. 20. Digital Beamforming (PSDF : Pipelined Sampled Delay Focusing)

1.5 Timing Chart

1.5.1 /PREG_WR connection for BFIC
/ETRG
/PREG_WR
Scanline
Focal point Data N+1 N
Linetype
? G1usec
? G3usec
1.5.2 . The interface between signals used for P register and Timing & RF memory
/
ETRG
Scanlin
Focal point N+ N+ N+
e N
data 1 2 1
/P_WR
data_ready_out
RF_DVS
RF_DATA
T1 T2

1.6 Wave Form

1.6.1 2CH : Element-0 of TP Board #3 à +20-V 1CH : TP L-14
1.6.2 2CH : Element-0 of TP Board #3 à +20-V 3CH: TP10 4CH: U38

PIN-7
1.6.3 2CH TP: Element-0 of TP Board #3 à +20-V 1CH: TP: M_CLK

1.6.4 1CH TP: /ETRG 2CH TP: Pin-121 of Board #3-

BFIC #0
< When /ETRG is Rising > < When /ETRG is

Falling>

1.6.5 1CH TP: Board #3 Pin-33 2CH TP: Board #0 Pin-119
1.6.6 1CH TP: Board #3 Pin-182 2CH TP: Board #3 Pin-121
1.6.7 1CH TP: Board #3 Pin-119 2CH TP: Board #3 R941 4CH TP: Board #3 Pin-121

1.6.8 2CH TP: U38? Pin-20 1CH TP: R118

1.6.9 2CH TP: R118 3CH TP: Pin-121
1.6.10 2CH TP: U3 Pin-19 3CH TP: U3 Pin11

1.6.11 1CH TP: /ETRG 2CH TP: P_REG
1.6.12 1CH TP: /ETRG 2CH TP: XC95144 Pin-64
1.6.13 B MODE à 2CH TP: /ETRG 1CH TP: TP-1

1: Relation of ETRC when GAIN is “0” 2, Relation of ETRC when GAIN is “100”
1.6.14 C MODE à 2CH TP: /ETRG 1CH TP: TP-1

1: Relation of ETRC when GAIN is “0”
2, Relation of ETRC when GAIN is “100”

1.6.15 BCD MODE à 2CH TP: /ETRG 1CH TP: TP-1

1, If 2D GAIN is “0” 2, If 2D GAIN is “100”


1.6.16 D MODE à 2CH TP: /ETRG 1CH TP: TP-1

1, If 2D GAIN is “0” 2, If 2D GAIN is “100”
1.6.17 1CH TP: /ETRG 2CH TP: /OF

B-MODE C-MODE

D-MODE M-MODE
1CH TP: /ETRG 2CH TP: /OF

CD-MODE CM-MODE

PD-MODE /OF

SonoAce9900 Section 2-10. PSA
10.PSA (PROBE SELECT ASSEMBLE)
10.1 General Description

Front plane module has functions for interfacing between System and Probe(Scanhead).
Probe Select Board has three 260-pin Cannon Connector and one coax-pin LEMO
Connector.
And each pin settled for Probe Personality signal and HV-MUX control, and for choosing
1 Probe among 3 Probes, each pin was made up of Relay circuit.
10.2 Cannon Connector

Connector use 260-pin ZIF Connector of ITT Cannon.
10.2.1 Generic Pinouts

PIN SIGNAL Function
A3,A7,c1,c7 SHG Outer Shield Ground
E8 PDAT Serial Data
E3 PCLK Serial Clock
J7 PSEL Chip Select
E7 PWEN Write Enable

T7 /PIND Probe Index
L3 XD0 Mux data signal
P3 XD1 Mux data signal
U3 XD2 Mux data signal
Y3 XD3 Mux data signal
L7 XD4 Mux data signal
P7 XD5 Mux data signal
S7 XD6 Mux data signal
U7 XD7 Mux data signal
J3 /XLD Strobe to buffered register on mux
chips.
G3 /XCLK Shift register clock.
Y7 REF+ +10V reference voltage
S3 X+5 +5V DC power
W7 X+12 +12V DC power for Mux chips
W3 X-12 -12V DC power
C7 HV+ +90V DC power for Mux chips

G7 HV- -90V DC power for Mux chips.

D3,K3,M7, R3,V7,X7 XGND Power and control signal ground
return
a3 SNS1 Sensor 1
C3 SNS2 Sensor 2
N7 SNS3 Sensor 3
a7 S_DR2 3D Motor control SIN drive
b7 S_RT2 3D Motor control SIN return.
Y10 C_DR2 3D Motor control COS drive
Y8 C_RT2 3D Motor control COS return
N3 STA2 3D Motor control position detection.

10.2.2 Linear/Curved Array and 3D Transducers
1 2 3 4 5 6 7 8 9 10
A EL96 EL97 SHG EL0 EL1 EL2 SHG EL48 EL49 EL50
B EL98 EL99 ELG EL3 EL4 EL5 ELG EL51 EL52 EL53
C EL100 EL101 SNS2 EL6 EL7 EL8 +HV EL54 EL55 EL56
D EL102 EL103 XGND EL9 EL10 EL11 ELG EL57 EL58 EL59
E EL104 EL105 PCLK EL12 EL13 EL14 PWEN PDAT FREEZ ELG
F EL106 EL107 ELG EL15 EL16 EL17 ELG EL60 EL61 EL62
G ELG ELG /XCLK EL18 EL19 EL20 -HV EL63 EL64 EL65
H EL144 EL145 ELG EL21 EL22 EL23 ELG EL66 EL67 EL68
J EL146 EL147 /XLD ELG ELG ELG PSEL EL69 EL70 EL71
K EL148 EL149 XGND EL108 EL109 EL110 ELG EL72 EL73 EL74
L EL150 EL151 XD0 EL111 EL112 EL113 XD4 EL75 EL76 EL77
M EL152 EL153 ELG EL114 EL115 EL116 XGND EL78 EL79 EL80
N EL154 EL155 STA2 EL117 EL118 EL119 SNS3 EL81 EL82 EL83
P EL156 EL157 XD1 EL120 EL121 EL122 XD5 EL24 EL25 EL26
R EL158 EL159 XGND EL123 EL124 EL125 ELG EL27 EL28 EL29
S EL160 EL161 X+5 EL126 EL127 EL128 XD6 EL30 EL31 EL32
T EL162 EL163 ELG EL129 EL130 EL131 /PIND EL33 EL34 EL35
U EL164 EL165 XD2 EL132 EL133 EL134 XD7 EL36 EL37 EL38
V EL166 EL167 ELG EL135 EL136 EL137 XGND EL39 EL40 EL41
W EL168 EL169 X-12 EL138 EL139 EL140 X+12 EL42 EL43 EL44
X EL170 EL171 ELG EL141 EL142 EL143 XGND EL45 EL46 EL47
Y EL172 EL173 XD3 ELG ELG ELG REF+ C_RT2 ELG
C_DR2
Z EL174 EL175 ELG EL180 EL181 EL182 ELG EL84 EL85 EL86
a EL176 EL177 SNS1 EL183 EL184 EL185 S_DR2 EL87 EL88 EL89
b EL178 EL179 ELG EL186 EL187 EL188 S_RT2 EL90 EL91 EL92
c SHG ELG ELG EL189 EL190 EL191 SHG EL93 EL94 EL95

10.2.3 Phased Array Transducers (64 elements)

1 2 3 4 5 6 7 8 9 10
A ELG1 ELG1 SHG EL0 EL1 EL2 SHG ELG1 ELG1

ELG1
B ELG1 ELG1 ELG1 EL3 EL4 EL5 ELG1 ELG1 ELG1
ELG1
C ELG1 ELG1 SNS2 EL6 EL7 EL8 +HV ELG1 ELG1
ELG1
D ELG1 ELG1 XGND EL9 EL10 EL11 ELG1 ELG1 ELG1
ELG1
E ELG1 ELG1 PCLK EL12 EL13 EL14 PWEN PDAT FREEZ
ELG1
F ELG1 ELG1 ELG1 EL15 EL16 EL17 ELG1 ELG1 ELG1
ELG1
G ELG1 ELG1 /XCLK EL18 EL19 EL20 -HV ELG1 ELG1
ELG1
H ELG1 ELG1 ELG1 EL21 EL22 EL23 ELG1 ELG1 ELG1
ELG1
J ELG1 ELG1 /XLD ELG1 ELG1 ELG1 PSEL ELG1 ELG1
ELG1
K ELG1 ELG1 XGND ELG1 ELG1 ELG1 ELG1 ELG1 ELG1
ELG1
L ELG1 ELG1 XD0 ELG1 ELG1 ELG1 XD4 ELG1 ELG1
ELG1
M ELG1 ELG1 ELG1 ELG1 ELG1 ELG1 XGND ELG1 ELG1
ELG1
N ELG1 ELG1 STA2 ELG1 ELG1 ELG1 SNS3 ELG1 ELG1
ELG1
P ELG2 ELG2 XD1 ELG2 ELG2 ELG1 XD5 EL24 EL25 EL26
R ELG2 ELG2 XGND ELG2 ELG2 ELG1 ELG1 EL27 EL28 EL29
S EL32 EL33 X+5 ELG2 ELG2 ELG1 XD6 EL30 EL31
ELG1
T EL34 EL35 ELG2 ELG2 ELG2 ELG1 /PIND ELG1 ELG1
ELG1
U EL36 EL37 XD2 ELG2 ELG2 ELG1 XD7 ELG1 ELG1
ELG1
V EL38 EL39 ELG2 ELG2 ELG2 ELG2 XGND ELG2 ELG2

ELG2
W EL40 EL41 X-12 ELG2 ELG2 ELG2 X+12 ELG2 ELG2
ELG2
X EL42 EL43 ELG2 ELG2 ELG2 ELG2 XGND ELG2 ELG2
ELG2
Y EL44 EL45 XD3 ELG2 ELG2 ELG2 REF+ C_RT2 ELG2
C_DR2
Z EL46 EL47 ELG2 EL52 EL53 EL54 ELG2 ELG2 ELG2
ELG2
a EL48 EL49 SNS1 EL55 EL56 EL57 S_DR2 ELG2 ELG2
ELG2
b EL50 EL51 ELG2 EL58 EL59 EL60 S_RT2 ELG2 ELG2
ELG2
c SHG ELG2 ELG2 EL61 EL62 EL63 SHG ELG2 ELG2
ELG2

10.2.4 Static Lemo Connector

Static CW Probe used coax -pin LEMO Connector. Connector is made up of two coax-
pins and six pins. Two coax-pins are used at TX/RX of Static CW, and six pins are used at
Personality of Static Probe.
Pin Signal Function
C1 CWRX Receiving signal of Static CW doppler

C2 CWTX Transmitting signal of Static CW doppler
1 CWID0 Static Probe Personality I.D. LSB
2 CWID1
3 CWID2
4 CWID3
5 CWID4 Static Probe Personality I.D. MSB
6 CWIDG
Shell SHG Outer Shield Ground
10.2.4.1 Lemo Pin-Out
C1
4 1
5 2
6 3
C2
Fig1. Lemo Connector for Static Probes (Backview)

10.3 Probe Switching

Use AGN21012 for switching one Probe among the 3 Probe. Relay AGN21012 is
Latched type and has two 1-pole/2-thow switch each chip. Each Relays was switched
through receiving 4 data such as /R_A_A, /R_A_B, /R_AB_A, /R_AB_B from CW board.
/R_A_A and /R_A_B is same and /R_AB_A and /R_AB_B is same. They switching table is
as below;
PSEL_AB PSEL_A /R_AB_A,B /R_A_A,B Probe Port
0 0 1 1 C
0 1 1 0 C
1 0 0 1 B
1 1 0 0 A
Table 1. Switching Table of Relay

10.3.1 Relay Switching Diagram
Syste Elementary Switching Prob
Port C
Echo Port B
Port A
/R_AB_A,B
/R_A_A,B
Fig 2. Relay switching diagram

10.3.2 Steered CW switching

Steered CW has own Pulser and Pre-amp separately Beamformer Board. That reason, In
Steered CW Mode, Line which come from Probe convert Beamformer Board into CW
Board by relay(AGN20012).
BF13~28
EL13~28
CWTX15~0
EL163~178
BF163~178(CH35~50)
(EL35~50)
CWRX0~15
EL0~12, BF0~12,
EL29~127 BF29~127
EL128-162, BF128-162,
EL179-192 BF179~192

SonoAce9900 Section 2-11. Rear Plate
11.REAR PLATE
REAR PLATE is made up of external equipments that are connected with this system as below.
VGA 1, 2 : Use can choose 1 or 2, if user choose 1, user see the image on MAIN MONITOR, or
if user choose 2, user see the image on external MONITOR< PARALLEL PORT is possible to
use PRINTER PORT. It is possible to input and output related to AUDIO/VIDEO. Beside,
PORT which called DICOM is able to be remote translating image.

SonoAce9900 Section 2-12. Revision History
12. REVISION HISTORY

12.1 H/W_S/W COMPATIBLE MATRIX
S/W VER.
Changing degree
V1.0.0.523
V1.0.0.529
V1.0.0.530
V1.0.1.533
V1.0.1.535
V1.02.545
B/D name Part number Problem fact
BEAMFORMER BD-332-B/F-2A 01 Initial release(2000.08.11)
CW BD-332-C/W-1A 01 Initial release(2000.08.11)
BD-332-C/W-2A 02
BD-332-C/W-2B 03
DSC BD-332-DSC-1A 01 Initial release(2000.08.11)
BD-332-DSC-1B 02
BD-332-DSC-1C 03
BD-332-DSC-2A 04 DC NO:00-9900-012 (2000.09.26)
Re-Artwork

DSP BD-332-DSP-1A 01 Initial release(2000.08.11)
BD-332-DSP-2A 02 DC No:00-9900-002 (2000.08.17)
Eliminate multibeam artifact and so on
ECG/A BD-332-ECG/A-1A 01 Initial release(2000.08.11)
KEY/I BD-332-KEY/I-1A 01 Initial release(2000.08.11)
KEY/M BD-332-KEY/M-0A 01 Initial release(2000.08.11)
BD-332-KEY/M-1A 02 DC No :00-9900-005(2000.08.22)
Correcting switch sensitivity
MOTHER BD-332-MOTHER-0A 01 Initial release(2000.08.11)

S/W VER.
Changing degree
V1.0.0.523
V1.0.0.529
V1.0.0.530
V1.0.1.533
V1.0.1.535
V1.02.545
B/D Name Part number Problem fact
P/S/A BD-332-P/S/A-0A 01 Initial release(2000.08.11)
REAR/L BD-332-REAR/L-1A 01 Initial release(2000.08.11)
REAR/M BD-332-REAR/M-1A 01 Initial release(2000.08.11)
REAR/R BD-332-REAR/R-1A 01 Initial release(2000.08.11)

U/D BD-332-U/D-0A 01 Initial release(2000.08.11)
V/M BD-332-V/M-1A 01 Initial release(2000.08.11)
MORTOR
BD-MOTOR/CNG Initial release(2000.08.11)
CONTROL
TRACK BALL BD-316-T-BALL Initial release(2000.08.11)

12.2 REVISON HISTORY OF EACH BOARD

12.2.1 DBF BOARD
Renewal date : 2000-10-13 Final Version : 2A Charge Person : JUNG YOUNG SU
Application ETC
B/D DC Facts & PCB(A/W)
Later Modification Facts D/C NO. Equipment (Application
Revision Problem Facts Modification Facts
( S/N ) Date )
332-02-004- 1.Doppler noise occurs before strong Rx switch part to be
1A target. constituted by diode.
èWhen it executes RX Changing to analog switch
switching(element select), (ADG711).
TX pulse occurs weakly.
Doppler noise occurs by that fact.
And giving a lot of prf dummy time
to hide this state.
So, loss frame rate because of
that fact.
332-02-004- 1. After changing PCB to version 1A, Control signal to transmit from
2A noise to have pattern occurs. BFIC to analog part is passed
èUsing analog switch to RX switch. buffer(74HC245 & 74LVC245)
The reason to be connected signal
for analog part is that noise occurs at
monitor by digital noise of BFIC

transmits to analog

12.2.2 CW BOARD
Renewal date : 2000-11-10 Final Version : 2A Charge Person : KIM JUNG BAE
Application ETC
REVISION Problem Facts Modification Facts
( S/N ) Date)
332-02-013- When occurring insertion mistake, 0A BOARD Modification as like 1/13(SHEET)
1A receiving damage ICL7667 1A BOARD 1A BOARD
Addition resistance 923~R946
(10ohm1/8W) 24EA.
Addition ICL7667 (U147,
U148) 2EA
Noise occur at monitor in connection Addition condenser(1) C823~C827 2/13(SHEET)

with PROBE I.D. Addition condenser(2) Addition 893~C901
Condenser C823~C827
(Addition 0.1Uf(SMD))
Condenser C893~C900
(Addition 220PF(SMD))

U143(MAX161)PIN 4, PIN5. MAX161part Addition PATTERN 2/13(SHEET)

(addition with HV SENSOR) #1 pin on U148 connect #5 on on PCB
U143.
#7 pin on U148 connect #4 pin
on U143.
Changing power part circuit in Changing +3.3V power Modification as like 13/13(SHEET)
connection with +3.3V (U149 part(before) before changing
MAX604CSA) Changing +3.3V power part
(after)
Addition U149
Connecting 2, 3, 6, 7 of U149
to GND(JUMPER)
Cancel L5

Application ETC
( S/N ) Date)
332-02-013- Part to SENSING HVF+,HVF- HVF+ Addition circuit 13/13(SHEET)
1A (TL082) HVF-
Addition TL082(U148) (1EA)
Addition Resistance 100KF
(R917,R919,R922)
Addition Resistance 8.25KF
(R918,920,R921)
Addition Condencer
0.1uF(C828,C829,C830,831,832)
3D PROBE I.D. READ After processing part 3,4PIN of RL7 13/13(SHEET)

7,8PIN SHORT
Nothing supply VCC(+5V) voltage Connecting #20 pin of U26 with Noting yet. 2/13(SHEET)
in 74HC245(U26) +5V
Nothing output +3.3V from Connection MAX604CSA(U149) Noting yet 13/13(SHEET)
MAX604CSA(U149) 2,3,6,7,PIN to GND
2A After processing of 1A and PCB 1. Modification because U26 is After processing
modification by changing not connecting with +5V facts reference
Materials. 2. Modification because 2, 3, 6, 7
of U149 is not connection with

GND.
3. Modification ; Addition PAD to
suit because changing
AD677(U39,U48) from DIP to
SMD.
4. Modification LAND to prepare

changing DS0026(U58,
U94~U107)

Application ETC
B/D DC Facts & PCB(A/W) D/C
Later Modification Facts Equipment (Application
REVISION Problem Facts Modification Facts NO.
( S/N ) Date)
2B 1. CPLD Compile error 1. Application compile, new
2. Accuracy improvement of TEE pose_cw2.jed after changing
probe temperature sensor. equation
2. Insertion 100K 1% resistance
between #1 and #2 pin after
raising #2pin of U144 TL082.
And connecting 20K 1%
resistance between #2 pin and
GROUND by jumper.
3. remove R120(10K ; exist
around U29) and attach to
R128(exist around U38) mark.

12.2.3 DSC BOARD

Renewal date : 2000-11-10 Final Version : 2A Charge Person : KIM JONG GU
Application ETC
( S/N) Date)
332-02-006- 1.Download Error : 1-1 Remove #5, #6 pin of Nothing
1A dsc_pixel_vel.hd0 U36,94,108, 146,164(XCS05XL)
dsc_azimuth_vel.hd0, 1-2 Connecting front hole to be
FPGA Down err connected with #96pin of U36 and
#16pin of U46 by jumper.
Connecting front hole to be
connected with #94pin of U36 and
#15pin of U46 by jumper
Connecting back resistance R58 to
be connected with #96pin of U94 and
#16pin of U98 by jumper
be connected with #94pin of U94 and
Connecting #99pin of U146 and
Connecting #90pin of U146 and

1-4. Connecting front resistance R70

to be connected with #91pin of U108
and #36pin of U114 by jumper.
be connected with #53pin of U164
and back hole to be connected with
be connected with #54pin of U164
and back hole to be connected with

Application ETC
( S/N) Date)
332-02-006- 2. Problem of 3D Path 1. dsciod.jed rewrite.
1A Error and Breaking è When do cine 3D acquisition,
when do Diagnostic. change reading unit 32 à16 (make
decoding addr to can open until
900-93F)
(Change reading unit 34 à 18 in
PC)
2-2.R337 Canceling
è Solve the problem to occur some
data Error on the Diagnostic Path
from SSRAM to FMC by controlling
FM_WCK1.
(Observe the clock before changing
and after it, raised the level at curve
part of wave by removing Pull-
down(R337) resistance)
3. Occurring dot when
Cine and Color& angio. 3-1.Exchange R222,230 to 33ohm à

75ohm
3-2.Remove Capacitor for EMI of
U109( 64Mbyte Module RAM)

Application ETC
( S/N) Date)
332-02-006- 4. Occur horizontal white 4-1.Changing dsc_memctr.hd0
1A line at random, or problem
to occur line in color box on
B/C Mode.
5-1.Removing R456
5. Occur white spot on
image. 6-1.Changing dsc_memctr.hd0
6. Occur dot line at the

lower end M-mode when
executing side by side in
B/M Mode.

Application ETC
( S/N) Date)
1B Occurring problem that occur 1. Connecting #17pin and #12pin of 00-
the horizontal line sparkle on U18(74LV245) by jumper. 9900-
display at random 2. Raise #2pin of U164(XC05XL). 011
3. Raise #54pin and 61pin of
U65(MGA017).
Connecting #8pin of
U18(74LV245) and #54pin,
#61pin of U65, and #2pin of
U164 by jumper
1C 1.Occur white spot sparkle on 1. Removing R384(220ohm) Expect
image at random. resistance ation
DC
2.Occur white spot on image.
( In low temperature ) 2. Changing U169(74LVC245) to
74LVT245
2A 1. Modification Artwork about 1-1. Clk(# 11pin of U40 , U41) of BW After processing facts 00-
each Jumper to be occurred input Data Latch reference 9900-
during certification test of BW_CLK -> Changing to 012
DSC B/D SS_EV_RCK,S_OD_RCK

: Securing of Timing Margin => Occurring Dot on image by Clk

difference between DSP b/d and DSC
b/d

Application ETC
( S/N) Date)
2A 1.Modification Artwork about 1-2.Changing FM_WCK2(Pin2 of U94) After processing 00-
each Jumper to be occurred of Color Azimuth Interpolator to facts reference 9900-
during certification test of FM_WCK3. (making anew 012
DSC B/D FM_WCK3 at #57pin of U157 )
: Securing of Timing Margin => Color data differ 1-2 count by
unstable Clk of FM_WCK2 when
execute Diagnostic test of DSC b/d
(Modification dsc_ictr.hd1)
Using hd1 to divide with 1B
1-3. Changing Clk of BW & Color
CINE Memory
=> Occurring Dot on image zone by
shortage Margin of Clk when
operate CINE Memory.
=> Divide input Clk0,Clk1,Clk2,Clk3 of
CINE Memory, and supply 61.6MHz
just to Clk0,Clk2
1-4.Addition one more Source to
FM_SC1 and FM_SC2
=> Occurring Dot by bad FM_SC Clk

wave when transmit DSC B/D data

to VM B/D.
1-5.Connecting TMS, TCK Pin to
reject FPGA Download Error at
+3.3V.
( U36 : connect pin 5, pin6 at +3.3V ,
U164 : connect pin 5, pin6 at +3.3V,
U146 : connect pin 5, pin6 at +3.3V)
Application ETC
( S/N) Date)
2A 1. Modification Artwork about 1-6. dscio.jed – dsc version check After processing 00-
each Jumper to be facts reference 9900-
occurred during 012
certification test of DSC 3.The time to output data from Module
B/D RAM is changed by temperature, so
: Securing of Timing Margin the problem occur to decrease Hold
2. Application with problem to time during fifo write.

be occurred at Ver 1C
( No changing Rev)
3. Occurring Dot when

executing 3D&SONOVIEW 4.Modification dsc_pgm.hd0
CINE.
5.Modification dsc_ictr.hd0
4. Occurring Dot when
executing 3D Rendering
5. Problem to disappear 6.Modification dsc_xmem.hd0,

image when press Update dsc__pgm.hd0
key continuously.
6. Disappear IMAGE.

12.2.4 DSP BOARD

Renewal date : 2000-10-12 Final Version : 2A Charge Person : KIM HANG WHOAN
B/D DC Facts & Later Modification Facts PCB(A/W) D/C Application ETC
REVISION Problem Facts Modification Facts NO. Equipment (Application
( S/N) Date)
BD-332-008- Application Mutibeam Connecting U52(74LV245),R363 332-02-008-1
1A JUMP Application all
BD-322-008- 1.Widen MGA015 Padpitch Changing PCB #1, #2 332-02-008-2

2A 2.Removing Mutibeam
JUMP 3.Changing PDSP0.HD0, PDSP0.HD1, Application at
3.Problem to deviate the PDSP0.HD2, PDSP0.HD3 Ver1.0.1.533
lower part of Color box
and output position of
Color differently.

12.2.5 ECG BOARD

Renewal date : 2000-10-13 Final Version : 1A Charge Person : KIM HANG WHOAN
Application ETC
( S/N) Date)
332-02-014- Nothing
1A

12.2.6 KEY INTERFACE BOARD

Renewal date : 2000-10-13 Final Version : 1A Charge Person : HEO YOUNG HWA

Application ETC
( S/N) Date)
332-02-020- It is possible to be damaged Addition radiant plate Occurring the hole at
1A XILINX by receiving heat. side part of XILINX,
and position of
material around the
hole changes
gradually

12.2.7 K/M BOARD

Application ETC
( S/N) Date)
332-02-021- It is difficult to press key Addition SW beside key of fan
1A button of fan shape at shape(changing to 2 count)
outside.

12.2.8 MOTHER BOARD

B/D DC Facts & PCB(A/W) D/C Application ETC
Later Modification Facts
REVISION Problem Facts Modification Facts NO. Equipment (Application

( S/N) Date)
332-02-001- Nothing
0A

12.2.9 PC BOARD
Application ETC
( S/N) Date)
0B When executing Main, it is XILINX COPY Nothing
expressed that CPU process (9054_0V(0B).JED)
is used 100%
0B Occurring Image sparkle Changing R268 to 33ohm Modification to be

toward side at WINDOWS Changing L5 to 0ohm changing to 2A.
BOOTTING screen
2A There are after Processing Nothing Nothing.
before B/D. Addition Module RAM 128M
Sometimes stop at
SONOVIEW

FILE of XILINX is L :\SA_TC\CWDP\HISTORY\

0B VERSION : P9054_V0(0B).JED
2A VERSION : P9054_V1.JED
12.2.10 PSA BOARD

Application ETC
( S/N) Date)
332-02-003- Nothing

0A

12.2.11 REAR L BOARD

Application ETC
( S/N) Date)
332-02-012- Nothing
1A

12.2.12 REAR M BOARD

Application ETC
( S/N) Date)
332-02-011 - Nothing
1A


12.2.13 REAR R BOARD

Application ETC
( S/N) Date)
332-02-010- Nothing
1A

12.2.14 UPDOWN B/D

Renewal date : 2000-10-13 Final Version : 0A Charge Person : KIM JONG GU
Application ETC
( S/N) Date)
332-02-022- Nothing
0A

12.2.15 V/M B/D

Renewal date : 2000-10-13 Final Version : 1A Charge Person : CHA JAE YONG

Application ETC
( S/N) Date)
332-02-007- Output INTERLACE green Raise #7pin of U34, U37 Changing RGB 565 FORMAT to be Nothing
1A and connect with #7pin of transmitted from AL251 to RGB DC
U35 666 FORMAT.
“ Appear the color ont Nothing Changing XC95144 FILE and Nothing
OVERLAY changing IC TYPE of KEYING DC
PART 74LVC245 : 74LVC245 à
74LV245
(Notice : Changed FILE

XC95144 FILE apply just specific
LOT
MF2000062100725_A060800**
“ Appear white sparkle spot “ Changing XPOST_HDO FILE “
on IMAGE
“ Shake the IMAGE “ Removing R451(220OHM), “
R452(330OHM)
“ Appear line sparkle on H “ Changing XZOOM FILE “
direction.

Appear dot when execute “ Changing VM__PGM.HD0 “

3D Rendering
Appear purple color line “ Changing XPOST_HD0 FILE “
sparkle on the lower end
of IMAGE
12.2.16 SOFTWARE HISTORY

Renewal date : 2000-11-11 Final Version : 1.0.0.530 Charge Person : KIM JONG GU
Application
S/W
Build NO. DC Facts (Problem Facts) DC NO. Equipment ETC
VERSION
(S/N)
1.0.0.529 1. Appear white line on horizontal at Random or problem to be occurred line in Nothing DC
color box at B/C Mode.
è Changing dsc_xmem.hd0
2. Problem to appeared white spot sparkle on image.
è Changing vm_xpost.hd0
1.0.0.530 1.Disappear the image when press Update key constantly. Nothing DC
èChanging Dsc_inctr.hd0
1.0.1.533 1. Changing FM_WCK2( #2pin of U94) of Color Azimuth Interpolator to 00-9900-

FM_WCK3( Occurring diagnostics error) 036

è Changing dsc_ictr.hd1
2. Appear purple color line sparkle on the lower end of IMAGE

èChanging vm_xpost.hd0
3. Get out of the color box(low direction)

è Changing PDSP0.HD0, PDSP0.HD1
Changing PDSP0.HD2, PDSP0.HD3
1.01.00.535 1.Disapplear image 00-9900-

è Changing dsc_xmem.hd0,dsc__pgm.hd0 038

SonoAce9900 Section 2-2. CW Board
2.CW BOARD
The CW DOPPLER MODULE supports two modes (STATIC CW, STEERED CW)
The CW BOARD supports STATIC CW(PENCIL TYPE) and STEERED CW(PHASED ARRAY
PROBE).
PW : Advantage to get the information on location and depth.
PW can measure the stream of specially fixed location by operating TX and RX by same
element.
CW : It is mainly used for continous signal.
Can receive continous ECHO by operating TX and RX by different element.
No information on depth

Static CW
- CW Pulser to drive Transducer.
- RF Pre-Amplifier for receive signal.
- Mixer to change from RX signal to baseband signal with 50Mhz range of right angle
phase.
(0’ and 90’)
- Thump filter (200/2KHz)
- Variable Wall filter (Min. 200Hz)
- Variable gain
- Variable lowpass filter with 1KHz resolution for noise bandwidth performance.
- 16bit analog-to-digital converters
Steered CW
- 16 Channel CW Pulser to drive Transducer.
- 16 Channel RF Pre-Amplifier for receiving signal.
- TX/RX Beamformer for Focusing when transmitting and receiving.
- Mixer for basebend with 50Mhz range of right angle phase(0’ and 90’). To change to
signal.
- Thump filter (200/2KHz)
- Variable Wall filter (Min. 200Hz)
- Variable gain
- Variable lowpass filter with 1KHz resolution for noise bandwidth performance.
- 16bit analog-to-digital converters

2.2.BLOCK DIAGRAM
Doppler Signal
clutter doppler
Over 40dB -. Clutter : Unnecessary signal from below 200
~ 400Hz.
Occurrence at motion like wall of the
heart
CLUTTE
MIXER
Tx Rx RF MP LPF HP Output dev
Oscillator
CW System Block Diagram.

Fo Cos
Tx EL. Pulser
Static
CW
Probe Rx EL. Pre-Amp
Selector
Buffer
(Static or
Fo Cos Steered)
EL. 16 Pulser 16 Transmit
36~51 16CH Focus
Phased
Array
Probe EL. Pre-Amp Receive
14~29 16 16CH 16 Focus
Notch I
De-
Filter Band Modulation Wall/
(Reject Mixer Variable
Carrier & Pass Driver (TAK-3H) Thump Gain
Filter & Filter
some L.O. Driver Q
Clutter)
Fo COS Fo SIN
I 16bit CW Data
ADC
Nyquest
Filter CW I/Q Data Interface CW SCLK
LPF
Q 16bit CW RFS
ADC
Fo COS
System CW Control CW/System Clock
Interface CW PWR Generator Fo SIN
&
Probe Personality 61.600MHz
OSC 8Fo
2.0MHz
XD[0..7] Relay
HV MUX XCLK P-Data

Probe Select Assembly Control
Control
XLD SHS
HV+,HV- Power
CW MODE BLOCK DIAGRAM
Mixer ClutterL
Tx Rx RF AMP LPF HP F
Oscillator
R
90’
LPF HP 90’
Steered CW system Block Diagram

CW
Power Control
0~8 [V]
EL 32 Pulser #0
EL 33 Pulser #1
8Fo
EL 34 Pulser #2
Shift
TX
Resister
MUX
(Delay)
Fo COS
EL 50 Pulser #14
EL 51 Pulser #15
EL 29 Pre-Amp #0
EL 28 Pre-Amp #1
EL 27 Pre-Amp #2
Delay
RX
Line RF-Sig
MUX
(SUM)
EL 15 Pre-Amp #14
EL 14 Pre-Amp #15
Steered CW Beamformer Block Diagram

Port Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
/CW_FO_WR 0x400 TEST CAL /PT_S Scanhead Frequency
ADC_
T CAL
/WALL_WR 0x402 LPF Spare Wall/Thump Filter
H
/LPF_WR 0x404 Lowpass Filter
/GAIN_WR 0x406 Variable Gain
RST 0x408 Tx/Rx Mux(MT8816): Count Reset

STRB 0x40A Tx/Rx Mux(MT8816): Count Clock & Data Write(16Bytes)
Rx-Focus Data Tx-Focus Data
/CWPWR_WR 0x40C CW Power Control

0x40E Spare
/P8254_CS:0 0x410 Doppler PRF
/P8254_CS:1 0x412 Sample Width
/P8254_CS:2 0x414 Test Frequency
/P8254_CS:3 0x416 8254 Mode Control
0x418 Spare
0x41A Spare
0x41C Spare
0x41E Spare
P_CLK 0x420 Scanhead Personality: P_CLK
/P_WR1, 0x422 Scanhead Personality: Write/Read
/P_RD1 Write Not Not Not P_SEL /P_DA P_DAT P_DAT P_DAT
Used Used Used T_OE _C _B _A
Read Spare /PIND_ /PIND_ /PIND_ /P_Fre P_DAT P_DAT P_DAT
C B A eze _C _B _A
/CW_PID_RD 0x424 Front_plane Board ID Pencil Ty pe CW Probe ID
/P_SEL_WR 0x426 HV_R_ HV_M MOD1 MOD0 Spare Spare P_SEL P_SEL
DN UX_E _AB _A
N
HV_RA_CLR 0x428 HV-MUX: RAM Address Count Reset(at Down Load)
HV_R_CNT 0x42A HV-MUX: RAM Count Clock & Data Write(at Down Load)
/BCPWR_WR 0x42C HV Power Control
/CW_VER_RD 0x42E CW Board ID
AD8_RD, HV+/HV-/CW Current/Voltage/Control Sense
0x430
AD8_CS, Not Used ADC Select
AD8_ALE 0x432 SPARE
0x434 SPARE

2.4 Details
2.4.1 LPF(LOW PASS FILTER) & HPF(HIGH PASS FILTER)
T Type Circuit FILTER
∏Type Circuit FILTER
2.4.2 CLOCK DRIVE (61.6Mhz PART)

Use MASTER CLOCK(61.6Mhz) and transfer to DBF,DSC,DSP

2.4.3 TX POWER CONTROL
+12V
R59
D?
U17 DIODE TP1
7
1
OP27
A1-A8 3
+ +BCPCON
6
DAC0808 2
-
T1
D?
4
8
DIODE
-BCPCON
-12V
DAC0808 is OPEN COLLECT type and controls IOUT.

The maximum output Voltage modification range from above diagram will be fixed by the
Voltage that is supplied to #2 and #3 of DAC0808.
IOUT range is also the same as electric current to the VOLTAGE REFERENCE of
DAC0808.
The IOUT is electric current component and change the Voltage through I-V
CONVERTOR.
2.4.4 HV MUX CONTROL

The reason of using KM682578-15 is to save the data about HIGH VOLTAGE and read
whenever it needs for SWITCHING function.

2.4.5 TX FOCUSING
30.8MHZ
3
IO_DATA
8 TXD_LOW
MT8816 SHIFT_REG SHIFT_REG

4
TRMA
TF_8
3
IO_DATA
8 TXD_HIGH
MT8816 SHIFT_REG SHIFT_REG

4
TRMA
TF_8
Tx-Focus executes Focusing the CW Pulse transmitted from Phased Array Probe during
CW mode. The Focus Data is directly loaded to MT8816 according to the location of
Steering Angle and Focus in the Main System. Data is 16 bytes . The LSB 4bit is used
for TX Focus and MSB 4 bit for RX-Focus.
Tx-Focus Data Formats

Delay[ns] TD3-0 Delay[ns] TD3-0
0 0 260.0 8
32.5 1 292.5 9
65.0 2 325.0 A
97.5 3 357.5 B
130.0 4 396.0 C
162.5 5 422.5 D
195.0 6 455.0 E
227.5 7 487.5 F

2.4.5 PULSER
The Pulser on the CW Board is used during CW Mode. There are 1 Pulser for Static CW
and 16 Pulser for CW(Phased Array Porbe). The Pulser is produced by activating 2
DMOS FET through Transformer of Dual MOS Clock Driver.
2.4.6 PRE-AMP
Pre-AMP has the characteristics of Low Noise/distortion. There are 1 Pre-Amp for Static
CW and 16 Pre-AMP for Steered CW. The Output of Pre-Amp for Steered CW is delivered
to MUX of Rx-Focus through V-I Converter.

+10V
16
PROBE C? 16
RX-FOCUS
PRE-AMP
D15 D16
CAP
-10V

2.4.7 RX SWITCHING (SELECT)

After SWITCHING the signal from PRE-AMP, supply a path to Delay line
3 8
RD F_DATA
4
MT8816
RA 16
PA DATA
RD3
OFFPAGELEFT-R
3 8
RD F_DATA
4
MT8816
RA 16
RD4
Rx-Focus Data Formats
Delay[ns] RD3-0 Delay[ns] RD3-0

0 0 240 8
30 1 270 9
60 2 300 A
90 3 330 B
120 4 360 C
150 5 390 D
180 6 420 E
210 7 450 F

2.4.8 POST MIXER FILTER/AMPLITER

There are the second LC LPF to eliminate high frequency and Low Noise Amp of
adequate Gain..
2.4.9 MIXER DRIVE

MIXER DRIVE is the Power Amp(6dB) for activating RF input of Mixer.
2.4.10 MIXERS
After mixing RF signal with L.O. signal, receives Doppler signal of Baseband. mixing I.Q.
TAK-3H I_SIG
L.O.
TAK-3H Q_SIG
2.4.11 BAND PASS FILTER

It is the part to prevent low frequency when a heart is beating.
5
8
AD797
I_SIG,D_SIG L.C 3 -
7
FILTER 2 +
1
4

2.4.12 ADC(ANALOG DIGITAL CONVERT)

ADC(ANALOG DIGITAL CONVERT) is the part to convert analog signal to digital signal
by AD-CONVERT after using the input from I_ADC, Q_ADC. The AD586 of this part is an
element to generate REFERENCE voltage. The output of power is about 5v.
I_ADC AD677 I_ADC_D
I_ADCLK
Q_ADC AD677 Q_ADC_D
Q_ADCLK
VOLTAGE
REFERANCE

2.5 Timing Chart

2.5.1 I,Q DATA Signal Process

2.6 Wave Form

2.6.1 TP:U112 Pin-8
V(P-P) ≒ 5V
Cycle : 16.23376623ns
2.6.2 CH1 TP: : /E_TRG CH2 TP:/EX_TRG
(CH1) : /E_TRG
V : 2.7V (P-P)
(CH2) : /EX_TRG
V : 5V (P-P)
2.6.3 CH1 TP: : /CWPRF CH2 TP:/4Fo
CH1 : /CWPRF(TP20)
CH2 : /4Fo
CH1 TP: :TP20 CH2 TP:TP27 CH1 TP: : TP20 CH2 TP: TP21

2.6.4 CH1 TP::TP20 CH2 TP:TP19
2.6.5 CH1 TP: TXP0 CH2 TP:/TXPO CH1 TP: U94 Pin-5 CH2
TP:U94 Pin-7
2.6.6 CH1 TP: CWTXO CH1 TP: TP6 CH2 TP:TP9

2.6.8 CH1 TP: TP8 CH2 TP:TP11 CH1 TP: TP14 CH2 TP:TP15
2.6.10 CH1 TP: TP20 CH2 TP:U39 Pin-14 CH1 TP: TP20 CH2 TP:U48
Pin-14
CH1 TP: TP20 CH2 TP:U39,48 Pin-2

SonoAce9900 Section 2-3. DSC Board
3. DSC BOARD
DSC receives the input from the DSP board(Echo-processor) and send image data to VM to
match video signal after 2D scan conversion. The input data format is BW 8 bits, color 16 bits
and output data is respectively 8 bits in the BW, Color, ECG. In case of Input, the BW means B,
M, D data and color means 2D color, color M data. ECG sends the input from the DSC board
to VM. The ECG uses new data bus from the output because it can be overlapped with B, M, D.
The management of signal from DSC input to DSC output is as following
Order
BW input -> Input SSRAM -> AI (Azimuth interpolator) -> FA (frame

2D average) -> FM (Frame memory),Cine -> Fifo -> FI (Frame interpolator) -
> VM input
Color input -> Fifo -> Color pixel interpolator -> AI -> FA & compare ->
Color
FM,Cine -> Fifo -> FI -> VM input
M,D BW input -> Loop fifo -> FM (Frame memory),Loop -> FIFO -> VM input
Color M Color input -> Fifo -> FM, Loop -> Fifo -> VM input
ECG ECG input -> A/D -> DSC DSP -> FM -> Fifo -> VM input

- Board Main Clock : 61.6Mhz
- DSP Input Clock : 20.53MHz(divide in FPGA by 3)
- Cine memory : 256 frames (dual cine mode application-128frames)
- 64Mbytes module RAM
- 256*512*512 = 64M
- Loop memory : 2048 size
- Frame memory : 256K * 4, SGRAM.
- Graphic is not available.
- BW resolution : 8bits 256 level
- Color Data : 16bits, Velocity is 2's complement format
Mode High (15..8) Low (7..0)
Vel Vel 7..0 Pwr7 .. Pwr0
Var Vel7, Var6..Var0 Pwr7 .. Pwr0
Power Vel7, Pwr6..Pw1 Pwr7 .. Pwr0
VelVar Vel7..3, Var2..Var0 Pwr7 .. Pwr0

Angio 0, Ang6..Ang0 Pwr7 .. Pwr0
- Color Code Generation : The Data format is 2'complement format and saved to frame
memory. It changes to signed magnitude in FI. The final result to be transferred to VM will
be remained as signed magnitude.
Input Output
DSC 2's complement
azimuth interpolator 2's complement 2's complement
Frame average 2's complement 2's complement
Frame interpolator 2's complement signed magnitude
DSC signed magnitude
- Azimuth interpolator : 8 by 8 bits interpolation,

- In case of Color, the High and Low side will be done separately and configure the FPGA
per
Color Mode.
- Frame Average : 8 by 8 SRAM LUT.
- Part is two. It uses to bypass first frame, when capture clear the high one part or start real.
- SRAM is connected to PC data bus and new down whenever changing FA factor
- FI mux : 4 by 2 mux, selection 2bits
- Maximum sampling clock : 61.6MHz
- Color pixel interpolator

3.2 BLOCK DIAGRAM
It controls the memory Controller and Input SSRAM Controller, so it generates the address
and many control signal of Frame Memory, Line Memory, Cine Memory.
It generally controls the Signal Path of the DSP board as the standard of the Hsync
Interrupt and OF interrupt Input SSRAM comes to Video Manager through Frame
Interpolation. It generates the data of SCG and XY angular, that data reads from the
Sin/Cos, Arch Mask ROM. And then writes XY data on XY Memory. Finally, RTC DSP
writes data to be received by serial on SCG Memory when SCG Data sent to serial
communication at TRC DSP.
DSC DSP &

SSRAM RTC DSP &
MEMCTR FPGA &
Memory pool FPGA
INPUT FPGA
INPUT FA &
DATA(B,C) AZIMUT
COMPAR
Latch H MISC,FI-
E OUT FIFO
- Buf INTERP MUX
(SRAM
OLATOR
LUT)
FA
FIFO
(SGRAM FMB,C FIFO
) CINE CINE TO
PCI
INPUT
DATA(M,D,C
M) OUT FIFO,
FIFO LOOP FM
ECG FIFO
ECG A/D


Name Add Explanation
B SSRAM write low address (9bits)
P_ssram_waddr_b_l 0x10 Real : Start address
Down : rd/wr address
P_ssram_waddr_b_h 0x11 B SSRAM write high address (9bits)
C SSRAM write low address (9bits)
P_ssram_waddr_c_l 0x12 Real : Start address
Down : rd/wr address
P_ssram_waddr_c_h 0x13 C SSRAM write high address (9bits)
This port is valid in real mode only.
P_ssram_wr_ctr 0x14 B0 - 0 : Odd write, 1:Even write
B1 – 0 : B write, 1: C write
P_ssram_access_ev_b 0x08 B even SSRAM access port (RD/WR)
P_ssram_access_od_b 0x09 B odd SSRAM access port (RD/WR)
P_ssram_access_ev_c 0x0a C even SSRAM access port (RD/WR)
P_ssram_access_od_c 0x0b C odd SSRAM access port (RD/WR)
Bit0 : DQM0
P_DQM_Sel 0x10
Bit1 : DQM1
Bit0: 1-Real, 0-Down
Real : DSC and DSP will port out inside of OF
P_real_down 0x0f
blank.
Down : Port out if Freeze flag is “1”.
XY clock enable
B8 : Down mode B Clock enable
P_sg_cke 0x51
B9 : Down mode C Clock enable
In case of Real, the clock enable is always “1”.
P_ sg _cmd 0x58 DSP down mode command
P_ sg _addr 0x59 DSP down mode add
P_ sg _access 0x5a DSP down mode access
Real acquision y line number , Sharing Port with
P_SG_YSTART 0x43
MemCtr
Real mode XY SGRAM read enable
B0: 1-Enable , 0-Disable
P_sg_real_ren 0x4a
Port sharing with MemCtr
If enables it, it moves to one line and automatically

disabled. DSC and DSP will accurately function

if port out in the range of HS à 0.
P_Testport 0x1f Test port

P_Reset 0x7f Port sharing with MemCtr, Bit 0 : active high
H800 –
B_PBUS_EN Port Bus enable
H9FF
P_RTC_DNLD H800 RTC DSP Download
P_RTC_IWR H802 RTC DSP I/O WR
P_RTC_IRD H802 RTC DSP I/O RD
H802 –
P_RTC_ICS RTC DSP I/O CS( chip select )
H804
P_PRTC_IAL H804 RTC DSP I/O AL( Address Latch )
P_DSC_DNLD H806 DSC DSP Download
P_DSC_IWR H808 DSC DSP I/O WR

P_DSC_IRD H808 DSC DSP I/O RD
P_DSC_ICS H808-H80A DSC DSP I/O CS( chip select )
P_DSC_IAL H80A DSC DSP I/O AL( Address Latch )
P_real_cpumd H80C REAL MODE/CPU DOWN MODE
P_FABW_WR H810 BW FA Download à WR( SRAM)
P_FABW_OE H812 BW FA Download àOE
P_FACD_WR H814 Color FA Download à WR( SRAM)
P_FACD_OE H816 Color FA Download à OE
P_FIBW_WR H818 BW FI WR( FPGA )
P_FIBW_OE H81A BW FI OE( FPGA )
P_FMCCMP_WR H81C FMC Compare WR( SRAM )
P_FMCCMP_OE H81E FMC Compare OE ( SRAM )
P_RAM_OE H820 Compare RAM OE( SRAM )
P_ADDR_HWR H822 SRAM Address
P_SLTFA H826 FA Look-Up Table
P_CDFIMUX_EN H828 Color FI MUX Enable
P_FACD_RAMOE H82C Color FA RAM OE
P_STS_RD1 H830 DSC Status RD2
P_XBWRADI_WR H832 BW FI MUX FPGA WR
P_XBWRADI_RST H834 BW FI MUX FPGA Reset
P_XCDRADI_WR H836 Color FI MUX FPGA WR
P_XCDRADI_RST H838 Color FI MUX FPGA Reset
P_XCDPXLI_WR H83A Color Pixel interpolator FPGA WR
P_XCDPXLI_RST H83C Color Pixel interpolator FPGA Reset
P_XMEM_WR H83E Memory Controller FPGA WR
P_XMEM_RST H840 Memory Controller FPGA Reset
P_XRTC_WR H842 RTC FPGA WR
P_XRTC_RST H844 RTC FPGA Reset

P_XFICD_WR H846 Color FI FPGA WR
P_XFICD_RST H848 Color FI FPGA Reset
P_XINCTR_WR H84A Input Controller FPGA WR
P_XINCTR_RST H84C Input Controller FPGA Reset
P_XFIBW_WR H870 BW FI FPGA WR
P_XFIBS_RST H872 BW FI FPGA Reset
P_SYS_VER_RD H850 System Version Read
P_STS_WR H854 DSC Status WR
P_STS_RD2 H856 DSC Status RD2
P_RTC_READY H850 RTC DSP Ready (Handshaking)
P_DSC_READY H862 DSC DSP Ready (Handshaking)
P_RTC_ECHO_CLR H864 RTC DSP Echo Clear( Handshaking )
P_DSC_ECHO_CLR H866 DSC DSP Echo Clear( Handshaking )
P_CINEFF_BW_OE H8F0 BW CINE FIFO OE (when 3D Operation)
P_CINEFF_CD_OE H8F4 Color CINE FIFO OE (when 3D Operation)
3.3.1 Pin Description
Name Width,type Explanation

Data 11,I/O DSP data
Addr 8,I DSP address
/WR 1,I DSP WR
/RD 1,I DSP RD
/IOMS 1,I DSP IOMS
Dclk 1,I DSP clock out
/OF 1,I OF
/BEADC 1,I BEADC
/CEADC 1,I CEADC
Rclk 1,I Real clock (61.6MHz)
Dot_clk 1,I Dot clock (used at writing)
HS 1,1 HSync

P_DATA_LCH 1,O Previous data latch clock

FM_WR_Clk(C_DATA_L Current data latch clock & RD main clock
1,O
CH) FM write clock (61.6/2 MHz)
SS_RD_Start 1,I SSRAM read start flag (active high,from MemCtr)
FM write start flag (active high)
FM_WR_Start 1,O P_Data_LCH and FM_WCK are available after
FM_WR_Start is “1”.
/B_SS_WEn 1,I Sampling write enable
/C_SS_WEn 1,I Sampling write enable
XY SGRAM Total 60
XY_ADDR 11,O XY SGRAM address
XY_Cmd 4,O XY SGRAM command
XY_CKE_B 1,O XY SGRAM clock enable
XY_CKE_C 1,O XY SGRAM clock enable
XY_CK 1,O XY SGRAM clock
XY_B_Data 18, I/O XY SGRAM B data (ssram address)
XY_C_Data 18, I/O XY SGRAM C data (ssram address)
XY_DQM_B 1,O XY SGRAM DQM
XY_DQM_C 1,O XY SGRAM DQM
XY_DEN_BL 1,O Data enable (Down load path)
XY_DEN_BH 1,O Data enable (Down load path)
XY_DEN_CL 1,O Data enable (Down load path)
XY_DEN_CH 1,O Data enable (Down load path)
SS_E_Addr_B 18,O Input SSRAM Even address
SS_O_Addr_B 18,O Input SSRAM Odd address
SS_E_Addr_C 18,O Input SSRAM Even address
SS_O_Addr_C 18,O Input SSRAM Odd address
SS_E_CK 1,O Input SSRAM Even clock
SS_O_CK 1,O Input SSRAM Odd clock
SS_E_ADSC 1,O Input B,C even SSRAM adsc
SS_O_ADSC 1,O Input B,C odd SSRAM adsc
SS_B_E_GW 1,O Input B SSRAM write enable
SS_B_E_OE 1,O Input B SSRAM Output enable
SS_B_O_GW 1,O Input B SSRAM write enable
SS_B_O_OE 1,O Input B SSRAM Output enable
SS_C_E_GW 1,O Input C SSRAM write enable
SS_C_E_OE 1,O Input C SSRAM Output enable

SS_C_O_GW 1,O Input C SSRAM write enable

SS_C_O_OE 1,O Input C SSRAM Output enable
3.4 Details
3.4.1 Input Controller
Input Controller Part controls the Input SSRAM and XYI Memory. The Input SSRAM is
used for input of 9900DSC and XYI Memory has the value of DSC data generation. So
the structure of FPGA(XCS30XL-PQ240) is mainly composed of SSRAM and SGRAM.
3.4.1.1 Input SSRAM Control
Even_Addr
WRITE ADDRESS
(LOADABLE
COUNTER)
READ RD
ADDRESS MUX
Odd_Addr
(SGRAM)
Input control FPGA
INPUT DATA
BUF
Even_Addr
EVEN
BUF
B SSRAM
AZIMUTH
BUF
INTERPOLATOR
Odd_Addr ODD
BUF
B SSRAM
BUF
Even_Addr EVEN
BUF
C SSRAM
BUF
Odd_Addr ODD
BUF
C SSRAM
As above B/D shows that the SSRAM uses BW * 2ea and Color * 2ea. Both B and C are
consisted of Even and Odd. Because of there should be basically the information on one
Frame for the direction of Hsync, when writing in the F.M. So, one Frame is written on
SSRAM. By the way, the reason to divide into Even and Odd is that SSRAM is not Dual

Port so that can not Read and Write at the same time. When Even SSRAM Writes, Odd
Reads. The reverse is true. That is to say, it is pingpong structure. To operate like this,
Even or Odd should use one Frame. So, Read should not be operated before one Frame
is full. As above process, Input SSRAM Control Part makes Control
Signal(WE,OE,ADSC..), Clock and Address for SSRAM.
3.4.1.2 XYI Memory Control ( SGRAM )

XYI Memory is connected with DSP. After the DSC DSP execute Data Generation of
Geometry for each Probe, Mode, Depth, it stores angular coordinates of Memory and
Azimuth interpolation vector(I) into XYI Memory. During Input SSRAM Read in Real
condition, data of Azimuth Interpolation can be read by Input SSRAM Read Address. And
the coordinates stored XYI Memory should be read in the input controller. The input
controller controls XYI Memory by these processes. .
3.4.2 Azimuth/Pixel/Frame Interpolator
3.4.2.1 Azimuth interpolator( BW&Color )
Even_D
(D0-D7)
Even SSRAM
Azimuth RIBW_D
Interpolator (D0-D7)
Odd_D (XCS05XL-VQ100)
(D0-D7)
Odd SSRAM
Addr BW_INTP
(0-4)
Pre, Curr
Input Control Addr(18bit) XYI Memory
(XCS30XL-PQ240) ( LUT )
As Fig.1 shows, Previous SL0( A ) and Current SL1( B ) multiplied with interpolation
vector in the XYI Memory is Azimuth Data( Z ). The process is as following. When the
SLO data which is read at input SSRAM latches onto P_DATA_CLK and DATA B of SL1
latches onto FM_WCK, the data Z is output by azimuth interpolation of DATA A and B at

the same time. During Azimuth interpolation, CLK is 61.6MHz. Because previous Data
and Current Data are handled simultaneously, the Output is 61.6MHz/2. That is to say,
one Interpolation Data(Z) comes to be output for 30.8MHz.
A
Z INTERPOLATION DATA
SAMPLING DATA
B
Prev SL0
Current SL1
Fig.1. Azimuth Interpolation
The Factor uses 5bit. Because color mode not B-mode has a cipher, the Factor should be
interpolated in consideration of the cipher. The new data is downloaded according to
Color mode. The same FPGA is used during Velocity, power, Variance mode. Otherwise,
different FPGA is used during Vel/Var because composition of bit is different.
3.4.2.2 Color Input & Pixel Interpolator

After CRP happens in the DSP board, Color input executes Port out(/CD_RST) the reset
of FIFO1. Afterward, writes onto FIFO 1. (/CD_WR). The end signal is sent after Writing.
(/CD_END). The RTC Controller(9572XL) sends /CD_RD_FLAG to 1 if it can recognize
END. The DSP board sends data only if /CD_RD_FLAG is zero, not 1. The RTC DSP
reads /CD_RD_FLAG in the PRF interrupt, and if that result is “1”, clear to “0”. Afterward,
it ports out FIFO1 read enable. (FIFO1 read enable signal is disable at the beginning of
PRF interrupt. So, it is clear from the start. ). This signal and /BEADC are masked. Data
passes pixel interpolation at FIFO1 and is used at FIFO 2. After reading the data at FIFO
1(FF1_ENDLN_OUT? 1 ), /STT_CD signal happens from the RTC FPGA. The DSC
recognizes this signal and the process of color 1 line is over by transferring FIFO 2 data
into FMC. The Fig 2 shows color input timing.

/PRF
/CRP
/CD_RST
/CD_WR
/CD_END
/CFF1_WR
CFF_ENDLN
RTC CLEAR
/CDRD_FLAG
/BEADC
/CFF1_RD
CFF_ENDLN_OUT
/STT_CD
Fig. 2.color input timing

.
The role of pixel interpolator is to give 440 color pixel data in the DSP B/D. If so, it is hard to get
good image after interpolation because there are few data during the color azimuth interpolation.
For that reason, 440 Color pixel are made to data by interpolation necessary at azimuth
interpolation. The Factor is 4bit and dependent only in Color.
color
scanline 0
A
INTERPOLATION DATA
z0
SAMPLING DATA
z1
Fig.3 Pixel interpolation
3.4.2.3 Frame Interpolation

The Frame Interpolation(F.I) is to interpolate one Frame with the other Frame. The
reason to execute frame interpolate is that the gap between present Frame and next

Frame is so large that the image is not good.
The DSC interpolates by four Frame with FIMUX connected.

The table below is regarding FI.
PFI_SEL (0x8f) port
0 : A, B
1 : B, C
2 : C, D
3 : D, A
FI_FM_Sel
Write FM Read FM FI_Sel
(Internal Variable)
0 A (DQM 1110) C,D 2
1 B (DQM 1101) D,A 3
2 C (DQM 1011) A,B 0
3 D (DQM 0111) B,C 1
Table. FI_Selection Table
As the table above, by Read FM we can know which Frame is interpolated. The selection
of this Frame is determined by FI_Sel.
F.M
F.M0
( A )
A
F.M1
( B )
A
Z
F.I MUX (interpol
( 4 * 2 )
F.I ation)
F.M2
( C ) B
F.M3 F I _ S E L 0, 1?
( D ) " 00 "? ?
Fig. 4 FI Block Diagram

Condition: present Frame Rate(F.R) is 30Mhz.

Because VSYNC is 60Hz, DSC DSP gives FI Vector for one FI. Then the FI_SEL(0,1) is
“00” and give Frame A and Frame B to F.I input in the F.I MUX. The next F.I makes Frame
Z by interpolating Frame A and Frame B. Output one Frame for each VSYNC like A à Z
à B.
3.4.3 FI MUX
TMP_ABWSD
(D0-D7)
FABW_D
(D0-D7)
Frame 1* 4 Demux (Wr) TMP_BBWSD
FIFO
Average 4 * 2 Mux (Rd) (D0-D7)
Fm
_W
FMB_D
r
(D0-D7,
d
FM_R
D8-D15,
D16-D23,
D24-D32)
FM
Fig. 5 FI_MUX Block Diagram

The role of FI_MUX is to switch required Frame during FI. Because the data of FM used
now is 32 bit and 8 bit is used for one Frame, 4 Frame could be stored at FM. The 1*4
Demux of FI_MUX operates this function(WR). The 4*2 MUX(RD) has the role of sending
only two Frame of four Frame. The 4*2 MUX(RD) is controlled by FI_SEL. The Frames
selected by FI_SEL control are explained at the FI_Seletion Table.
3.4.4 Memory Controller Part

Memory controller handles Cine memory, FM memory , line memory. It also transmits the
data to VM according to Video signal after DT.
3.4.4.1 Structure of Memory Controller

♦ Decoder : Latch to have the information on Decoder and operation condition.
♦ Mode_CTR : To control State Diagram of Mode.
♦ SGIO_CTR : DSP SGRAM Read/Write.
♦ DT_CTR : DT.
♦ Loop_CTR : Loop Acquisition.
♦ Real_CTR : BC Acquisition.
♦ Cine_CTR : Cine Transfer to FM.

3.4.4.2 Function of Memory Controller

♦ One line Acquisition
Input SSRAM or loop FIFO(M.D) transfers to FM by the standard of HS. If HS becomes
low, DT is carried out at first. And checks if SttBW is active. SttBW becomes active
when there is data at Loop FIFO. The DSC DSP recognizes the signal of SttBW and
Real flag is set. (Port num : 0x0B bit 0). This flag is automatically free when recognizing
the Line End signal. For this reason, DSP always should be set before managing the
new line. If SttBW is not active, B, Color information of Input SSRAM is sent to FM. After
sending the signal(SS RD Start) to move to FM, wait until FM WR Start. If FM WR Start
is active, delay FM WR Start to some extent by Flip Flop until data comes. Afterward,
start to be written onto FM from column 0. After all 512 are written, SS RD Start
becomes inactive.
♦ Memory Selection
Memory selection is made by controlling DQM and CKE. The DQM controls the
movement to FM in Real Mode because of Frame Interpolation. The CKE is used to
select Memory according to Acquisition mode. As the table below, DSP is the value for
DSP to port out.
DQM(0x50)
Real DT Cine Line_TC
F All 0 DSP port

DSP DSP
M0..3 (active) out
Li All 1 All 1
DSP DSP
ne (inactive) (inactive)
CKE(0x51)
Real DT Cine Line_TC
F DSP and All 1

DSP DSP
M0..3 real pattern (inactive)
Li All 1 All 1 All 0

DSP
ne (inactive) (inactive) (active)

3.4.4.3 Address generator

♦ FM address
Source : DSP(reg_sgio), DT(dt_ctr), Real(fm_ctr) , Cine(cine_ctr)
Each of them is composed to tri-state buffer, not using mux to increase speed.
♦ Sweep(loop) address
Source : DSP(reg_sgio), DT(dt_ctr), Real(fm_ctr)
Sweep address is the same with FM address except DT . Cine address doesn’t exist
because loop has no cine memory. It is composed of tri-state like FM.
♦ Cine address
Source : DSP(reg_sgio), Real(fm_ctr) , Cine(cine_ctr)
Same with FM address . no address about DT.
♦ Line address
Source : DSP(reg_sgio), Real(ln_ctr)
3.4.4.4 Command generator

♦ FM command
Source : DSP(reg_sgio), DT(dt_ctr), Real(fm_ctr), Cine(cine_ctr)
Each is composed of tri-state buffer, not using mux to increase speed.
Sweep command and cine command use FM command together, not existing
separately.
♦ Line command
Source : DSP(reg_sgio), Real(ln_ctr), DT(dt_ctr)
Refresh command is generated from DT.
3.4.4.5 OP(Operation) Mode

♦ Operation mode is set by bit 0, 1 from 0x44 port.
00 : DSP mode (default)
01 : Real (BC acq) mode
10 : Loop acq.
11 : Cine mode
Real mode and cine mode are completed when column address is 512. Loop mode is
completed after recognizing Loop_Ln_End. After each mode is over, it is sent to DSP
mode automatically. Cine mode transfers one row like real mode, not one Frame.

MAINCLOCK : 61MHz
30us
512/61.6 = 8.3us 512/61.6*2 = 16.6us
DT & LINE FIFO WRITE REAL (61.6/2MHz) RESERVED
OP_DT
OP_REAL
Fig. 6 OP DT Timing
LOOP END
NO FLAG SET
POWER-ON RST /HS LOOP FLAG

OR DSP DT LOOP
DSP RESET
/HS
BC ACQ
FLAG CINE
BC ACQ FLAG
END
CINE
REAL
CINE END
Fig. 6 OP Mode State Machine Diagram

3.4.5 DSC DSP

♦ DSC DSP controls Memory Controller and Input SSRAM Controller and makes Address
and various kinds of Frame Memory, Line Memory, Cine Memory.
♦ It also controls the Signal Path of DSP board by standard of Hsync Interrupt and OF
interrupt before sending data from Input SSRAM to Video Manager through Frame
interpolation.
♦ It generates XY coordinates and SCG by Data to be read data from Sin/Cos, Arch Tan
Mask ROM. The XY data is written onto XY Memory and SCG data is sent to RTC DSP
by Serial . Then, RTC DSP writes the data to be received serial onto SCG Memory.
3.4.5.1 DSC DSP FLOW_CHART
DSC DSP flow_chart( Real Acq )

Real Acq
y
Acq_Done = 1
n
STT_BW , STT_CD = 1 n
y PDOP_SET <= OP_REAL
BC_Row + 1
STT_BW , STT_CD = 0
y
BC_Row < g_bybottom
PDOP_SET <- OP_LOOP n
Acq_Done=1
M
Check LineType
D RTS
DYStartY <- D_Row DYStartY <- M_Row
PDXStart <- XSyncCount

XSyncCount + 1
n
XSyncCount < LoopSize
y
XSyncCount = 0
y
XSyncCount < 511
n
DT_LooPStartY =
DT_LooPStartY =
XSyncCount + LoopSize -511
XSyncCount - 511
RTS

3.4.6 RTC DSP

3.4.6.1 Functions of RTC DSP
♦ HOST Interface:
- receiving the cycle of PRF, EADC, PIXELCLK, DOTCLK, XSYNC, EDFDLY,
ECGSYNC from Host.
- sends the condition of RTC FPGA and Sequence to Host.
Receive the Sequence of Operation of Each Mode.
- receives operation Sequence of each Mode from Host.
♦ Sequence Change:
- carries out Sequence table and specific Mode transmission.
- reads send data and register data and is controlled by RTC FPGA.
♦ RTC FPGA Control
- Post Out to RTC FPGA various data.
- sets register of RTC FPGA by determined value.
RTC(Real Time Controller) makes standard signal for whole system operation in real
time and controls system operation.
BF(Beam Former), DSP, PRF for V/M(Pulse Repeat Frequency), OF(One Frame),
RP(Rate Pulse), Line Type, Scan Line are made and controlled.
In addition, it has the role of making signal to control data stream in the DSC board
internally.
It makes the various standard signal essencial to system operation because PC is the
main Host and controls FPGA by DSP. Because these standard signals are used for
whole system operation, it should be easy to control and operated according to basic
frequency. RTC is composed of DSP and RTC FPGA. DSP part is commanded by
HOST(PC) and carried out. Or receives Sequence(operation order for each mode) at
the form of table and makes progress. And controls cycle of each signal by register
setting of FPGA. FPGA is commanded by DSP and makes a real signal.

3.4.6.2 RTC BLOCK DIAGRAM
RTC-DSP
Host Interface
(ADSP2181)
LineType
Scanline
/prf
/OF
61.6Mhz /RP
HSYNC /CRP
/EOF RTC-FPGA /DRP
CWPRF /ETRG
dotclk
pixelclk
/EADC
xsync
ecgsync
Fig1. Overall Structure of RTC
3.4.6.3 Structure of RTC-DSP

♦ Command Process
It receives Command and Data from HOST and the definition of the Command and
Data will be described in the RTC-DSP Command List of Appendix A. There are three
parts on the Command list.
st
The 1 part is RTC Control Signal generation part,
nd
The 2 part is receiving data for port out to RTC FPGA, and
rd
The 3 part is Command for DSP debugging purpose.
♦ PRF Process
If interrupt occurred by /PRF signal from RTC FPGA, the PRF Process will function. In
this part, it controls overall data flow to be processed whenever the PRF interrupt
occurred.
If the PRF interrupt occurred, it assigns Scan Line and Line Type to be occurred next
step, the frequency of PRF, /EADC, and /RP. And, prepare to the values for next PRF.
♦ Set Port Value

It assigns proper value per each Mode among the transferred values from the Host and
preparing value transfer to RTC FPGA. It should assign proper value to the applicable
port that is presented by Port Map List per each PRF.

♦ Port Out to FPGA

It is the part to transmit the assigned value from the Set Port Value block to RTC FPGA.
♦ Set Next Sequence

The problem part of Sequence is the B-C Mode. It does not generate PRF regularly as
Scan Line sequence like B-mode of Color. It generates to interleave several scan lines
for color ensemble at velocity. This sequence is generated at host(PC), and transmit to
internal memory of RTC -DSP as table shape. RTC -DSP generates sequence according
to transmitted table. And it is assigned U-Table about BC-mode, M-Table about M-mode,
D-Table about Doppler-mode. So it makes PRF according to Sequence Table about
each mode. In this case, the most complex thing is U-Table to include color. So,
following is composition of the table and generation process of real sequence.
<U-Table>
LineType ScanLine Count tmpcount offset
OF 3 3 0
B 0 2 2 0
B 4 2 2 0
B 8 2 2 0
C 12 4 4 +1
C 16 4 4 -1
B 12 2 2 0
B 12 2 2 0
C 20 4 4 +1
C 24 4 4 -1
B 20 2 2 0
B 20 2 2 0
END_LINE
Below table show sequence to generate at U-Table. We used offset to embody

Interleave. Namely, if offset is zero(0), repeat as value to be assigned at count from the
line. After Tmpcount value is zero(0), pass the next line. If offset is +1, progress the
pointer forward as 1. If offset is –1, regress the pointer backward as 1. Make the
Interleave like that method.
<U-Table Sequence List>

LineType ScanLine count tmpcount Offset

OF 3 3 0
OF 3 2 0
OF 3 1 0
B 0 2 2 0
B 0 2 1 0
B 4 2 2 0
B 4 2 1 0
B 8 2 2 0
B 8 2 1 0
C 12 4 4 +1
C 16 4 4 -1
C 12 4 3 +1
C 16 4 3 -1
C 12 4 2 +1
C 16 4 2 -1
C 12 4 1 +1
LineType ScanLine count tmpcount Offset

C 16 4 1 -1
B 12 2 2 0
B 12 2 1 0
B 12 2 2 0
B 12 2 1 0
END_LINE
♦ Change Sequence Table

After checking the stipulation of each PRF, changing of each sequence table is
organized to State hange form. Following diagram show each transfer stipulation and
possible process.

Fig. 7 Sequence Table
seq_Utable
&
le f l a g
lt=1
_
u
me x s y n c
sim
nab
&
&
ist
xist
t
ist
exis
ex
_ex
_d_
_b_
_b_
_m
seq_Mtable seq_Dtable
State Diagram of Sequence Table

Variable
Init.
Host
command
process
No
PRF Interrupt ?
Yes
Prf Process
Set Port Value
Port out to PLD
Set Next Sequence
Change Sequence Table
Flow chart of RTC-DSP

3.4.7 RTC FPGA

3.4.7.1 RTC
All commands are sent from RTC -DSP, and are written at internal register. The function of
each command is defined in port map table. First, Tprt and Xprt must make reference
signal. It is made by counter MCLK(61.6MHz). And all signals are made synchronous to
MCLK. Next, Dotclk and Pixelclk are made Peroid to be sent from TRC-DSP. RTC signals
must be made carefully, because it is used reference signal in system. Each signal is made
synchronous to Master Input Clock. Input Master Clock is 61.6Mhz, and it is made
20.53MHz system master clock to divide it by 3.
3.4.7.2 Structure of RTC FPGA

u DSP interface
Data to receive from DSP write data that it will send to Port map table of inter Register
or Host.
u PRF
Xprf_n makes system clock, prf period is made from DSP.
Xprf_n makes tprf_n, prf blank period is made from DSP.
u dot_pixel_clk
Dot_clk is made from system clock and div_dotclk.
Pixel_clk is made dot_clk and div_pxlclk value.
u sweep_rate, xsync
Make sweep rate signal and xsync signal
It is made with input clock and delay value from Hsync.
Following diagram is structure of RTC FPGA.
Make
/xprf,
/tprf
/tprf
/xprf
Make
dotclk
dotclk &
pixelclk
pixelclk
DSP Make
from DSP Interface /eadc /eadc
Make
xsync & xsync ..
ecgsync
sttbw
from SCGRAM SCG control
ffwen
Structure of RTC FPGA

3.4.7.3 Functions of RTC FPGA

♦ PRF, RP, CRP… Reference signal Generation
♦ dot_clk, pixel_clk generation
♦ EADC, sttbw, sttcd generation
♦ Generation of DSC Sampling Clock
♦ XSYNC, ECG TRIGGER, UPDATE.SWEEP RATE
♦ CLOCK DEVIDE(MCLK/2,MCLK/3=20M, DOTCLK,PXLCLK )
3.4.7.4 Port map of RTC FPGA

♦ PRTC_CTR : Using to ON/OFF of main signal.
♦ PSCG_CTR: Using to ON/OFF of SCG signal.
♦ PEXT_SEL: Using to select of PRF signal.
♦ PPRF_PERIOD: Period of PRF signal.
♦ PPRF_BLANK: Length of PRF Blank
♦ PEADC_DELAY: Starting point of EADC
♦ PEADC_ENABLE: Length of EADC signal.
♦ PSCANLINE: Number of Scan Line
♦ PLINETYPE: Kind of Scan Line
3.4.7.5 DSP Interface

Following is structure of part to receive data from DSP. There are two registers part. So,
they store data to be transmitted from DSP. And, when PRF changes, transmit data to
all internal register. Therefore all internal registers are changed synchronous with every
PRF. The whole movement is stabilized to match PRF, because we selected this
structure.
SPRF_n
MUX /TPRF
MCW_prf_n
MUX
DSP_D[15:0]
TPRF
/PRF_WIDTH_CS GENERATION
16BIT CNT
MCLK
SECTORMD
CWprf_sel
/PRF_BLANK_CS XPRF xpf_n

GENERATION
/TPRF 16BIT CNT
RPEN
DSP_D[15:0]
CRPEN
FIREEN
LATCH LATCH LSTPRF
FSTPRF
/PRTCTRCS0 FSTRP
LSTRP
/TPRF
DSP_D[15:0]
BWWRON/OFF
CDWRON/OFF
LATCH LATCH
LPMDON/OFF
LPCMON/OFF
/PRTCTRCS1
/TPRF
DSP Inteface of RTC-PLD

3.4.7.6 PRF
61.6MHz
20.53MHz
=MCLK
prf period
/tprf
prf prf
blank blank
/xprf
Firing Start
eof_n
etrg_delay
/etrg_dy
focusing start
/prf
eadc enable
/eadc eadc
delay
Timing Diagram of Main Signal
Fig 8. Timing
Fig8 show timing relation of PRF and EADC to be main signal. First, receiving system
clock of 61.6MHz and making MCLK(Master Clock) of 21.25MHz to divide it by 3. Next,
it determines reference clock of RTC_FPGA. It makes reference /tprf and /xprf
according to PRF Period value to be transmitted from MCLK and DSP. And It makes
/etrq_dy to be delayed as setting value in ETRG-delay register to /prf of system. So,
make /eadc signal.
3.4.7.7 Dotclk & pixelclk

Dot clock is clock to make SCG data. So, the period of dot clock and pixelclk is
determined according to Scan_depth. First it makes dotclk from MCLK to be divided by
determined value in DIVCLK register. Next it makes pixelclk from dotclk to be divided by
same method

DSP_D[7:0]
dot_clk
D[3:0]
LATCH LATCH GEN
MCLK 4BIT CNT
load_n Carry_n dot_clk
/TPRF
EOF_dy_n
=extrg_n
LATCH
MCLK pixel_clk
D[7:4]
GEN
dot_clk 4BIT CNT
load_n Carry_n pixel_clk
EOF_dy_n
LATCH
MCLK

3.5 Timing Chart

3.5.1 Input SSRAM rd/wr signal
DOT CLK
(SS clk)
SCG_SC
(ADSC,OE)
EADC
SCG DATA D0 D1 D2
WEN D00-0 D01-1 D02-0 D10-1 D11-0 D12-1 D20-1 D21-0 D22-1
WEN
(ISS ADSC,WE)
ISS ADDR A0 A1 A2 A3
DOT CLK
(SS clk)
SCG_SC
(ADSC,OE)
EADC
SCG DATA D0 D1 D2
WEN D00-0 D01-1 D02-0 D10-1 D11-0 D12-1 D20-1 D21-0 D22-1
WEN
(ISS ADSC,WE)
ISS ADDR A0 A1 A2 A3

3.5.2 Color Input Processing
/PRF
/CRP
/CD_RST
/CD_WR
/CD_END
/CFF1_WR
CFF_ENDLN
RTC CLEAR
/CDRD_FLAG
/BEADC
/CFF1_RD
CFF_ENDLN_OUT
/STT_CD
3.5.3 Input SSRAM RD/WR Timing
PRF
EADC
SSRAM write SSRAM write
(Even) (Odd)
HS
REAL
mode
SSRAM read SSRAM read
(Even) (Odd)

3.5.4 dotclk & pixelclk generation
7.000 8.000 9.000 10.000 11.000 12.000 13.000 14.000 us
div_dotclk 6
div_pixelclk 6
dot_clk
etrg_dly_n
pixel_clk
pixel_cnt_carry
pixel_cnt_load_n
3.5.5 /prf & /tprf generation
40.600 40.700 40.800 40.900 41.000 41.100 41.200 41.300 41.400 us
CLK61_6M
DOT_CLOCK
PIXEL_CLOCK
TPRF_N
PRF_N
EOF_DLY_N
3.5.6 Making sampling clk from SCG data
70.200 70.400 70.600 70.800 71.000 71.200 71.400 us
eadc_n
dot_clk
pixel_clk
scg_load
scg_sc
cscg_sd 0010101001010101 1010101001010111
sttBW_n
ser_out
cBWfifoWen_n
cBWfifoWCLK
pBWfifoWen_n
pBWfifoWCLK

3.5.7 TestPort RD/WR
150 200 250 300 350 400 450 500 ns
dclk
Addr 06 0F 06 0F
Data 000 0AA 000 0AA ZZZ
b_IOMS
b_WR
b_RD
3.5.8 SGRAM DSP RD/WR
750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 ns
XY_CK
XY_Cmd F 4 F 4 F 4 F 4 F
XY_Addr 000 0AA 055

Addr 10 11 12 13 12 13
b_IOMS
3.5.9 SSRAM DSP RD/WR
2400 2500 2600 2700 2800 2900 3000 ns
Addr 03 08 09
b_WR
b_RD
b_SS_E_ADSC
b_SS_E_B_OE
b_SS_E_B_WE
b_SS_O_ADSC
b_SS_O_B_OE
b_SS_O_B_WE
3.5.10 SSRAM Write Timing Start (Even Write)
2200 2400 2600 2800 3000 3200 ns
S_REAL
dot_clk
b_SCG_WEn
SS_E_Addr_B 15555 15556 15557 15558 15559 1555A 1555B
SS_E_CK
b_SS_E_ADSC
b_SS_E_B_WE
b_SS_E_B_OE

3.5.12 SSRAM Write Timing End (Even Write)
5100 5150 5200 5250 5300 5350 5400 5450 5500 ns
SS_E_CK
SS_E_Addr_B 00000 00001 00002
dot_clk
b_B_SS_WEN
b_BEADC
b_SS_E_ADSC
b_SS_E_B_OE
b_SS_E_B_WE
3.5.12 SSRAM Read Timing end (Odd Read)
5050 5100 5150 5200 5250 5300 ns
SS_O_CK
SS_O_Addr_B 00028
b_SS_O_ADSC
b_SS_O_B_OE
b_SS_O_B_WE
SS_RD_Start
FM_WR_Start
P_Data_LCk
FM_WCk
5410 5415 5420 5425 5430 5435 5440 5445 ns
SS_O_CK
SS_O_Addr_B 2002D 0002E 2002F
b_SS_O_ADSC
b_SS_O_B_OE
b_SS_O_B_WE
SS_RD_Start
FM_WR_Start
P_Data_LCk
FM_WCk

3.6 WAVE FORM

3.6.1 B Mode
1) BW Data Latch 2)input SSRAM WR
3) Azimuth data input 4) BW_INTP_Vector
5)F.A data input( Azimuth output ) 6) BW_NO_DATA

7) FI_MUX input 8)FI input
9) FI output 10) LINE MEMORY WR
3.6.2 Loop Mode

1) Loop Memory Read( FIFO input )

3.6.3 Color Mode

1) Pixel Interpolator input 2) input SSRAM WR
3) color Azimuth input 4) color FA input
5) Color_NO_DATA 6) Color FI_MUX input

7)FI input ( FIFO )
3.6.4 Color M Mode

1) Color M input( FIFO input ) 2) Color M FM Input( FIFO output )
3)Color M FM output( FIFO input ) 4) FIFO output

SonoAce9900 Section 2-4. DSP Board
4.DSP BOARD
DSP(Digital Signal Processor)B/D receives RF and CW I/Q data from Beamformer and CW
board. And, after it makes BW image, Spectral Doppler Spectrum and Color Doppler image, it
executes function to transmit it to DSC and V/M board.

<DTGC specifications>
Input bit width /rate 16 bits / fM fM : Master clock. Max 62 MHz
# of bins (or intervals) 64.
Interval size Programmable. N, N = 1 ~ Common to all 64 intervals.
1023.
M
Gain formula G = K / 2 , M = 12, K = 0 ~ 131071.
Gain increment ? ??
? ??
? ? ?
? ??
? ? SW is responsible for
One for each interval. calculating proper gain
increment and interval size to
meet the functional
requirements.
# of DTGC gain tables 7 One table is used for TGC
update. The others are used
as programmed (for instance,
use 6 tables for B0(=B2), B1,
M, C0(=C3), C1(=C2), D
(B/W uses tripple beam and
Color uses quad-beam
receiving ).
Contents of the DTGC gain Scale : 0 ~ 1023 Bin size will be shifted left by
table Initial value: 0 ~ 65535 2 in circuit, so effectively bin
64 bin size: unsigned 8 bits size means 10bits.
64 Gain increments: signed 11
bits
# of SGC gain tables 2
Contents of the SGC gain Two table Common: See Tbl.
table sgc_tbl0_line_type[4]
: unsigned 3bit * 4
center_sc : unsigned 9bit
sgc_bm_scale : unsigned
4bit

sgc_sc_scale : unsigned 8bit

Individual:
sgc_data[128]: unsigned
12bit
Output 16 bits, 62 MHz max.
4.2 BLOCK DIAGRAM
SA
memo
Synth Decim 1/N DC
BF etic DTG ation Decim Cancel

Apert C FIR ation FIR
Quadratur
e
Dynamic
FIR Filter
M/N Pixel
Log Envel Moving
Deci Decima
compress ope Average
mati tion
M/N
Zone BHF BW To
Decimatio
Blean NSF post DSC
n
ATGC To
To
color&

MCA016A PIN NUMBER

Bit
Pin Name Definition Note
count
I_IN Real data of RF to be transmitted from MGA015
Q_IN Imaginary data of RF to be transmitted from MGA015
/IQ_RDY Enable section of I.Q data in one /prf
IQ_CLK I,Q data enable signal
Read strobe when PDSP read clutter data from
/pdsp_cr
MGA016.
Read strobe when PDSP read Doppler data from
/pdsp_dr
MGA016.
Reset Clutter fifo in MGA016, before PDSP read
/c_rdy_rst
clutter data from MGA016.
Reset Doppler fifo in MGA016, before PDSP read
/d_rdy_rst
doppler data from MGA016.
Test_en Test output enable signal of MGA016
inp
Host_wr Time to write in MGA016 register or memory
Host_rd Time to read in MGA016 register or memory
Host_cs Time to access in MGA016 register or memory
EM_D Even memory data bus
EM_A Even memory address bus
OM_D Odd memory data bus
OM_A Odd memory address bus
EM_ctrl Even memory control signal bus
OM_ctrl Odd memory control signal bus
Mem_clk Memory clk
Out_c Clutter output bus of MGA016
Out_d Doppler output bus of MGA016
C_sem Clutter semaphore bus
D_sem Doppler semaphore bus
D_dsp_end Doppler data read end signal
C_dsp_end Clutter data read end signal
/c_rdy Clutter data ready signal to read clutter data
/d_rdy Doppler data ready signal to read doppler data

test
Clk Main clk
/of /OF
/prf /PRF
/crp /CRP
/reset Chip reset signal
4.4 Detail
4.4.1 MOTHER BUFFER
Buffering each kind of system control signal like that RF data to be transmitted from PC
data BUS, address BUS and Beamformer board, and CW I/Q data to be transmitted from
CW board.
4.4.2 PRE-MID FGGA

Pre-MID FPGA works to enlarge SNR and Contrast. At this time, it uses average data to
get several times at same scan-line with Multi-beam receiving. If this function can Multi-
beam overlap, real scan-line number to be transmitted to DSC is reduced.
1) dual beam --à single beam

Tx2 Tx4 Tx6
Rx0 Rx4
Rx8
Rx4
Rx8 Rx12
Rx0 Rx4' Rx8' Rx12'
2) triple beam -à dual beam

Tx2 Tx4 Tx6
Rx0 Rx4 Rx8
Rx8 Rx12 Rx16
Rx16 Rx20 Rx24
? ? ?
Rx0 Rx4 Rx8' Rx12 Rx16' Rx20' Rx24'
3) Quad beam --à single beam
TX2 TX4 TX6
RX0 RX8
RX4 RX12
RX12
RX20
RX8 RX16
RX16 RX24
RX20 RX26
? ? G?
RX0 RX8' RX16' RX24'

RX4 RX12' RX20' RX26'

4.4.3 MGA015A
MGA 015A makes I/Q data to process BW image spectral Doppler and Color Doppler with
RF data to be transmitted from Beamformer.
131: BW_OUT[10]
144: BW_OUT[0]
143: BW_OUT[1]
142: BW_OUT[2]
140: BW_OUT[3]
139: BW_OUT[4]
138: BW_OUT[5]
136: BW_OUT[6]
135: BW_OUT[7]
134: BW_OUT[8]
132: BW_OUT[9]
168: Q_OUT[15]
167: Q_OUT[14]
166: Q_OUT[13]
165: Q_OUT[12]
163: Q_OUT[11]
162: Q_OUT[10]
189: I_OUT[15]
188: I_OUT[14]
187: I_OUT[13]
186: I_OUT[12]
184: I_OUT[11]
183: I_OUT[10]
161: Q_OUT[9]
160: Q_OUT[8]
158: Q_OUT[7]
157: Q_OUT[6]
156: Q_OUT[5]
155: Q_OUT[4]
153: Q_OUT[3]
152: Q_OUT[2]
151: Q_OUT[1]
150: Q_OUT[0]
190: IQ_CK_O1
147: BW_CK_O
182: I_OUT[9]
181: I_OUT[8]
179: I_OUT[7]
178: I_OUT[6]
177: I_OUT[5]
176: I_OUT[4]
174: I_OUT[3]
173: I_OUT[2]
172: I_OUT[1]
171: I_OUT[0]
191: IQ_RDY1
146: BW_RDY
130: RP_OUT
185: VDD
175: VDD
164: VDD
154: VDD
145: VDD
137: VDD
129: VDD
192: VSS
180: VSS
170: VSS
169: VSS
159: VSS
149: VSS
148: VSS
141: VSS
133: VSS
VDD :193 128: VSS
IQ_RDY:194 127: BM_INDEX[0]
IQ_CK_O:195 126: BM_INDEX[1]
VSS:196 125: VDD
RAM_DATA0[15] :197 124: RF_IN[0]
RAM_DATA0[14] :198 123: RF_IN[1]
RAM_DATA0[13] :199 122: RF_IN[2]
VDD :200 121: RF_IN[3]
RAM_DATA0[12] :201 120: RF_IN[4]
RAM_DATA0[11] :202 119: RF_IN[5]
RAM_DATA0[10] :203 118: RF_IN[6]
VSS :204 117: RF_IN[7]
RAM_DATA0[9] :205 116: VSS
RAM_DATA0[8] :206 115: RF_IN[8]
RAM_DATA0[7] :207 114: RF_IN[9]
VDD :208 113: RF_IN[10]
RAM_DATA0[6] :209 112: RF_IN[11]
RAM_DATA0[5] :210 111: RF_IN[12]
RAM_DATA0[4] :211 110: RF_IN[13]
VSS :212 109: RF_IN[14]
RAM_DATA0[3] :213 108: VSS
RAM_DATA0[2] :214 107: RF_IN[15]
VDD 215 106: VSS
RAM_DATA0[1] :216 105: CK
RAM_DATA0[0] :217 104: VSS
VSS :218 103: PRF
RAM_ADDR0[15] :219 102: RP
RAM_ADDR0[14] :220 101: TESTEN
RAM_ADDR0[13] :221 100: CWK_SEL
MGA015A
RAM_ADDR0[12] :222 99: H_CS
VDD :223 98: H_RD
NC :224 97: H_WR
RAM_ADDR0[11] :225 96: VSS
RAM_ADDR0[10] :226 95: H_ADDR[0]
RAM_ADDR0[9] :227 94: H_ADDR[1]
RAM_ADDR0[8] :228 93: H_ADDR[2]
VSS :229 92: RESET
RAM_ADDR0[7] :230 91: VSS
RAM_ADDR0[6] :231 90: H_ADDR[0]
RAM_ADDR0[5] :232 89: H_DATA[1]
RAM_ADDR0[4] :233 88: H_DATA[2]
VDD :234 87: H_DATA[3]
RAM_ADDR0[3] :235 86: VDD
RAM_ADDR0[2] :236 85: H_DATA[4]
RAM_ADDR0[1] :237 84: H_DATA[5]
RAM_ADDR0[0] :238 83: H_DATA[6]
VSS :239 82: H_DATA[7]
RAM_WR0 :240 81: VSS
RAM_OE0 :241 80: H_DATA[8]
VDD :242 79: H_DATA[9]
RAM_DATA1[15] :243 78: H_DATA[10]
RAM_DATA1[14] :244 77: H_DATA[11]
RAM_DATA1[13] :245 76: VDD
VSS :246 75: H_DATA[12]
RAM_DATA1[12] :247 74: H_DATA[13]
RAM_DATA1[11] :248 73: H_DATA[14]
RAM_DATA1[10] :249 72: H_DATA[15]
VDD :250 71: VSS
RAM_DATA1[9] :251 70: ATGC[0]
RAM_DATA1[8] :252 69: ATGC[1]
RAM_DATA1[7] :253 68: ATGC[2]
VSS :254 67: ATGC[3]
RAM_DATA1[6] :255 66: ATGC[4]
VSS :256 65: VDD
1: VDD
2: RAM_DATA1[5]
3: RAM_DATA1[4]
4: RAM_DATA1[3]
5: VSS
6: RAM_DATA1[2]
7: RAM_DATA1[1]
8: RAM_DATA1[0]
9: VDD
10: RAM_ADDR1[15]
11: RAM_ADDR1[14]
12: RAM_ADDR1[13]
13: RAM_ADDR1[12]
14: VSS
15: RAM_ADDR1[11]
16: RAM_ADDR1[10]
17: RAM_ADDR1[9]
18: RAM_ADDR1[8]
19: VDD
20: RAM_ADDR1[7]
21: RAM_ADDR1[6]
22: RAM_ADDR1[5]
23: RAM_ADDR1[4]
24: VSS
25: RAM_ADDR1[3]
26: RAM_ADDR1[2]
27: RAM_ADDR1[1]
28: RAM_ADDR1[0]
29: VDD
30: RAM_WR1
31: RAM_OE1
32: VSS
33: VSS
34: SC_INFO[7]
35: SC_INFO[6]
36: SC_INFO[5]
37: SC_INFO[4]
38: SC_INFO[3]
39: SC_INFO[2]
40: SC_INFO[1]
41: SC_INFO[0]
42: SC_NO[7]
43: SC_NO[6]
44: SC_NO[5]
45: SC_NO[4]
46: SC_NO[3]
47: SC_NO[2]
48: SC_NO[1]
49: SC_NO[0]
50: VDD
51: ATGC_INFO[1]
52: ATGC_INFO[0]
53: ATGC_PRF
54: VSS
55: ATGC_CK_O
56: ATGC[11]
57: ATGC[10]
58: ATGC[9]
59: ATGC[8]
60: VDD
61: ATGC[7]
62: ATGC[6]
63: ATGC[5]
64: VSS


4.4.3.1 Synthetic Aperture Control
First TX/RX CYCLE Second TX/RX CYCLE
RAM SUM
RX B/F RX B/F
TX
• OUTPUT •
The signal to execute first TX/RX is stored in RAM like above diagram. After it sums second
TX/RX data with first data to be stored in RAM, transmit it to OUTPUT.
4.4.3.2 DTGC(DIGITAL TIME GAIN COMPENSAION)

Response of ultrasound becomes attenuation as deeper more and more. Using TGC to
compensation this state. MGA015A executes DTGC(Digital Time Gain Compensation),
but Front-end executes ATGC(Analog Time Gain Compensation). DTGC executes output
by multiplication RF(Radio Frequency) from Beamformer and DTGC GAIN.
B/F RF output
DTGC
4.4.3.3 DECIMATION FIR FILTER

MGA015A executes to 61.6MHz Clock. If noise component to contain in RF Signal
becomes decimation, it is transmitted after changing low frequency rate. In this case, SNR
is dropped, so use LPF(Low-pass Filter) to reduce the noise
4.4.3.4 1/N DECIMATION

The clock of MGA015 uses 61.6MHz. It is difficult next calculation because the time to

can next calculation is 61.6MHz. So, it uses 1/N. Decimation executes 1/N Decimation.
When N is 2, for example, it indicates following diagram. It is meaning to select either of
two data. The time to be transmitted data is 61.6MHz. Th e time to be transmitted is
divided by this method ; 61.6MHz/2=30.8MHz.
: Output data
: Throwing data
DATA
t
61.6Mhz
4.4.3.5 DC CANCEL FIR FILTER

There are DC component around frequency zero(0). To reject this DC component, it uses
HPF(high-pass filter). And it executes maximum cut-off.
4.4.3.6 QUADRATURE MIXER

The operation to change RF data to component of base band is “Quadrature
demodulator”. Mixer in Quadrature mixer is demodulator in other word. Main signal has to
be located at center of frequency. If main signal is not located at center of frequency, you
have to transfer that toward center of frequency. This is demodulator. It is method like
following diagram.
Expectation
Demodulato
Noise
The signal to execute Quadrature demodulator has to use Low-Pass Filter like following
f
30.8Mhz
diagram. Because of it needs to reject Noise component and unnecessary signal. After
passed this Dynamic filter, it is separated into route to make BW image data and I/Q data.
LOW
Pass
Service Manual Published byFilter
Customer Service Department
4.4.3.7 DYNAMIC FILTER

It is called Dynamic filter, because it is changed cut-off according to the depth.
3.5MHz f
4.4.3.8 ENVELOPE DETECTION
When the wave is transmitted like following left diagram, make it positive direction wave to
reject negative direction wave like following right diagram.
0 t 0 t
It changes the right wave like following graph by link each point.
0
t

4.4.3.9 LOG COMPRESSION
OUTPUT
INPUT
0
Dynamic range of BW data to become Envelope detection is very large. It is impossible to

display image directly. So it compresses the data. This course is compression. In this time,
it executes log compression. If the value is small, raises the Dynamic range, and value is
large, makes saturation.
As image depth is deeper, the noise becomes heavy and the contrast becomes small.
Raising the contrast of deep depth, and shallow depth makes changeless. So it makes
the whole contrast similarly.
4.4.3.10 M/N DECIMATION TO NEAREST

If the number of input data is N, output data is the number of M after receive the data as
many as M. For example, If N is 5 and M is 3, input data is 5 and output data is 3.
4.4.3.11 PIXEL DECIMATION

Real pixel number to execute out from M/N Decimation to Nearest is transmitted over
minimum 2000. But pixel number to receive at DSC is 1000~2000 degree. Before transmit
to DSC, calculate real entered number as number of the pixel to need at DSC. And
transmit it to DSC

4.4.3.12 ZONE BLEND
ZONE ? ? ? ?
When there are several TX focusing, it has to focus several times. In this time, curve
occurs like above left diagram. The section between curve them is called Zone section. It
mixes overlap section of Zone naturally. This is Zone Blending. Following diagram shows
gain to be given in each zone during mixing.
a 0(n)
1
0 n
a 1(n) (depth)
1
0 n
a 2(n) (depth)
1
0 n
a 3(n) (depth)
1
0 n
n n n (depth)
1 2 3

4.4.3.13 BHF(BLOCK-HOLD-FILLTERING),
NSF(NOISE-SPILCE FILLTERING)
Above diagram is BHF method.

BHF(Block-hold-filtering) can take off the hole to be any place in image. It uses the
method that compensate similarly with around gain after average around data.
NSF(Noise-Spilce Filltering) is opposite method with BHF. If the gain in any place is ve ry
larger than around, we can think that it is noise. In this case, it rejects Pixel.
・・・
・・
・・・
4.4.3.14 BW POST FILLTER

BW data to be finished all processing pass LPF(Low-pass filter) to reject noise or
unnecessary signal before transmitting to DSC.
4.4.3.15 MOVING AVERAGE

If you link each point of DATA such as following diagram, it would make irregular curve.
To flatten this curve, it collects the data N by N, and transmits data after execute sum and
average. Following diagram is example when N equal 3.

DATA
DATA
t
t
4.4.4 MGA016 PIN DIARAM & BLOCK DIAGRAM

Following block diagram shows the function and stream of signal in MGA016A. MGA016A
can divide 3 blocks. It is divided signal processing part to process pre-processing of Color
Doppler processing, cornering part to help Color Doppler processing after standing in line
I/Q data, and host interface part to connect Host and internal memory/register.
157 : /DRDY_RST
155 : /CRDY_RST
208 : OUT_D[15]
207 : OUT_D[14]
206 : OUT_D[13]
205 : OUT_D[12]
204 : OUT_D[11]
203 : OUT_D[10]
190 : OUT_C[15]
189 : OUT_C[14]
188 : OUT_C[13]
187 : OUT_C[12]
186 : OUT_C[11]
185 : OUT_C[10]
172 : /DSP3_DR
171 : /DSP3_CR
170 : /DSP2_DR
169 : /DSP2_CR
168 : /DSP1_DR
167 : /DSP1_CR
166 : /DSP0_DR
165 : /DSP0_CR
202 : OUT_D[9]
201 : OUT_D[8]
199 : OUT_D[7]
198 : OUT_D[6]
197 : OUT_D[5]
196 : OUT_D[4]
195 : OUT_D[3]
194 : OUT_D[2]
193 : OUT_D[1]
192 : OUT_D[0]
184 : OUT_C[9]
183 : OUT_C[8]
181 : OUT_C[7]
180 : OUT_C[6]
179 : OUT_C[5]
178 : OUT_C[4]
177 : OUT_C[3]
176 : OUT_C[2]
175 : OUT_C[1]
174 : OUT_C[0]
163 : D_SEM[1]
162 : D_SEM[0]
160 : C_SEM[1]
159 : C_SEM[0]
226 : TEST[15]
225 : TEST[14]
224 : TEST[13]
223 : TEST[12]
222 : TEST[11]
221 : TEST[10]
220 : TEST[9]
219 : TEST[8]
217 : TEST[7]
216 : TEST[6]
215 : TEST[5]
214 : TEST[4]
213 : TEST[3]
212 : TEST[2]
211 : TEST[1]
210 : TEST[0]
227 : TESTEN
158 : /RESET
156 : DRDY
154 : CRDY
218 : VDD
200 : VDD
182 : VDD
164 : VDD
161 : VDD
228 : VSS
209 : VSS
191 : VSS
173 : VSS
153 : VSS
229 : VSS 152 : VSS
230 : VSS 151 : HOST_D[15]
231 : /OM_CTRL[0] 150 : HOST_D[14]
232 : /OM_CTRL[1] 149 : HOST_D[13]
233 : /OM_CTRL[2] 148 : HOST_D[12]
234 : /OM_CTRL[3] 147 : VDD]
235 : VDD 146 : HOST_D[11]
236 : /OM_CTRL[4] 145 : HOST_D[10]
237 : /OM_CTRL[5] 144 : HOST_D[9]
238 : /OM_CTRL[6] 143 : HOST_D[8]
239 : /OM_CTRL[7] 142 : VDD
240 : VSS 141 : HOST_D[7]
241 : OM_A[0] 140 : HOST_D[6]
242 : OM_A[1] 139 : HOST_D[5]
243 : OM_A[2] 138 : HOST_D[4]
244 : OM_A[3] 137 : HOST_D[3]
245 : VDD 136 : HOST_D[2]
246 : OM_A[4] 135 : HOST_D[1]
247 : OM_A[5] 134 : HOST_D[0]
248 : OM_A[6] 133 : VSS
249 : OM_A[7] 132 : HOST_A[2]
250 : VSS 131 : HOST_A[1]
251 : OM_A[8] 130 : HOST_A[0]
252 : OM_A[9] 129 : /HOST_WR
253 : OM_A[10] 128 : /HOST_RD
254 : OM_A[11] 127 : /HOST_CS
255 : VDD 126 : VDD
256 : OM_A[12] 125 : IQ_RDY
257 : OM_A[13] 124 : /IQ_CLK
258 : OM_A[14] 123 : D_DSP_END
259 : OM_A[15] 122 : C_DSP_END
260 : VSS 121 : VSS
261 : OM_A[16] 120 : VSS
262 : OM_A[17] 119 : VSS
263 : OM_A[18] 118 : /PRF
264 : OM_A[19] 117 : /CRP
265 : OM_A[20] 116 : /OF
MGA016A
266 : VDD 115 : CLK
267 : OM_D[0] 114 : VSS
268 : OM_D[1] 113 : I_IN[15]
269 : OM_D[2] 112 : I_IN[14]
270 : OM_D[3] 111 : I_IN[13]
271 : OM_D[4] 110 : I_IN[12]
272 : OM_D[5] 109 : I_IN[11]
273 : OM_D[6] 108 : I_IN[10]
274 : OM_D[7] 107 : I_IN[9]
275 : VSS 106 : I_IN[8]
276 : OM_D[8] 105 : VDD
277 : OM_D[9] 104 : I_IN[7]
278 : OM_D[10] 103 : I_IN[6]
279 : OM_D[11] 102 : I_IN[5]
280 : OM_D[12] 101 : I_IN[4]
281 : OM_D[13] 100 : I_IN[3]
282 : OM_D[14] 99 : I_IN[2]
283 : OM_D[15] 98 : I_IN[1]
284 : VDD 97 : I_IN[0]
285 : OM_D[16] 96 : VSS
286 : OM_D[17] 95 : Q_IN[15]
287 : OM_D[18] 94 : Q_IN[14]
288 : OM_D[19] 93 : Q_IN[13]
289 : OM_D[20] 92 : Q_IN[12]
290 : OM_D[21] 91 : Q_IN[11]
291 : OM_D[22] 90 : Q_IN[10]
292 : OM_D[23] 89 : Q_IN[9]
293 : VSS 88 : Q_IN[8]
294 : OM_D[24] 87 : VDD
295 : OM_D[25] 86 : Q_IN[7]
296 : OM_D[26] 85 : Q_IN[6]
297 : OM_D[27] 84 : Q_IN[5]
298 : OM_D[28] 83 : Q_IN[4]
299 : OM_D[29] 82 : Q_IN[3]
300 : OM_D[30] 81 : Q_IN[2]
301 : OM_D[31] 80 : Q_IN[1]
302 : VSS 79 : Q_IN[0]
303 : MEM_CLK 78 : INP2
304 : VSS 77 : VSS
1 : VSS
2 : /EM_CTRL[0]
3 : /EM_CTRL[1]
4 : /EM_CTRL[2]
5 : /EM_CTRL[3]
6 : VDD
7 : /EM_CTRL[4]
8 : /EM_CTRL[5]
9 : /EM_CTRL[6]
10 : /EM_CTRL[7]
11 : VSS
12 : EM_A[0]
13 : EM_A[1]
14 : EM_A[2]
15 : EM_A[3]
16 : VDD
17 : EM_A[4]
18 : EM_A[5]
19 : EM_A[6]
20 : EM_A[7]
21 : VSS
22 : EM_A[8]
23 : EM_A[9]
24 : EM_A[10]
25 : EM_A[11]
26 : VDD
27 : EM_A[12]
28 : EM_A[13]
29 : EM_A[14]
30 : EM_A[15]
31 : VSS
32 : EM_A[16]
33 : EM_A[17]
34 : EM_A[18]
35 : EM_A[19]
36 : EM_A[20]
37 : VDD
38 : EM_D[0]
39 : EM_D[1]
40 : EM_D[2]
41 : EM_D[3]
42 : EM_D[4]
43 : EM_D[5]
44 : EM_D[6]
45 : EM_A[7]
46 : VSS
47 : EM_D[8]
48 : EM_D[9]
49 : EM_D[10]
50 : EM_D[11]
51 : EM_D[12]
52 : EM_D[13]
53 : EM_D[14]
54 : EM_D[15]
55 : VDD
56 : EM_D[16]
57 : EM_D[17]
58 : EM_D[18]
59 : EM_D[19]
60 : EM_D[20]
61 : EM_D[21]
62 : EM_D[22]
63 : EM_D[23]
64 : VSS
65 : EM_D[24]
66 : EM_D[25]
67 : EM_D[26]
68 : EM_D[27]
69 : EM_D[28]
70 : EM_D[29]
71 : EM_D[30]
72 : EM_D[31]
73 : VDD
74 : INP0
75 : INP1
76 : VSS

Axial Power
Threshold
for Doppler
Input from Clutter Matrix Boxcar Output

Input Autocorrelation Mapper Output to
Cornering Buffer
Modulation Filter for Doppler Filter
for Doppler
Buffer
for Doppler for Doppler for Doppler for Doppler Post DSP
Memory
Output Output to
Autocorrelation Mapper Buffer
for Clutter for Clutter Post DSP
for Clutter
Axial Power
Axial Power
Threshold
Threshold
for
for Clutter
Modulation
Output to Control signals

Input from Cornering
Buffer Cornering
MCB015A
Memory
System Internal
ASIC Host Input
Control Controller
Memory &
Interface
Cornering Register from Host
Control Signals
4.4.4.1 Signal processing part

This part receives input I/Q data to be became cornering(Input Buffer). And it detects
information of blood by auto-correlation after executing Clutter modulation(Clutter
Modulation for Doppler) and filtering Clutter signal(Matrix Filter for Doppler). This
information is transmitted to post-processing part through mapping process(Mapper for
Doppler).
4.4.4.2 Cornering part

Cornering part changes the direction of input I/Q/ data. Also it executes buffering until
collecting all ensemble data. It is divided state machine to control cornering memory
during counting scanline, ensemble, interleave and pixel, and control part to control
directly buffering memory to execute these works.
4.4.4.3 Host interface part

Host interface is consisted internal address/internal data port to access internal
memory/register, external high address/external low address/external data port to access
cornering memory, test control register to control output what data of internal function
block to test output port, and chip ID register to be having chip ID, command register to
control function of host interface.

4.4.5 DOPPLER PART

Doppler part is divided Clutter filtering, Hilbert transform, FFT(Fast Fourier Transform).
Each Clutter filtering, Hilbert transform, FFT(Fast Fourier Transform) is constituted ADSP
2183.
I data IFIFO Clutter FFT DSC

DSP DSP
Q data IFIFO
Hilbert
V/M
transform
DSP
4.4.5.1 Clutter filtering

I/Q data(each 16bit) to be transmitted from MGA015 enter every PRF through /IFIFOWR
and /QFIFOWR of FIFO(72bv01). If the signals work out such as following diagram, the
difference of phase is angle of 90 degree.
4.4.5.2 FFT (Fast Fourier Transform)

FFT(Fast Fourier Transform) indicates the magnitude of each frequency component to
constitute signal wave.
4.4.5.3 Hilbert transform

Input I/Q data from FIFO has difference of phase angle of 90 degree. In this time,
summing phase angle of 90 degree. That reason is to separate direction of Doppler sound.
Output value from this process is transmitted to VIDEO MANAGER.

4.5 Timing Chart

4.5.1 HOST WRITE
CLK
/HOST_CS
/HOST_WR
/HOST_RD
HOST_A[0..11]
HOST_D[0..15]
4.5.2 HOST READ
CLK
/HOST_CS
/HOST_WR
/HOST_RD
HOST_A[0..11]
HOST_D[0..15]
4.5.3 MGA 015
CLK(61.6MHz)
IQ_RDY
IQ_CLK
IIN[0..15]
QIN[0..15]

4.5.4 Write with auto-precharge sequence(1 pixel, Random write, Sync-DRAM)
NOP ACT NOP WRA NOP NOP ACT NOP
CLK
/CS
/RAS
/CAS
/WE
ADDR ROW COL
DATA Data
4.5.5 Write sequence(8 pixel, Random write & write with auto-precharge, Sync-DRAM)
NOP ACT NOP WR WR WR WR WR WR WR WRA NOP NOP ACT NOP
CLK
/CS
/RAS
/CAS
/WE
ADDR ROW n n+32 n+64 n+96 n+128 n+160 n+192 n+224
DATA n n+32 n+64 n+96 n+128 n+160 n+192 n+224
4.5.6 Read sequence(12 Ensemble, Random read & read with auto-precharge, Sync-
DRAM)
NOP ACT NOP RD NOP NOP NOP RD NOP NOP NOP RDA NOP NOP NOP NOP NOP NOP ACT NOP
CLK
/CS
/RAS
/CAS
/WE
ADDR ROW n n+4 n+8
DATA n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11

4.5.7 Auto-refresh sequence(Sync-DRAM)
NOP PCH NOP ARF NOP NOP NOP ACT
CLK
/CS
/RAS
/CAS
/WE
ADDR ALL
DATA
4.5.8 Init sequence(Sync-DRAM)
PUP NOP PCH NOP ARF NOP NOP NOP ARF NOP NOP NOP LMR NOP ACT
CLK
/CS
/RAS
/CAS
/WE
ADDR ALL Mode ROW
DATA Hi-Z Hi-Z

4.6 Wave Form

4.6.1 PRE-MID clk and /RF_DVS setup time PRE-MID clk and /RF_DVS hold time
4.6.2 PRE-MID clk and PRE-MID data /RF_DVS input and /RF_DVS
4.6.3 /RF_DVS output and PRE_MID MID RAM_WE and data
4.6.4 MID HOST_CS, HOST_WR, PC address MID HOST_CS, HOST_WR, PC data

4.6.5 MID HOST_CS, HOST_RD, PC data MID HOST_CS, HOST_RD, PC

address
4.6.6 /BW_RDY ? /BW_CLK /BW_RDY , /BW_CLK , /BW
4.6.7 IFIFO_WCK and IFIFO_WEN IFIFO_WCK, IFIFO_WEN, IFIFO I N

4.6.8 IFIFO_RCK and IFIFO_REN IFIFO_RCK, IFIFO_REN, IFIFO_OUT
4.6.9 BW_RDY, BW_CLK, BW_DATA BW_RDY, BW_CLK, BW_DATA

4.6.10 IQ_RDY and CPLD IQ_RDY IQ_RDY, IQ_CLK, CPLD IQ_RDY
4.6.11 IQ_RDY and IQ_CLK IQ_RDY, IQ_CLK, I DATA
4.6.12 CDP HOST_CS, HOST_WR, ADDRESS CDP HOST_CS, HOST_WR, ADDRESS

Hold time timing setup time timing
4.6.13 CDP HOST_CS, HOST_WR, ADDRESS CDP HOST_CS, HOST_WR, ADDRESS
4.6.14 EM_CS,EM_RAS,EM_CAS,EM_DATA EM_CS,EM_RAS,EM_CAS,EM_ADDRESS
4.6.15 PDSP0_DR0 and OUT0


4.6.16 Clutter ADSP input FIFO Clutter ADSP input FIFo
4.6.17 Clutter ADSP input FIFO Clutter ADSP input FIFO
4.6.18 /cltint, sd_sclk, sd_tfs, sd_sdata Interrupt /CLTINT of Clutter DSP and
Audio DSP interrupt
/AUDINT&SPORT0
4.6.19 Audio DSP interrput/AUDINT& Audio DSP interrput/AUDINT&

SPORT0 output SPORT0 output
4.6.20 Output of FFT DSP in B/D simultaneous mode Output of FFT DSP
.
4.6.21 CW Doppler CW Doppler
4.6.22 MSE output MSE output

(Case that Gap is 3 line) (Case that Gap is 3 line)
4.6.23 Mother clk and CPLD clk Mother clk and MGA016 clk
4.6.24 Mother clk and MGA015 clk CPLD input clk and output clk
4.6.25 CPLD0 output clk and PLL output clk PLL output clk and PDSP0 clk

4.6.26 PDSP0 clk and PDSP0clk0 PDSP0 clk and CADCLK

SonoAce9900 Section 2-5. Video Manager Board
5.VIDEO MANAGER
Executing KEYING image to receive from DSC and VGA data. And it makes final output after
making INTERLACE/NON-INTERLACE signal. It has the function that executing A/D after
receiving VCR input data, and display it after DECORDING. Also it has the function to save DSC
INPUT DATA in IMAGE GRABBER after changing to RGB 24 BIT by POST CONTROL FPGA
and POST MAP.
It has the function that does DT saved DATA in IMAGE GRABBER, and writes it in FIELD
MEMORY, display to MONITOR after MUX with VGA data. (It displays to MONITOR after
KEYING VGA 800*600 signal and IMAGE GRABBER 640*480 signal). It includes the part about
DOPPLER SOUND except IMAGE PATH.
That part works D/A after receiving input DOPPLER SERIAL DATA, and output SOUND to
SPEAKER after processing data in LOW PASS FILTER and AMPLIFIER.

- VGA clock : Using 40Mhz and standard 800 x 600.
- IMAGE clock : Using 25Mhz And standard 640 x 480.
- Image Grabber Memory : Using 256K x 32bit x 2bank. (KM4132G512) Clock is 50Mhz.
- VCR In : Receiving input video signal by SAA7110 and using after transformation to
RGB565 format by De-interlace chip(AL251).
- VCR out : Using VGA to Ntsc / Pal converter chip (AL251)
- Supporting two type 800 x 600, 640 x 480
- Supporting Digital RGB and YC , Composite at the same time
- VGA and VCR expression type : VGA expression is NON-INTERLACE type. It is normal
PC-MONITOR type. But VCR input/output is INTERLACE type.
- Vsync is 60Hz, and there are Hsync of the number of 522 in one Sync. There are Hsync
of the number of 10 in Vsync BLANK zone. Hsync is fixed about 32us, and there are clock
of the number of 790 in one Hsync, and ACTIVE zone is fixed the number of 644.

5.2 BLOCK DIAGRAM



ADDR Port Name Kind Description

A00H~BFFH PBUS_EN
A00H /X_POST_WR W Reserved
A04H /XZM_WR W Reserved
A0CH /PSNDLT W Sound volume Data load
A10H /PSNDWR W AD7524 WR
A14H /PCLTLPFCS W S3528B set up data load
A18H /PVMIWR W ADSP /IWR
/PVMIRD R ADSP /IRD
A18H~A1CH /VMCS
A1CH PVMAL W ADSP IAL
A20H /PDSPECHORD R ADSP -> CPU Data read Enable
A28H /PVMSTSRD R VM Status read
A2CH /PVMSTSWR W VM Status write
A30H PDLCLK R/W DLQ Clock
/PZMLUTWE
/PPOSTWR
/PZMLUTDEN
/PPOSRDEN
A34H PDLRST W DLQ Reset
A40H~A4CH PSYNCCS 74ACT715 CS
A50H /XZM_RST W ZOOM Control Reset
A54H /XPOST_RST W POST Control Reset
A58H /OVIDLEY_CLR W Video Key Reset clear

VIDEO MANAGER DSP COMMAND LIST

? ? CMD Para0 Para1 Para2 Para3 Comment
SG RAM Control
reserved 0x00 Clock enable DQM
SG_WriteOne 0x01 Row addr Col addr Data
SG_ReadOne 0x02 Row addr Col addr Data
PDSP_FIFORST 0x03
SG_FillMem 0x04 Data
reserved 0x05
SG_ReadOneRow 0x06 Column start row start column end row end addr
addr addr addr
SG_WRSTT 0x07 Start point
SG_WREnable 0x08 WR Start 1 WR Start 2 WR End 1 WR End 2
VM_CTR 0x09 b0: s_vcine_igr
b1 : s_r_rd_en
b2 : s_r_wr_en
b3 : s_real
b4:xend_le_512
b5:xstt_ge_512
SG_Refresh 0x0a
SG_DQM 0x0b b[2..0]DQM
B(2),G(1),R(0)
Zoom scale 0x0c 4 : x 2
2 : x 4
1 : x 8
0 : normal

Post Control CMD Para0 Para1 Para2 Para3 Comme

nt
System 0x40 b0:image display
Display Mode on(1)/off(0)
b1 : ECG on/off
b2 : PCG on/off
b3: doppler mean
on/off
b4 : doppler max
on/off
Select 0x41 0-normal display
Image Mode 1- B/W only
2- reserved
3 - color only
Select 0x42 0 - image clock
Clock Mode 1 - VCR clock
Post 0x43 0-postram Not
Ram Mode download mode used
1-real mode
PostMode Kind 0x44 b[3..0]
0 - B mode
1 - M mode
2 - D mode
3 - reserved
4 - C mode
5 - CM mode
6,7 - reserved
8 - ECG mode
9 - PCG mode
a - Doppler mean
b - Doppler max
Window Kind 0x45 b[4..0]
1H- FM (B,C)
3H- display (vga)
10H- sweep
12H- M
13H- D
14H- Acquisition

15H- ECG
others - reserved
H Window Set 0x46 Horizontal Horizontal
window start window end
V Window Set 0x47 Vertical Vertical window
window start end
Window Attribute 0x48 b0:single(1)
composite(0)
b1: Horizontal(1)
b2 : Vertical(1)
Window Latch 0x49
Color Mask Set 0x4a Color mask
ECG Size Set 0x4b
Post Test 0x4c b0 : 0-real
Pattern 1-test pattern
b1:0-Hori,1-Verti
for B/Wdata path
b2:0-Hori,1-Verti
for C data path
Acquisition 0x4d Horizontal start Horizontal end Vertical start Vertical
window end
SetVideoTrigger 0x4e video_trigger video_trigger_ video_trigger_ video_t
locx locy rigger_
width
Post control CMD Para0 Para1 Para2 Para3 Comment

I2Bus Write 0x50 0 : SA7110 Control Register
1 : AL251 Register Value
2 : AL128A Index
3 : AL128B
Select 0x51 0 : NTSC
PAL/NTSC 1 : PAL
Select 0x52 0 : System
Input Source 1 : VHS
(video source
1)
2: S-VHS

(video source
2)
Set 0x53
SAA7110 Reg
Set 0x54
AL128a Reg
Vm 0x55 b0 : real(0)
Freeze Real freeze(1)
b1: DT
disable(0)
enable(1)
Video 0x56 b[1..0] Not used
Key Control 0,2 – real
(VGA+imag
e)
mode
1 - only VGA
3 - only
image
Video Out 0x57 0 -- 800x600
800x600/640x480 1 -- 640x480
Select
Debug command
Image size 0xf0
640x480
VCR test Ntsc 0xf1
VCR test pal 0xf2
SG_Write 0xf3 Row addr data
One row
SG_Write 0xf4 Col addr data
One column
VS start 0xf6 Start point

5.4 Detail Fact

SA9900 can display 800 x 600 full size at monitor.
But ultrasound image expression zone is just 640 x 480 size. Also this part can display
external input such as VCR input.
VGA expression is Non-Interlace type, and it is normal PC monitor.
Input/Output of VCR is Interlace type, so it is necessary circuit composition to express
Interlace type.
And the section can divide ultrasound zone and VCR zone with black part and boundary

5.4.2 VCR INPUT

ANALOG VIDEO signal(VHS, S-VHS) to be transmitted from VCR is TV signal and
INTERLACE type signal. And TV image signal is divided NTSC, PAL, and SECAM type by
character of each region. So, it uses exclusive using chip like ONE CHIP FRONT
END1(SAA7110) to process each different input data, and executes A/D CONVERSION in
the inside. And it makes UV/Y FORMAT from INPUT ANALOG VIDEO signal by internal
CHROMINANCE CIRCUIT and LUMINANCE CIRCUIT. And it transmits to be changed
data.
7
1
CV-IN 3
+ 6
2 8
-
UV
4
5
7
1
Y-IN 3 VIDEO INPUT PROCESSOR

+ 6
2 SAA7110
-
8
Y
4
5
7
1
C-IN 3
+ 6
2
-
4
5

It is the part that express NON-INTERLACE type signal after changing the signal to be
transmitted from ONE CHIP FORNT END. Also, it transmits the result value after changing
R.G.B 565 and VCR SYNC (640 x 480). The R.G.B signal of 24BIT is transmitted from this
part. Also, this chip can support the interface by 12C PROTOCOL.
Square Pixel CCIR 601

NTSC PAL NTSC PAL
Pixel Total 780 x 525 944 x 625 858 x 525 864 x 635
Pixel Active 640 x 480 768 x 576 720 x 480 720 x 576
VCLKx2(MHZ) 24.545454 29.5 27 27
VCLK (MHZ) 12.272727 14.75 13.5 13.5

In IMAGE PART, B-MODE IMAGE, COLOR DATA, and ECG DATA to be transmitted from
DSC BOARD transmit to POST CONTROL. In this part, it transmits input signal according
MODE(B,C,ECG) to POST MAP after separating signal.

5.4.5 IMAGE GRABBER

REAL IMAGE signal and VCR signal is saved in IMAGE GRABBER, and IMAGE
GRABBER DATA works to make VIDEO SIGNAL after transmitting to OUTPUT FIFO. Also,
it works to transmitting IMAGE of IMAGE GRABBER to MAIN PC, or receiving that.
5.4.6 FIELD MEMORY

It has to transform the signal after matching synchronism with SYNC to display at VGA
MONITOR. FIELD MEMORY works this function. And FIELD MEMORY uses AL422, and
supports suitable RESOLUTION to use VGA and TV signal. AL422 is 3M-BITS FIFO FIELD
MEMORY, and it is possible to operate each READ/WRITE.
5.4.7 VIDEO KEY

IMAGE/VCR signal of 640 x 480 size to be transmitted from FIELD MEMORY is displayed
at MONITOR in 800 x 600 size with OVERLAY(VGA signal) or other MENU signal. In this
time, it is the part to do MUX with VGA signal.

DIGITAL RGB signal to be executed KEYING is transmitted to VGA MONITOR after
changing into ANLOG RGB through VIDEO DAC(TDA8772).
5.4.9 INTERLACE OUTPUT

It is necessary output signal to display at ECHO PRINTER or INTERLACE MONITOR
separately VGA signal, and it uses exclusive chip AL128. Also it is necessary FIELD
MEMORY to display 640 X 480 size or 800 x 600 size full image. In this FIELD MEMORY,
the signal to be executed MUX is transmitted to AL128 after output 640 x 480 signal.

5.4.10 SOUND I/O

This part works to come out sounds such as final output DOPPLER signal and SOUND to
be transmitted from VCR at SPEAKER. And first input DOPPLER signal is changed to
SERIAL signal by AD766
INVERT_AMP
6 SOUND_MUX_L
6 6 DA LPF
CONVERT
CPU_DATA HEX
BUFFER
BUFFER
INVERT_AMP
8 8 6
CPU_DATA OCTAL DA LPF SOUND_MUX_R
BUFFER CONVERT

5.5 Timing Chart

5.5.1 VGA SYNC TIMING
16.6ms
VGA_VS
VGA_HS
VGADOTCLK
26.3us
25ns
5.5.2 IMAGE SYNC TIMING
16.6ms
IMG_VS
IMG_HS
IMGDOTCLK
31.56us
40ns
5.5.3 IMAGE GRABBER
/HS
IFIFOWEN
IFIFOREN
OFIFOWEN
OFIFOREN

5.6 Wave Form

5.6.1 CH1 TP:/VGAVS CH2 TP :/VGAHS CH1 TP:/VGAHS CH2 TP :/VGABLK
CH3 TP :/VGADOTCLK
5.6.2 CH1 TP:/VGAHS CH2 TP :/VGABLK
5.6.3 IMAGE REALTION


5.6.3 SONOVIEW SIGNAL

5.6.4 KEYING SIGNAL


5.VIDEO MANAGER
Executing KEYING image to receive from DSC and VGA data. And it makes final output after
making INTERLACE/NON-INTERLACE signal. It has the function that executing A/D after
receiving VCR input data, and display it after DECORDING. Also it has the function to save DSC
INPUT DATA in IMAGE GRABBER after changing to RGB 24 BIT by POST CONTROL FPGA
and POST MAP.
It has the function that does DT saved DATA in IMAGE GRABBER, and writes it in FIELD
MEMORY, display to MONITOR after MUX with VGA data. (It displays to MONITOR after
KEYING VGA 800*600 signal and IMAGE GRABBER 640*480 signal). It includes the part about
DOPPLER SOUND except IMAGE PATH.
That part works D/A after receiving input DOPPLER SERIAL DATA, and output SOUND to
SPEAKER after processing data in LOW PASS FILTER and AMPLIFIER.

- VGA clock : Using 40Mhz and standard 800 x 600.
- IMAGE clock : Using 25Mhz And standard 640 x 480.
- Image Grabber Memory : Using 256K x 32bit x 2bank. (KM4132G512) Clock is 50Mhz.
- VCR In : Receiving input video signal by SAA7110 and using after transformation to
RGB565 format by De-interlace chip(AL251).
- VCR out : Using VGA to Ntsc / Pal converter chip (AL251)
- Supporting two type 800 x 600, 640 x 480
- Supporting Digital RGB and YC , Composite at the same time
- VGA and VCR expression type : VGA expression is NON-INTERLACE type. It is normal
PC-MONITOR type. But VCR input/output is INTERLACE type.
- Vsync is 60Hz, and there are Hsync of the number of 522 in one Sync. There are Hsync
of the number of 10 in Vsync BLANK zone. Hsync is fixed about 32us, and there are clock
of the number of 790 in one Hsync, and ACTIVE zone is fixed the number of 644.

5.2 BLOCK DIAGRAM



ADDR Port Name Kind Description

A00H~BFFH PBUS_EN
A00H /X_POST_WR W Reserved
A04H /XZM_WR W Reserved
A0CH /PSNDLT W Sound volume Data load
A10H /PSNDWR W AD7524 WR
A14H /PCLTLPFCS W S3528B set up data load
A18H /PVMIWR W ADSP /IWR
/PVMIRD R ADSP /IRD
A18H~A1CH /VMCS
A1CH PVMAL W ADSP IAL
A20H /PDSPECHORD R ADSP -> CPU Data read Enable
A28H /PVMSTSRD R VM Status read
A2CH /PVMSTSWR W VM Status write
A30H PDLCLK R/W DLQ Clock
/PZMLUTWE
/PPOSTWR
/PZMLUTDEN
/PPOSRDEN
A34H PDLRST W DLQ Reset
A40H~A4CH PSYNCCS 74ACT715 CS
A50H /XZM_RST W ZOOM Control Reset
A54H /XPOST_RST W POST Control Reset
A58H /OVIDLEY_CLR W Video Key Reset clear

VIDEO MANAGER DSP COMMAND LIST

? ? CMD Para0 Para1 Para2 Para3 Comment
SG RAM Control
reserved 0x00 Clock enable DQM
SG_WriteOne 0x01 Row addr Col addr Data
SG_ReadOne 0x02 Row addr Col addr Data
PDSP_FIFORST 0x03
SG_FillMem 0x04 Data
reserved 0x05
SG_ReadOneRow 0x06 Column start row start column end row end addr
addr addr addr
SG_WRSTT 0x07 Start point
SG_WREnable 0x08 WR Start 1 WR Start 2 WR End 1 WR End 2
VM_CTR 0x09 b0: s_vcine_igr
b1 : s_r_rd_en
b2 : s_r_wr_en
b3 : s_real
b4:xend_le_512
b5:xstt_ge_512
SG_Refresh 0x0a
SG_DQM 0x0b b[2..0]DQM
B(2),G(1),R(0)
Zoom scale 0x0c 4 : x 2
2 : x 4
1 : x 8
0 : normal

Post Control CMD Para0 Para1 Para2 Para3 Comme

nt
System 0x40 b0:image display
Display Mode on(1)/off(0)
b1 : ECG on/off
b2 : PCG on/off
b3: doppler mean
on/off
b4 : doppler max
on/off
Select 0x41 0-normal display
Image Mode 1- B/W only
2- reserved
3 - color only
Select 0x42 0 - image clock
Clock Mode 1 - VCR clock
Post 0x43 0-postram Not
Ram Mode download mode used
1-real mode
PostMode Kind 0x44 b[3..0]
0 - B mode
1 - M mode
2 - D mode
3 - reserved
4 - C mode
5 - CM mode
6,7 - reserved
8 - ECG mode
9 - PCG mode
a - Doppler mean
b - Doppler max
Window Kind 0x45 b[4..0]
1H- FM (B,C)
3H- display (vga)
10H- sweep
12H- M
13H- D
14H- Acquisition

15H- ECG
others - reserved
H Window Set 0x46 Horizontal Horizontal
window start window end
V Window Set 0x47 Vertical Vertical window
window start end
Window Attribute 0x48 b0:single(1)
composite(0)
b1: Horizontal(1)
b2 : Vertical(1)
Window Latch 0x49
Color Mask Set 0x4a Color mask
ECG Size Set 0x4b
Post Test 0x4c b0 : 0-real
Pattern 1-test pattern
b1:0-Hori,1-Verti
for B/Wdata path
b2:0-Hori,1-Verti
for C data path
Acquisition 0x4d Horizontal start Horizontal end Vertical start Vertical
window end
SetVideoTrigger 0x4e video_trigger video_trigger_ video_trigger_ video_t
locx locy rigger_
width
Post control CMD Para0 Para1 Para2 Para3 Comment

I2Bus Write 0x50 0 : SA7110 Control Register
1 : AL251 Register Value
2 : AL128A Index
3 : AL128B
Select 0x51 0 : NTSC
PAL/NTSC 1 : PAL
Select 0x52 0 : System
Input Source 1 : VHS
(video source
1)
2: S-VHS

(video source
2)
Set 0x53
SAA7110 Reg
Set 0x54
AL128a Reg
Vm 0x55 b0 : real(0)
Freeze Real freeze(1)
b1: DT
disable(0)
enable(1)
Video 0x56 b[1..0] Not used
Key Control 0,2 – real
(VGA+imag
e)
mode
1 - only VGA
3 - only
image
Video Out 0x57 0 -- 800x600
800x600/640x480 1 -- 640x480
Select
Debug command
Image size 0xf0
640x480
VCR test Ntsc 0xf1
VCR test pal 0xf2
SG_Write 0xf3 Row addr data
One row
SG_Write 0xf4 Col addr data
One column
VS start 0xf6 Start point

5.4 Detail Fact

SA9900 can display 800 x 600 full size at monitor.
But ultrasound image expression zone is just 640 x 480 size. Also this part can display
external input such as VCR input.
VGA expression is Non-Interlace type, and it is normal PC monitor.
Input/Output of VCR is Interlace type, so it is necessary circuit composition to express
Interlace type.
And the section can divide ultrasound zone and VCR zone with black part and boundary

5.4.2 VCR INPUT

ANALOG VIDEO signal(VHS, S-VHS) to be transmitted from VCR is TV signal and
INTERLACE type signal. And TV image signal is divided NTSC, PAL, and SECAM type by
character of each region. So, it uses exclusive using chip like ONE CHIP FRONT
END1(SAA7110) to process each different input data, and executes A/D CONVERSION in
the inside. And it makes UV/Y FORMAT from INPUT ANALOG VIDEO signal by internal
CHROMINANCE CIRCUIT and LUMINANCE CIRCUIT. And it transmits to be changed
data.
7
1
CV-IN 3
+ 6
2 8
-
UV
4
5
7
1
Y-IN 3 VIDEO INPUT PROCESSOR

+ 6
2 SAA7110
-
8
Y
4
5
7
1
C-IN 3
+ 6
2
-
4
5

It is the part that express NON-INTERLACE type signal after changing the signal to be
transmitted from ONE CHIP FORNT END. Also, it transmits the result value after changing
R.G.B 565 and VCR SYNC (640 x 480). The R.G.B signal of 24BIT is transmitted from this
part. Also, this chip can support the interface by 12C PROTOCOL.
Square Pixel CCIR 601

NTSC PAL NTSC PAL
Pixel Total 780 x 525 944 x 625 858 x 525 864 x 635
Pixel Active 640 x 480 768 x 576 720 x 480 720 x 576
VCLKx2(MHZ) 24.545454 29.5 27 27
VCLK (MHZ) 12.272727 14.75 13.5 13.5

In IMAGE PART, B-MODE IMAGE, COLOR DATA, and ECG DATA to be transmitted from
DSC BOARD transmit to POST CONTROL. In this part, it transmits input signal according
MODE(B,C,ECG) to POST MAP after separating signal.

5.4.5 IMAGE GRABBER

REAL IMAGE signal and VCR signal is saved in IMAGE GRABBER, and IMAGE
GRABBER DATA works to make VIDEO SIGNAL after transmitting to OUTPUT FIFO. Also,
it works to transmitting IMAGE of IMAGE GRABBER to MAIN PC, or receiving that.
5.4.6 FIELD MEMORY

It has to transform the signal after matching synchronism with SYNC to display at VGA
MONITOR. FIELD MEMORY works this function. And FIELD MEMORY uses AL422, and
supports suitable RESOLUTION to use VGA and TV signal. AL422 is 3M-BITS FIFO FIELD
MEMORY, and it is possible to operate each READ/WRITE.
5.4.7 VIDEO KEY

IMAGE/VCR signal of 640 x 480 size to be transmitted from FIELD MEMORY is displayed
at MONITOR in 800 x 600 size with OVERLAY(VGA signal) or other MENU signal. In this
time, it is the part to do MUX with VGA signal.

DIGITAL RGB signal to be executed KEYING is transmitted to VGA MONITOR after
changing into ANLOG RGB through VIDEO DAC(TDA8772).
5.4.9 INTERLACE OUTPUT

It is necessary output signal to display at ECHO PRINTER or INTERLACE MONITOR
separately VGA signal, and it uses exclusive chip AL128. Also it is necessary FIELD
MEMORY to display 640 X 480 size or 800 x 600 size full image. In this FIELD MEMORY,
the signal to be executed MUX is transmitted to AL128 after output 640 x 480 signal.

5.4.10 SOUND I/O

This part works to come out sounds such as final output DOPPLER signal and SOUND to
be transmitted from VCR at SPEAKER. And first input DOPPLER signal is changed to
SERIAL signal by AD766
INVERT_AMP
6 SOUND_MUX_L
6 6 DA LPF
CONVERT
CPU_DATA HEX
BUFFER
BUFFER
INVERT_AMP
8 8 6
CPU_DATA OCTAL DA LPF SOUND_MUX_R
BUFFER CONVERT

5.5 Timing Chart

5.5.1 VGA SYNC TIMING
16.6ms
VGA_VS
VGA_HS
VGADOTCLK
26.3us
25ns
5.5.2 IMAGE SYNC TIMING
16.6ms
IMG_VS
IMG_HS
IMGDOTCLK
31.56us
40ns
5.5.3 IMAGE GRABBER
/HS
IFIFOWEN
IFIFOREN
OFIFOWEN
OFIFOREN

5.6 Wave Form

5.6.1 CH1 TP:/VGAVS CH2 TP :/VGAHS CH1 TP:/VGAHS CH2 TP :/VGABLK
CH3 TP :/VGADOTCLK
5.6.2 CH1 TP:/VGAHS CH2 TP :/VGABLK
5.6.3 IMAGE REALTION


5.6.3 SONOVIEW SIGNAL

5.6.4 KEYING SIGNAL


SonoAce9900 Section 2-6. Key Matrix Board
6.KEY MATRIX BOARD

It is the part to receive TGC,USERKEY, SET, D, C, PW, SOUND, ANGLE, POWER,TRACK
BALL.
KEY INTERFACE
BOARD
PC 86KEY BOARD
PUSH S/W JP10
12
ENCODER S/W
8
SLIDE VR
13
LED_OUT JP11
4
TRACK
BALL

SonoAce9900 Section 2-7. Key Interface Board
7.KEY INTERFACE BOARD
It controls KEY INTERFACE by using 89C51 MICRO-PROCESSOR. After making PLCC for
IN/OUT INTERFACE, MAX239 is used to interchange the data about USER KEY, ENCODER
KEY, and all kind of LED output control. TGC GAIN VOLUME can control the step of volume
until 255step by using AD-CONVERT.
7.1 BLOCK DIAGRAM
SPECIAL
PUSH
8 3-STATE 8 2 1
BUFFER
ENCODER
DATA ADDRESS IN/OUT S/W
8BIT MICRO CONTROL
PROCESSOR PLCC
LEDOUT
6 3-STATE
1 2
BUFFER
SA
8 8
ADC_CONVERT SLIDE
VR
SD_DATA ASL
UART RS239

SonoAce9900 Section 2-7. Key Interface Board
Port name Port Comment

address
D0 –D7 DATA
A0 – A7 ADDRESS
SD0-SD7 DATA when changing DIGITAL of AD/CONVERT
DATA of ENCODR S/W
/RD READ DATA of IN-OUT CONTROL
READ DATA of 8250 UART
/WR READ DATA of IN-OUT CONTROL
READ DATA of 8250 UART
/CS CHIP SELECT
LP SIGNAL to output LED PORT

ECD READ DATA of ENCODER S/W

SonoAce9900 Section 2-8. Mother Board.
8.MOTHER BOARD
MOTHER BOARD is CONNECTOR BOARD to be connected CW BOARD, DBF
BOARD(1,2,3,4), DSC BOARD, DSP BOARD, VIDEO MANAGER, PC BOARD. So, this part
receives each signal and power, or transmits that.
PC VM DSC DSP B/F 3 B/F 2 B/F 1 B/F 0 CW
J33A J24 J18 J20 J14 J11 J5 J2 J8
J33B J22 J16 J19 J13 J10 J4 J1 J7
U34 J23 J17 J21 J15 J12 J6 J3 J9
FRONT PART

SonoAce9900 Section 2-9. PC Board
9.PC BOARD
9.1 ROM BIOS SETTING
9.1.1 ENTER IN ROM BIOS
When check the RAM on turn on the POWER S/W of SA9900, if user presses the “DEL”
KEY several times, appear the MAIN sight as below;
ROM PCI/ISA BIOS(2A69KJFA)

CMOS SETUP
AWARD SOFTWARE, INC.
STANDARD CMOS SETUP LOAD SETUP DEFAULTS
BIOS FEATURES SETUP SUPERVISOR PASSWORD
CHIP FEATURES SETUP USER PASSWORD
POWER MANAGEMENT SET UP IDE HDD AUTO DETECTION
PNP/PCI CONFIGURATION SAVE & EXIT SETUP
INTEGRATED PERIPHERALS EXIT WITHOUT SAVING
ESC:Quit ↑↓→← : Select Item

F9: Load Sset Define F10:Save & Exit Setup (SHIFT)F2 :Charge Color
Set up the each MODE based on this table, and save the Rom Bios by pressing the F10 KEY..
9.1.2 STANDARD CMOS SETUP SETTING

ROM PCI / ISA BIOS (2A69KJFA)

STANDARD COMS SETUP
Date (mm:dd:yy) : Thu, Jul 4 1997
Time (hh:mm:ss) : 15 : 3 : 27
Type SIZE CYLS. HEAD PRECOMP LANDZ SECTOR MODE
Primary Master : AUTO 0 0 0 0 0 0 AUTO
Primary Slave : NONE 0 0 0 0 0 0 --------
Secondary Master : NONE 0 0 0 0 0 0 --------
Secondary Slave : NONE 0 0 0 0 0 0 --------
Drive A : NONE Base Memory: 640K

Drive B : NONE Extended Memory:130048K
Other Memory: 384K
Video : EGA/VGA ------------------------------------
Total Memory: 131072K
Halt On : All, But Keyboard
Esc : Quit áâàß : Select Item Pu/Pd/+/- : Modify

F1 : Help (Shift) F2 : Change Color

9.1.3 BIOS FEATURES SETUP SETTING

BIOS FEATURES SETUP
Virus Warning : Disabled Video BIOS Shadow : Enabled

CPU Internal Cache : Enabled C8000-CBFFF Shadow : Disabled
External Cache : Enabled CC000-CFFF Shadow : Disabled
CPU L2 Cache ECG Checking : Enabled D0000-D3FFF Shadow : Disabled
Quick Power On Self Test :Ennabled D4000-D7FFF Shadow : Disabled
Boot Sequence :C,A,SCSI D8000-DBFFF Shadow : Disabled
Swap Floppy Drive : Disabled DC000-DFFF Shadow : Disabled
Boot Up Floppy Seek : Disabled
Boot Up Numlock Status : ON
Gate A20 Option : Fast

Typematic Rate Setting : Enabled Esc : Quit áâàß : Select Item
Typematic Rate (Chars/Sec) : 30 F1 : Help Pu/Pd/+/- : Modify
Typematic Delay (Msec) : 250 F5 : Old Values (Shift)F2 : Color
Security Option : Setup F6 : Load BIOS Defaults
PCI/VGA Palatal snoop : Disabled F7 : Load Setup Defaults
OS Select For DRAM>64Mb : Non-OS2
Report No FDD for WIN95 :Yes
Display PnP/PCI Device List :No
9.1.4 CHIP FEATURES SETUP SETTING

CHIPSET FEATURES SETUP

Auto Configuration : Enable

EDO DRAM Speed Selection : 60 ns
EDO CASx# NA Wait State :2
EDO CASx# Wait State :2
SDRAM RAS –to-CAS Delay :3
SDRAM RAS Precharge :3
SDRAM CAS Latency Time :3
SDRAM Precharge CONTROL : Disabled
DRAM Data Integrity Mode : Non-ECC
System BIOS Cacheable : Disabled
Video BIOS Cacheable : Disabled
Video RAM Cacheable : Disabled
8 Bit I/O Recovery Time :3 Esc : Quit áâàß : Select Item
16 Bit I/0 Recovery Time :1 F1 : Help Pu/Pd/+/- : Modify
Memory Hole At 15M-16M : Disaabled F5 : Old Values (Shift)F2 : Color
Passive ReleaseDelayed : Enable F6 : Load BIOS Defaults
Delayed Transaction : Disabled
Auto Detect DIMM CLK : Enable

9.1.5 POWER MANAGEMENT SET UP SETTING

POWER MANAGEMENT SETUP
Power Management : Disabled ** Reload Global Time Events **
PM Control by APM : Yes IRQ[3-7,9-15],NMI : Disabled
Video Off Method : DPNS Primary IDE 0 : Disabled
Video Off After : Standby Primary IDE 1 : Disabled
MODEM Use IRQ : NA Secondary IDE 0 : Disabled
Doze Mode : Disable Secondary IDE 1 : Disabled
Standby Mode : Disable Floppy Disk : Disabled
Suspend Mode : Disable Serial Port : Enabled
HDD Power Down : Disable Parallel Port : Disabled
Throttle Duty Cycle :62.5%
PCI/VGA Act-Monitor : Disabled
Soft-Off by PWR-BTTN : Instand-Off Esc : Quit áâàß : Select Item
CPUFAN Off in Suspend : Enable F1 : Help Pu/Pd/+/- : Modify
PowerOn by Ring : Disabled F5 : Old Values (Shift)F2 : Color
IRQ8 Break Suspend : Disabled F6 : Load BIOS Defaults
F7 : Load Setup Defaults
9.1.6 PNP/PCI CONFIGURATION SETTING
ROM PCI / ISA BIOS (2A59FP6B)

PNP/PCI CONFIGURATION

PnP OS Installed : No Onboard VGA IRQ : Auto

Reset Controlled by Data : Disabled PCI DMAC IRQ : Auto
Reset Configuration by : Auto Onboard LAN IRQ : Auto
Onboard SOUND IRQ : Auto
USE IRQ : Auto
Esc : Quit áâàß : Select Item

F1 : Help Pu/Pd/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Defaults
9.1.7 INTEGRATED PERIPHERALS SETTING
ROM PCI / ISA BIOS (2A59FP6B)

INTEGRATED PERIPHERALS

IDE HDD Block Mode : Enabled Onboard FDD Controller :Enable

On-Chip Primary PCI IDE : Enabled Onboard Serial Port1 :3F8/IRQ4
Primary Master PIO : Auto Onboard Serial Port2 :2F8/IRQ3
Primary Slave PIO : Auto Serial Port2 Mode :Noraml
Primary Master UDMA : Auto
Primary Slave UDMA : Auto Onboard Serial Port3 :3E8/IRQ12
On-Chip Secondary PCI IDE : Enabled Onboard Parallel Port :378/IRQ7
Secondary Master PIO : Auto Parallel Port DMA :ECP+EPP
Secondary Slave PIO : Auto ECP Mode Use DMA :3
Secondary Master PIO : Auto EPP Mode Select :EPP1.9
Secondary Slave PIO : Auto USB Keyboard Support :Disabled
Video Font Expasion :Enabled
Esc : Quit áâàß : Select Item

F1 : Help Pu/Pd/+/- : Modify
F5 : Old Values (Shift)F2 : Color
F6 : Load BIOS Defaults

9.2 I/O Map PORT ADDRESS MAP

ADDRESS DEVICE
000-01F DMA CONTROLLER#1
020-03F INTERRUPT CPNTROLLER #1
040-05F TIMER
060-06F KEYBOARD CONTROLLER
070-07F REAL TIME CLO
080-08F INTERRUPT CONTROLLER #2
0F0 CLEAR MATH COPROCESSOR SINGAL
0C0-0DF DMA CONTROLLER #2
0F1 RESET MATH COPROCESSPR
0F8-0FF MATH COPROCESSPR
120 DISABLE WATHCDOG TIME OPERAQTION(READ)
121 ENABLE WATCHDOG TIME OPERATION(READ)
122 WATCHDOG
1F0-1F8 FIXED DISK CONTROLLER
200-207 GAME PORT
300-31F PROTOTYPE CARD
360-36F RESERVED
378-37F PARALLEL PORT
380-3F8 SDLC #2
SA0-3AF SDLC#1
3F0-3F7 FLOPPY DISK CONTROLLER
2F8-3FF SERIAL PORT #1(COM1)
2F8-2FF SERIAL PORT #2(COM2)
3F0 WINBOND I/O
9.3 INTERRUPT CONTROLLER
NMI PARITYCHECK ERROR

IRQ0 SYSTEM TIMER OUTPUT
IRQ1 KEYBOARD
IRQ2 INTERRUPT REROUTING FROM IRQ8 THROUGH IRQ15
IRQ3 SERIAL PORT #2
IRQ4 SERIAL PORT #1
IRQ5 RESERVED
IRQ6 FLOPPY DISK CONTROLLER

IRQ7 PARALLEL PORT #1

IRQ8 REAL TIME CLOCK
IRQ9 RESERVED
IRQ10 RESERVED(ONBOARD SCSI)
IRQ11 USB AND[ONBOARD NETWORK]
IRQ12 PS/2 MOUSE
IRQ13 MATH COPROCESSOR
IRQ14 PRIMARY IDE CHANNEL
IRQ15 SECONDARY IDE CHANNEL

SonoAce 9900 Section 3-1. Power Specification3
1.POWER SPECIFICATION
1.1 GENERAL
THIS UNIT SUPPLY INPUTTING AC POWER (90V-132V/180V-264V SINGLE PHASE) BY PWM

CONTROL OUTPUT (±5V, ±12V, +3.3V± 10～80V ±97V PC POWER) AND SUPPLY HIGH
VOLTAGE TO (URANUS MODEL) SWITCHING MODE POWER SUPPLY
1.2 FUNCTION
AC INPUT AUTO DELAY OFF

CONSTANT VOLTAGE OUTPUT
ARIABLE ARRAY OUTPUT VOLTAGE
OVER CURRENT PROTECTION ＆ OVER VOLTAGE PROTECTION
1.3 ELECTRONIC CHARACTERISTICS
1.3.1 INPUT CHARACTERISTICS
1.3.1.1 VARIABLE INPUT VOLTAGE RANGE

AC90V～132V & AC180V～AC264V SINGLE PHASE
1.3.1.2 RATED INPUT VOLTAGE

AC110V FIX & AC220V FIX
1.3.1.3 MAX INPUT CURRENT

9.4 MAX AT 85V AC
1.3.1.4 INRUSH CURRENT

100A MAX AT MAX OUTPUT/AC 110V INPUT
1.3.1.5 EFFICIENCY
65% AT MAX LOAD, MAX OUTPUT VOLTAGE, RATED INPUT
1.3.1.6 LEAKAGE CURRENT

100uA MAX at AC264V INPUT

1.3.2 OUT PUT CHARACTERISTICS
1.3.2.1 OUTPUT VOLTAGE ＆ CURRENT
INPUT VOLTAGE RANGE : AC90V～132V / AC180V～AC264V 50HZ ～ 60HZ
CURRENT REMARK
VOLTAGE
MIN TYP MAX MAX POWER
+ 3.5VBF 7A 8A 15A 52.5W
+ 3.5VD 5A 6A 12A 42W
+ 5.2VD 0A 3A 4A 21W
+ 12.2VD 0A 1.5A 2A 24.4W
- 12.2VD 0A 1.5A 2A 24.4W
+ 5.2VA 0A 3A 5A 26W
- 5.2VA 0A 3A 5A 26W
+ 12.2VA 0A 1A 3A 36.6W
- 12.2VA 0A 0.5A 1A 12.2W
+ 5.2VPC 5A 6A 14A 72W
+ 3.5VPC 1.2A 2.5A 3A 10.5A
+ 12.3VPC 0A 2A 3A 36.9W
- 12VPC 0A 1.5A 2A 24W

- 5.2VPC 0A 0.07A 0.1A 0.5W
+ 12V FAN 0.2A 0.7A 1A 12W
+97V 0A 100mA 200 mA 19.4W
-97V 0A 100mA 200 mA 19.4W

+10V～80V 0A 100 mA 200 mA 16W
-10V～80V 0A 100 mA 200 mA 16W
TOTAL 491.9W
1.3.2.2 REGULATION
? LINE REGULATION ( Below ±1% )
※ INPUT AC90V～132V / AC180V～AC264V OUTPUT TYP LOAD
? LOAD REGULATION ( Below ± 2% +0.1V )
※ INPUT AC110V/AC220V , OUTPUT MIN～MAX LOAD
? CROSS REGULATION ( Below ± 3% +0.1V )
※ OUTPUT MIN,TYP,MAX LOAD

1.3.2.3 PROTECTION
? OVER VOLTAGE PROTECTION : 120% ± 10% +1V
? OVER CURRENT PROTECTION : SHORT PROTECTION
If the power supply (except high voltage) is shortened the input voltage will be cut off and will be back to
normal if it turns on the power supply after removing the shortage.
1.3.2.4 RIPPLE ＆ NOISE

VOLTAGE RIPPLE NOISE
+5VD 50mVP-P 100mVP-P
+3.3VD,BF 33mVP-P 66mVP-P
±12VD 120mVP-P 240mVP-P
±5VA 50mVP-P 100mVP-P
±12VA 120mVP-P 240mVP-P
PC±5V 50mVP-P 100mVP-P
PC±12V 120mVP-P 240mVP-P
PC+3.3V 33mVP-P 66mVP-P
-5V 50mVP-P 100mVP-P
±80V 800mVP-P 1.6V
±97V 970mVP-P 1.94V
1.3.2.5 RISING TIME (+3.3VPC,+5VPC)

30mS MAX AT RATED LOAD, MIN INPUT VOLTAGE
1.3.2.6 FAIL TIME (+3.3VPC,+5VPC)

200mS MAX AT TYP LOAD, RATED INPUT VOLTAGE
1.3.2.7 OVER SHOOT (ALL OUTPUT)

MAX 5% AT RATED OUTPUT

AC INPUT
AC FAIL TIME
OVER
SHOOT
RATED
DC OUTPUT
OFF TIME
1.3.2.8 PC-POWER SUPPLY SEQUENCE

IN PUT : AC110V/60HZ
OUTPUT : TYP LOAD
SET UP TIME : 100mS～450mS *Ta , Te Deflection : Below 150mS
1.3.2.9 LOGIG DIAGRAM


1.3.2.9 BURN-IN TEST

CONDITION : LOAD - TYP LOAD , CIRCUMSTANCE TEMPERATURE - 40℃ , TIME-8HR
*TO THE ABOVE CONDITION, THE ELEMENT TEMPERATURE BELOW 90℃
1.3.3 SAFETY
1.3.3.1 * IEC 601-1 (SAFTY OF ELECTRIC MEDICAL EQUIPMENT)
* CISPR 11 CLASS A, VDE 0871 CLASS B
1.3.3.2 INSULATION RESISTANCE

20M ohm MIN AT 500V DC
1.3.3.3 WITHSTANDING VOLTAGE

AC 1.5KV PRIMARY ↔ FG
AC 4KV PRIMARY ↔ SECONDARY
1.3.4 ENVIRONMENT
1.3.4.1 TEMPERATURE
OPERATING : 0 ℃ ～ 40℃
STORAGE : -20 ℃ ～ 60℃
(+) STORAGE TEMPERATURE : SYSTEM NO OPERATION
(-) STORAGE TEMPERATURE : SYSTEM NO OPERATION
(+) OPERATING TEMPERATURE

(-) OPERATING TEMPERATURE
1.3.4.2 HUMIDITY
OPERATION : 10%-90% RH
STORAGE : 10%-90% RH
1.3.4.3 VIBRATION
FREQUENCY : 5 HZ -100 HZ
IMPULSE VOLUME: 1.0 G
SWEEP CYCLE : 5 MIN. 4 TIME
1.3.4.4 BURN-IN TEST

LOAD - TYP LOAD , CIRCUMSTANCE TEMPERATURE - 40℃ , TIME-8HR
1.3.4.5 OUTPUT SHORT & OPEN TEST

SHORT & OPEN : 10 TIMES
1.3.4.6 INPUT POWER ON-OFF TEST
USING BY AC ON/OFF SYSTEM 10 TIMES
1.3.4.7 DYNAMIC LOAD TEST

LOAD : MAX-MIN LOAD SWEEP (OR SWITCHING)
FREQUENCY : 1 HZ
RIPPLE NOISE BELOW 5%
1.3.5 MISC
1.3.5.1 DEMENTION : 260(L)×200(W)×400(H) (mm)

1.4 CIRCUIT DESCRIPTION

1.4.1 Input Circuit
Input power that is supplied from the AC CORD is supplied to TIME DELAY BOARD (OFF2000),
through the INLET(CR1) supplied to inductor(L1), and after L1 is filtering NOISE,
REF TRANS (T2) 1st coil is supplied to power when POWER SWITCH(CN106) is on, 2nd Voltage
of T2 supplied to CN2 of OFF2000, rectified and smoothed by BD1 C4
Smoothed DC power is derated 12V by Q2, 12V power is suppling to INPUT ON/OFF RELAY
(RY2.RY3) through D4, it is operating RELAY and TRIAC to RELAY PROTECTION OF A POINT OF
CONTACT TIME DIFFERENCE CIRCUIT
AC power is supplied to MAIN TRANSFORMER(T1) 1st COIL by way of RY2.RY3 points through
VOLTAGE SELECTOR (S2)
T1 is an INSULATING TRANSFORMER that is cut off the leakage current and, do INPUT
VOLTAGE CONTROL CAPACITY by S2. The 2nd Voltage is output 15V,19V and 110/220V
1.4.2 AC Output Circuit

110V of 2 nd Voltage goes to COLOR MONITOR OUTLET (CR4). Other 110V or 220V is selected
by S3 and goes to VCR OUTLET (CR3) and PRINTER OUT CONNECTOR (CN107).
1.4.3 DC Output Circuit

19V,15V out of 2nd Voltage in T1 make DC OUTPUT at AC TO DC SMPS and output DC voltage
to CN101～CN105.
1.4.4 AC OFF TIME DELAY CIRCUIT(OFF2000)

OFF TIME CONTROL BOARD (OFF2000) is BOARD that is when you finish the use of machine
and off the power switch, make a delay cut off the power as much as the time for saving the
operating data in disk
1.4.4.1 POWER SWITCH ON
When Input power switch turn on, the voltage to supply at CN2 supply at RY2 and RY3 through Q2
and D4. Voltage is supplied by R9 and D3, it is supplied to RELAY TIME DIFFERENCE
OPERATION CIRCUIT INPUT. When switch is on at once, RELAY and TRIAC operate by TIME
DIFFERENCE in order to protect the point of contact, so MAIN POWER is operating. Also this REF
power is operating U2 through R3. It is output LOW LEVEL when POWER SWITCH is ON at P/O
terminal of CN1 and it could maintain output PC BOARD when POWER SWITCH is OFF.
When RY2 and RY3 operate, main power will act and output voltage DC 12V is supplied to CN1. It
is supplied to RY2 and RY3 to REF power through D1 parallel. When REF power is intercept, it
takes charge of RELAY power supply

1.4.4.2 POWER SWITCH OFF

When POWER SWITCH is OFF, REF power is disappearance then MAIN 12V maintain this circuit.
At that time U2 which is operated by REF is off, and then output signal is changed H LEVEL.
PC BOARD know that POWER SWITCH is OFF caused by P/O SIGNAL, at once entering storing
work, when storage is finish, convert signal at P/B terminal to LOW. RELAY TIME DIFFERENCE
DRIVING CIRCUIT INPUT cut off caused by U2 makes off, then RELAY OFF-POWER became OFF
1.4.5 PROTECTION CIRCUIT

1.4.5.1 AC INPUT OVERCURRENT PROTECTION
All the 110/220V INPUT protect FUSE of INLET.
1.4.5.2 AC INPUT OVERVOLTAGE PROTECTION(OFF-2000PCB)

AC INPUT is supplied overvoltage, then 15VAC of CN2 in OFF2000 is supplied high.
When U3 detect INPUT VOLTAGE by R6,R13 in the OFF2000 BOARD, INPUT VOLTAGE entered
over standard, Q2 makes off through LED(LD1). RY2,RY3 stop operation
1.4.5.3 DC OUTPUT LOWVOLTAGE PROTECTION (OFF-2000PCB)

+POWER(except HV) that is supplied by CN11,12 connect U11 through D22-27, The
POWER(except HV) connect U5-U8. Within these voltage, signal of low-voltage inserted and then
U11 detected this voltage, U10,Q7,Q6 act consecutively. It is controlled RELAY action signal of U4,
RY2,3 do stop.
Once Q6 SCR act one time, act continuously until becoming below maintenance current, if low
voltage cut off one time, input make off, after SCR is OFF, Power have to put in on.

1.4.6.1 INPUT CIRCUIT (+5V +3.3V)
AC15V connected connector CN2 rectified D5.9, smoothed in smoothing condenser C33.40.
Through EMI FILTER L14,C78,42 cut off to input incoming or discharging noise, stabilized power
connect each converter input terminal.(F11,F12)
1.4.6.1.1 +5V OUTPUT CIRCUIT

DC voltage is inserted through FUSE is supplied to FET(Q5,6,7) through current detection C.T
connected parallel. FET acts by controlling of control circuit rapid switching, the pulse width
controlling send output. L4 C21,22,L5,C29,49,28 offer an output by removing ripple and noise.
1.4.6.1.2 SWITCHING CONTROL CIRCUIT

Control signal of FET(Q5,Q6,Q7) is supplied through R22,23,24 to SD-9002 CONTROL IC(U1)
PIN6 PWM output. CONTROL IC is formed sending IC(U1) PIN2 from detecting output +5V
Accoding to FEED BACK condition of PIN2, it controls pulse width wide or narrow
1.4.6.1.3 OVER VOLTAGE BREAK CIRCUIT

When power occur to disorder (FET SHORT etc), it happens overvoltage. At this time overvoltage
break circuit is neccesary to protect load machine. If +5V is detected by ZD2, detect over regular
voltage(output regularity’s 110-130%), Q8 will act compulsorily output has shorted, cut off the output
voltage. It is becoming low the output, OFF2000 circuit cut off the input power and protect the
machine.
1.4.6.1.4 OVERCURRENT PROTECTION

When strange of load machine or take overload caused by carelessness of treatment, it is
necessary overcurrent protection because of protection of POWER(SMPS). Current convert voltage
in C.T, current detection resistance(R20) happen to voltage proportioned to current wave. This
voltage supplied Condenser(C3) IC(U1)3rd pin, cut off the output wave become about over 1V.
Therefore that is becoming output overcurrent, pulse width make narrow and output voltage brings
down and limit the current.
1.4.6.1.5 +3.5V OUTPUT CIRCUIT

DC voltage is inserted through FUSE is supplied to FET(Q10,11) through current detection C.T
connected parallel. FET acts by controlling of control circuit rapid switching, the pulse width
controlling send output. L12 C38,39,L13, C36, 74,32 offer an output by removing ripple and noise.
(+3.5VD)

Control signal of FET(Q10,11) is supplied through R30,31 to SD-9002 CONTROL IC(U1) PIN6
PWM output. CONTROL IC is formed sending IC(U1) PIN2 from detecting output +3.5V

break circuit is neccesary to protect load machine. If +3.5V is detected by ZD3, detect over regular
voltage(output regularity’s 110-130%), Q12 will act compulsorily output has short cut off the output
machine.
1.4.6.2 INPUT CIRCUIT (+12VD -12VD)

AC19V connected connector CN2 rectified D12, smoothed in smoothing condenser C56,64.
Through EMI FILTER L22,C66,57 cut off to input incoming or discharging noise, stabilized power
connect each converter input terminal.(F13,F14)

1.4.6.2.1 +12V OUTPUT CIRCUIT

DC voltage is inserted through FUSE is supplied to FET(Q16,17) through current detection C.T
connected parallel. FET acts by controlling of control circuit rapid switching ,the pulse width
controlling send output. L19 C52,58,L9,C30,31 offer an output by removing ripple and noise.

PWM output. CONTROL IC is formed sending IC(U1) PIN2 from detecting output +12V

machine.

1.4.6.2.5 -12V OUTPUT CIRCUIT

DC voltage is inserted through FUSE is supplied to connect one side of coil of T2 through current
detection C.T and the other side of coil connect FET(Q18,19). FET acts by controlling of control
circuit rapid switching , current run to the (-), TRANS runs rapid switching current.
High frequency voltage caused by 2nd of TRANS rectified D19. L24,C65,66,L7,C26,27 offer an
output by removing ripple and noise.

PWM output. CONTROL IC is formed sending IC(U1) PIN2 from detecting output -12V and GND is
detected reverse voltage control signal of U5 by photocoupler


machine.

When strange of load machine or take overload caused by carelessness of treatment, it is necessary
overcurrent protection because of protection of POWER(SMPS). Current convert voltage in C.T,
current detection resistance(R43) happen to voltage proportioned to current wave. This voltage
supplied Condenser(C10) IC(U2)3rd pin, cut off the output wave become about over 1V. Therefore
that is becoming output overcurrent, pulse width make narrow and output voltage brings down and
limit the current
1.4.6.2.9 -5V OUTPUT CIRCUIT

Static voltage IC(U9) that is given power by –12V output makes –5V offer an output

1.4.7.1 INPUT CIRCUIT
AC19V connected connector TB1 rectified D3.8, smoothed in smoothing condenser C21,20.
Through EMI FILTER L13, C13,49,50 cut off to input incoming or discharging noise, stabilized power
connect each converter input terminal.(F1,2,3,5)
1.4.7.1.1 +12VA OUTPUT CIRCUIT

DC voltage is inserted through FUSE is supplied to FET(Q3) through current detection C.T
connected. FET acts by controlling of control circuit rapid switching, the pulse width controlling
send output. It is smoothed in L4,C11, stabilized +12V through LOW DROP IC(U3).
C10,15,L3 offer an output by removing ripple and noise.

Control signal of FET(Q3) is supplied through Q1 to S D-9001 CONTROL IC(U1) PIN6 PWM output.
CONTROL IC is formed sending IC(U1) PIN2 from detecting output +12V

necessary overcurrent protection because of protection of POWER(SMPS). Current convert
voltage in C.T, current detection resistance(R14) happen to voltage proportioned to current wave.
This voltage supplied Condenser(C3) IC(U1)3rd pin, cut off the output wave become about over 1V.
down and limit the current

1.4.7.1.4 +12V FAN OUTPUT CIRCUIT

It is Supplied by +12VA LOW DROP IC of input terminal and offer an output after Static voltage IC
makes Static voltage
1.4.7.1.5 +5VA OUTPUT CIRCUIT

DC voltage is inserted through FUSE is supplied to FET(Q4) through current detection C.T
connected. FET acts by controlling of control circuit rapid switching, the pulse width controlling
send output. It is smoothed in L12,C24,39, stabilized +12V through LOW DROP IC(U3).
L7,C16,22,39 offer an output by removing ripple and noise.

Control signal of FET(Q4) is supplied through Q1 to S D-9001 CONTROL IC(U1) PIN6 PWM output.
CONTROL IC is formed sending IC(U1) PIN2 from detecting output +5VA

1.4.7.1.8 -5VA OUTPUT CIRCUIT

DC voltage is inserted through FUSE is supplied to connect one side of coil of T2 through current
detection C.T and the other side of coil connect FET(Q6,7). FET acts by controlling of control circuit
rapid switching, current run to the (-), TR runs rapid switching current.
High frequency voltage caused by 2nd of TR rectified D6. It is smoothed in L14,C31, stabilized -
5VA through LOW DROP IC(U51). L8,C29 offer an output by removing ripple and noise.

Control signal of FET(Q6,7) is supplied through R43,47 to SD-9002 CONTROL IC(U9) PIN6 PWM
output. CONTROL IC is formed sending IC(U1) PIN1 from detecting output -5VA


necessary overcurrent protection because of protection of POWER(SMPS). Current convert
voltage in C.T, current detection resistance(R37) happen to voltage proportioned to current wave.
This voltage supplied Condenser(C52) IC(U9)3rd pin, cut off the output wave become about over
1V. Therefore that is becoming output overcurrent, pulse width make narrow and output voltage
brings down and limit the current
1.4.7.1.11 -12VA OUTPUT CIRCUIT

High frequency voltage caused by 2nd of TR rectified D9. It is smoothed in L14, stabilized -12VA
through LOW DROP IC(U6). L11,C33 offer an output by removing ripple and noise.
1.4.8.1 ±HV ,±97V OUTPUT CIRCUIT

1.4.8.1.1 SWITCHING CIRCUIT
DC voltage is inserted through FUSE is supplied to connect one side of coil of TRANS(T1) through
current detection C.T and the other side of coil connect FET(Q12). FET acts by controlling of
control circuit rapid switching , current run to the (-), TRANS runs rapid switching current.

FET(Q12) is supplied through resistance(R83) at CONTROL IC(U19) PIN6. CONTROL IC is
formed sending IC(U19) PIN1 from detecting voltage of D28.
1.4.8.1.3 +10～80V OUTPUT CIRCUIT

High frequency voltage caused by 2nd of TRANS rectified D28 and filtering by L28,81,80,59 and
makes +97V DC. U22 inverts control signal(0~5V) and use the reference voltage of +HV
CONTROL IC(U16). Following the reference voltage, U16 give Q13 to act, and adjust +10～80V.
1.4.8.1.4 -10～-80V OUTPUT CIRCUIT

High frequency voltage caused by 2nd of TRANS rectified D27 and filtering by L20,79,78,56 and
makes -97V DC. U22 inverts control signal(0~5V) and use the reference voltage of -HV CONTROL
IC(U16). Following the reference voltage, U16 give Q9 to act, and adjust -10～-80V

necessary overcurrent protection because of protection of POWER(SMPS). The current of 1st
TRANS runs through FET pass by current detection resistance(R90,95). At this time current wave
comes into being proportioned to current wave at current detection resistance. This wave supply
Condenser(C71) IC(U19)3rd pin, cut off the output wave become about over 1V. Therefore that is
becoming output overcurrent, cut off the current lower output voltage because pulse width is narrow.

Current limitation of 2nd side is that +80V restain Q15 Q14 by current run to R92, –80V restain Q11
Q10 by current run to R80
1.4.1.8.6 OUTPUT SHORT INTERCEPTION

When high voltage output is short for a long time, Q14 and Q10 will happen damage by emitting
heat. In order to prevent, add the timer circuit , ±HV act SHORT U13,14 and charge time(about 5
sec) later in C51, acting U2. It cuts off acting of U22 through Q8 and cannot send output.
1.4.1.8.7 ±HV CONSTANT VOLTAGE PROTECTION CIRCUIT

In case of ±HV output, it maybe needs 20~40V. At this time if FET INPUT VOLTAGE is high, FET
has dropping voltage many, FET occur to a lot of heat. To prevent the case, it compares to HV
CONTROL at U25. If it is below 2.5V, it permits about 56V, and if it is over 2.5V, it acts relay and
permit 97voltage.
Then it changes setting value of OUTPUT O.V.P
1.4.1.8.8 FAN DISORDER GENERATION PROTECTION CIRCUIT

In order to take precautions against stopping fan caused by disorder of fan or other
reasons, U25 makes acting of POWER stop by driving OFF circuit as a result of detecting
HIGH LEVEL

SonoAce9900 chapter 2

SonoAce9900 Section 3-2. MOD
2. MOD
2.1 MCD3130AP : Magneto-Optical Drive characteristics
Fujitsu's new MCD3130AP drive has achieved the highest capacity of any 3.5-inch
magneto-optical drive by using new Magnetically induced Super Resolution (MSR)
technology.
MSR technology allows the drive to read and write any GIGAMO standard 1.3GB
disk at twice the liner bit density. The MCD3130AP drive also delivers a faster data
transfer rate of up to 5.9MB/sec., and provides 28 millisecond seek time. The
MCD3130AP drive also retains full read/write compatibility with ISO/IEC 3.5- inch
disks ranging from original 128MB to current 640MB.
Protecting Investments in Data

MO disks are nearly indestructible, and completely immune from the problems that
plague magnetic media. Shock, vibration, moisture, dust, x-rays and magnetic
fields can't destroy data stored on an MO disk. And because of their ruggedness,
these disks make the perfect medium for office, home or industry. MO disks can be
rewritten an unlimited number of times.
High Performance Rewritable Storage
The MCD3130AP provides two high performances depending on the MO disk to

use. When using a standard 1.3GB GIGAMO disk, the maximum transfer rate is
5.9MB/sec. with 3,214rpm rotational speed. When using a standard ISO disk, the
maximum transfer rate is 4.9MB/s with 4,500rpm rotational speed, which is 25%
faster than the conventional MCC3064, 640MB MO series.
Broad Disk Options

The MCD3130AP's read/write compatibility with all ISO standard disks means big
user benefits. Protecting your previous investment of data on ISO standard disk
comes first. The second big benefit is that you have the broad disk options among
today's removable products. No other removable solution offers you such a variety
of capacity selection, including 128, 230, 540, 640MB and 1.3GB, depending on
the usage.
2.2 MOD SPEC.
MODEL MCD3130AP
Storage Capacity by Disk 1.3GB
Sector Capacity 2,048Byte
Max* 3.46 to 5.92MB/s
Data Drive write 0.88 to 1.50MB/s

Transfer read 2.63 to 4.50MB/s
Rate
PIO mode 4 : 16MB/s
Interface/ATAPI
multiword DMA mode 2 : 16MB/s
Seek Time(TYP) 28ms
Average Latency Time 9.3ms 6.7ms
Rotational Speed(TYP) 3,214rpm 4,500rpm
Load Time 12s 8s
Unload Time 4s
Interface ATAPI(ATA/ATAPI-4)
Buffer size 2MB
Power Requirements +5V DC +/-5%
Dimensions (WxDxH)
101.6 x 150.0 x 25.4 mm
(Single bezel)
Weight 465g (with bezel)
Acoustic noise Less than 38dB
Ready 4.5W
Power
Random R/W 5.6W
Consumption
Sleep 0.6W
o o o
Ambient Operating 5 C to 45 C(15 C/h)10 to 85%

temperature
Operating 0.4G(5-500Hz)
Vibration
Non-operating 1.0G(5-500Hz)
Operating 2.0G
Shock
Non-operating 5.0G

2.3 MOD JUMPER SETTING

2.3.1 FACTORY SETTING (slave setting)
Figure 1 shows jumper settings at factory shipping.
2.3.2 Mode setting
2.3.2.1 Setting master device mode

Figure 2 shows the setting for recognizing the master device.
(device 0)
Figure 2. Master device setting
2.3.2.2 Setting slave device mode

Figure 3 shows the setting for recognizing the slave device.
(device 1)
Figure 3. Slave device setting

2.3.2.3 Setting cable select mode

Figure 4 shows the master device/slave device setting when the CSEL signal is connected to
the interface. In the example shown in Figure 5 this setting requires a special interface
connection.
Figure 4. Cable select mode setting
Figure 5 shows a cable select example using a special interface cable.

The example connects CSEL of the master device to the CSEL line (conductor) of the cable,
then ground it so that the device recognizes that it is the master. At this time, the CSEL
conductor of the slave device is removed and cannot be connected to CSEL of the cable, so
that the drive recognizes that it is the slave.
Example 1
Example 2
Figure 5. Cable select example

SonoAce9900 Section 3-3. CR R/W
3. CR R/W
3.1 CD R/W DRIVE CHARACTERISTICS

- Produce「Full Package」for making CD in personal computer
- Writing/Playing for variable CD-R, CD-RW disk
- Low-noise and low-vibration realization by reverse resonance
- Easy form-ware upgrade by sticking flash ROM
- Adoption 2MB Buffer for preventing Buffer Under-run
- Adoption E-IDE interface attach easy on normal PC
- Data backup is easy like floopy disk
- Product audio CD or CD-ROM for oneself
- Permanent storage of data in the office and government and public office
- Storage a lot of information of MAX 650MB
3.2 CD R/W using recommendation disk

CD-R : Mitshubishi Chemical, Taiyo Yuden
Richo, Mitsui, Kodak, TDK, SKC, Maxwell
CD-RW : Mitshubishi Chemical, Richo
3.3 CD R/W SPEC.
Product name CED-8120B
Manufacturer LG Electronics
Interface EIDE within machine
Maximum transmission ratio 4,800 KB/sec
Multiple 12X / 8X / 32X
CD-R/RW, CD-DA, CD-ROM, CD-I, CD-ROM

Support Format
XA, Photo CD, Video CD, CD-Extra
Buffer 8 MB
Characteristic Internal mode, Tray loading mode
IBM Pentium processor(200MHz),

Minimum system specification Microsoft Windows 95B, Windows 98,
NT Workstation (SP4), 32MB Ram

SonoAce9900 Section 3-4. HDD
4.HDD
4.1 HDD SPEC(.FIREBALL LCT10-20.4GBYTE)
QUANUM FIREBALL lct10 20.4Gbyte
FORM FACTOR 3.5INCH(LOW PROFILE)
INTERFACE ULTRA ATA/66
FORMATTED CAPACITOR(MB2) 20.4168
4.2 DISK DRIVE ORGANIZATION

RECORDING SURFACE 4
ATA LOGICAL CYLINDER 16.383
HEADS 16
SECTORS 63
4.3 CAPACITY SPEC.

TYPICAL SEEK TIMES(ms)
AVERAGE 9.5
TRACK TO TRACK 2.0
FULL STOKE 18.0
AVERAGE ROTATIONAL LATENCY(ms) 5.56
ROTATIONAL SPEED(RPM) 5,400
INTERAL DATA RATE(Mb/sec) UP TO 297
DATA TRANSFER RATES(BUFFER TO
HOST)
ULTRA DMA/66 66.6MB/SEC
PIO MODE 4 16.6MB/SEC
DMA MODE 2 16.6MB/SEC
BUFFER SIZE(KB) 512
TYPICAL POWER ON TO DRIVE 8
READY(SEC)
4.4 POWER SPEC.

NORMINAL VOLTAGE(V) +5/+12
VOLTAGE MARGIN(%) ±5/±10
TYPICAL POWER DRAW(W)
IDLE 5.0
OPERATION 8.5

SonoAce9900 Section 3-4. HDD
4.5 JUMPER SETTING

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Service Manual Published by SERTECH

1.4.2 Receive Channel

Service Manual Published by SERTECH

Service Manual Published by SERTECH

5.4.9 Interlace Output

Service Manual Published by SERTECH

12.2.8 MOTHER BOARD

Service Manual Published by SERTECH

Service Manual Published by SERTECH

Upon arrival, inventory the shipment with the carrier’s driver.

During formal inspection, you should :

1.2 UNPACKING INSTRUCTIONS

2-1 To unpack the 15” VGA monitor

2-2 To unpack the unit

Service Manual Published by Customer Service Department

Service Manual Published by Customer Service Department

2.2 SAFETY PRECAUTIONS

2.2.1 Physical Safety Precautions

2.2.2 Mechanical Safety Precautions

① Equipment brake system

② Moving the equipment

Service Manual Published by Customer Service Department

2.2.3 Electrical Safety Precaution

n Before starting to use the system, check the following .

Detail 2. SA9900 Main Console Safety Ground

Service Manual Published by Customer Service Department

Service Manual Published by Customer Service Department

2.2.4 SAFETY SYMBOLS

Isolated patient connection (IEC 601-1-Type BF)

I and O on power switch represent ON and OFF, respectively.

VGA Output port or Parallel port

Modem or RS232 Input/Output port

Left/Right Audio Input or Video Input port

Left/Rig Left/Right Audio Output or Video Output port

Print Remote Output

Service Manual Published by Customer Service Department

2.3 MAINTENANCE AND PROTECTION

To disinfect clean surface of system as following :

To disinfect surface of system, should do by antiseptic solution is provided by Medison.

Service Manual Published by Customer Service Department

2.3.2 CLEANING FOR GENERAL PURPOSE PROBE

Service Manual Published by Customer Service Department

① Separate the probe from system.

Sterilization and antiseptic

Sterilization Manufacture Form Solution FDA 510(k)

Service Manual Published by Customer Service Department

Service Manual Published by Customer Service Department

2.3.3 Using Probe Correctly

2.3.4 Protect Circuit : Fuse Replacement

Regular Fuse Electricity

Input Electricity Fuse Electricity

Service Manual Published by Customer Service Department

Kauttu. Box Fuse

Figure-A. Appliance INLET

Fuse Holder Fuse

Figure-B. Side view of Figure-C. Inserting Fuse and

Service Manual Published by Customer Service Department

2.4 SYSTEM COMPONENTS

Part Name Description Qty.

Service Manual Published by Customer Service Department

3. Installation Guide for SA9900

Avoid the following environments for operation or storage

① Where the equipment is exposed to water vapor.