Infineon Power Cookbook

DC-DC Power Solutions for FPGAs:

Xilinx Zynq UltraScale+ MPSoC

revision 0.1
Solution Brief
DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Infineon offers Scalable Solutions for SoC

Infineon offers scalable power solutions for Xilinx Zynq UltraScale from Zu02
to Zu19 for the CG, EG and EV series featuring our new Multi-output PMIC, FPGA
IRPS5401.

Highlights
> IRPS5401 5 Output DC/DC PMIC
Four Regulators and LDO. Full PMBus ready
Integrated sequencer eliminates need for external controller
Full Digital compensation. No external components
Compact space design: 19.3 mm x 15mm
www.infineon.com/xilinx
> IR3883 Easy COT DC/DC Regulator, 1A to 3A

3.5 inches (76.2 mm)

Infineon
Compact IRPS5401
2 inches
Power
(50.8 mm)
Design for
FPGA/SoCs,
IRPS5401 IRPS5401
 Solution Brief: Power for FPGAs 2

www.infineon.com/xilinx
DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC
Power Map - Zynq UltraScale+ MPSoC - Zu02 and Zu03 with Low Power and Full Power Control
UltraZed-EG™ SOM
IRPS5401 Bourns 3.3uH
SRP5030T 0.85V / 3.7A 1 VCC_PSINTFP/VCC_PSINTFPDDR
Switcher D

Sequencing
& Ramp φ_D*
Vin 12V, 5V 1x220uF 47uF
Control 22uF UltraZed IO Carrier Card
PGood <A:D> Bourns 1.5uH
SRN2512-1R5M 0.85V / 0.6A 1 VCC_PSINTLP 1
Switcher C

EN <A:D> EN <A:D> VPS_MGTRAVCC

φ_C*
1x220uF 47uF 22uF
Optional only for SERDES
Timing &
Phase
Bourns 1.5uH IRPS5401 Bourns 1.5uH
2 0.85V / 2A
Switcher B

PMBus 1.2 SRN2512-1R5M 1.8V / 1.1A VCCAUX, VCCADC, VCCAUX_IO SRN2512-1R5M

Switcher D
Fault φ_B Sequencing
Management & Ramp φ_D*
1x220uF
Vin 12V, 5V
1x220uF 47uF
1 x22uF Control 22uF
Bourns 1.5uH PGood <A:D>
Telemetry
SRN2512-1R5M 1.8V / 0.5A 2 VCCO_PSIO (0:3) Bourns 3.3uH
USB UART, LVDS drive,
Switcher A

φ_A PMOD, LEDs, Arduino

Switcher C
EN <A:D>
VCCO_PSADC, VCC_PSAUX φ_C*
SRP5030T 3.3V / 3A
Configuration 1x220uF 1 x22uF
Timing &
LDOin
Memory
2 VCC_PSPLL Phase
1x220uF 47uF 22uF
LDO

Switcher B
USB3.0 and Arduino
5V PMBus 1.2 Fault φ_B 5V/ 1.5A
REG 7mm x 7mm
1 x22uF Zynq UltraScale+ Management
MPSoC 1x220uF 47uF 22uF
XCZU3EG-SFVA625 Telemetry
Bourns 1.5uH 2
SRN2512-1R5M
1.8 / 0.5A

Switcher A
φ_A
VCCIO
IRPS5401 Bourns 3.3uH
SRP5030T
0.85V / 4A
1 Configuration 1x220uF 1 x22uF
VCCINT
Switcher D

Sequencing
φ_D*
Memory 2
Vin 12V, 5V & Ramp 1.8V / 0.3A
1x220uF 47uF LDOin LDO
Control 22uF

EN <A:D>
PGood <A:D> Bourns 3.3uH system 1 x22uF
SRP5030T
3.3V / 1A voltage 7mm x 7mm
Switcher C

EN <A:D>
φ_C*
Timing & 1x220uF 47uF 22uF
Phase 2
Bourns 1.5uH
1 VPS_MGTVTT
Switcher B

PMBus 1.2 Fault φ_B

SRN2512-1R5M 0.85V / 0.6A VCCINT_IO / VCCBRAM
Management
1x220uF 1 x22uF
Bourns 1.5uH
Telemetry SRN2512-1R5M 3 VCCO_PSDDR4_504
Switcher A

φ_A 1.2 / 1.2A

Configuration 1x220uF 1 x22uF Power Mode
Memory
2 SOM LP FP
LDOin
LDO
1.8V / 0.5A VCC_PSDDR_PLL
VCCPSINTLP on on
7mm x 7mm
1 x22uF 3.3V VCCPSINTFP off on
LDO 1.0V Enet PHY Enet PHY, OSC 24MHz
2.5V CH Switches USB Flash Controller VCCINT_IO / VCCBRAM off on
3.3V NAND Flash, REF VCCINT off on
input DDRx DDRx_VREF Logic / Supervisors
1.2V Reg DDRX_VTT VCCPSAUX / VCCPSIO (0:2:3) / PSBATT on on
Term outputs
VCCPLL on on
VCCDDR / VCCO / DDR4 devices off on
VCCAUX / AUX_IO / VCCO / ENET PHY off on
VCCO off on
VCCO / ENET PHY off on
VTERM off on
ENET PHY off on

Fully integrated power sequencer - shown Infineon PowIRCenter GUI to set sequencing - 15 power rails
 Solution Brief: Power for FPGAs 3

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DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Power Solution - High Level - Zynq UltraScale+ - Zu02 / Zu03 - CG / EG / EV Series

UltraZED Reference Design

Zu02/03 UltraZED Design

ZYNQ UltraScale+ CG - EG - EV Series
With SERDES option
Always On Always On
Rail Consolidation Zu02
Zu03
Configuration 1
IRPS5401
ZYNQ US+ MPSoC Ch A 3 Auxiliary supply 1.8V - 0.5A

VCCINT 0.85/0.9V Ch B 2 Auxiliary supply 1.8V - 1.1A

1a 1.1-3.3V VCCO (HDIO)
U1 Ch C 1d Core Voltage 0.85V - 0.6A
VCCAUX 1.8V 1-1.8V VCCO (HPIO)
2 Ch D 1c Core Voltage 0.85V - 3.7A
VCCAUX_IO 1.8V
0.85 / 0.9V VMGATAVCC LDO 8 SERDES / PLL 1.2V 1.2V - 0.5A
VCCADC 1.8V
1.8V VMGTAVCCAUX 7
1.2V VMGTAVTT
8 Configuration 2
VCCBRAM 0.85/0.9V 0.85 / 0.9V VMGTYAVCC
IRPS5401
Ch A 5 DDR (VCCO_PSDDR4) 1.2V - 1.2A
1b VCCINT_IO 0.85/0.9V 1.8V VMGTYAVCCAUX
1.2V VMGTYAVTT Ch B 1b Core Voltage 0.85V - 0.6A
U2 Ch C 9 System Voltage 3.3V 3.3V - 1A
PS 1.2V VCC_PSPLL
Ch D 1a Core Voltage 0.85V - 4A
VCC_PSINTLP 0.85/0.9V VCCO_PSIO (0:3)
1d 1.8- 3.3V LDO 4 VCC_PSDDR_PLL 1.8V - 0.5A
VCC_PSINTFP 0.85/0.9V
1c VCC_PSINTFPDDR 0.85/0.9V 1.1 - 1.5V VCCODDR 5
Configuration 3
IRPS5401
VCC_PSAUX 1.8V 12 VCCIO system 1.8V - 0.5A
0.85/0.9V VPS_MGTRAVCC 6 Ch A
3 VCCO_PSADC 1.8V
1.8V VPS_VMGTAVTT Ch B 11 System Voltage 5V 5V - 1.5A
VCC_PSDDR_PLL
4 1.8V U3 Ch C 10 System Voltage 3.3V 3.3V - 3A
Ch D 6 SERDES 0.85V 0.85V - 2A
LDO 7 SERDES 1.8V 1.8V - 0.3A

U1, U2 on UltraZED SOM

Consolidation
Suggested User Consolidation U3 on UltraZED Carrier

Example Layout Design Per IRPS5401 PMIC

UltraZED Reference Design
(including inductors and capacitors):

19.3mm x 15.3mm - 5 Outputs
 Solution Brief: Power for FPGAs 4

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DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Power Solution - High Level - Zynq UltraScale+ - Zu02 to Zu09 - CG / EG / EV Series

Power Always On

Zu02/03/04/05/06/07/09
CG - EG - EV Series
No SERDES
Always On
ZYNQ UltraScale+
IRPS5401
Always On Ch A TDA21240/2 1 Core Voltage
Rail Consolidation Ch B 2 DDR (VCCO_PSDDR4)
Ch C 3 PS I/O supply
Ch D 4 Auxiliary supply
LDO 5 PS PLL supply
ZYNQ US+ MPSoC
1 VCCINT 0.85/0.9V 1.1-3.3V VCCO (HDIO) IR3883 System Voltage 3.3V
VCCAUX 1.8V 1-1.8V VCCO (HPIO)
4 TDA21240 (<25A-35A) - Zu07, Zu09
VCCAUX_IO 1.8V
0.9V VMGATAVCC 7 TDA21242 (<16A) - Zu02, Zu03, Zu04, Zu05
VCCADC 1.8V
1.8V VMGTAVCCAUX
6
VCCINT_VCU 0.85/0.9V 1.2V VMGTAVTT Zu02/03/04/05/06/07/09
5
VCCBRAM 0.85/0.9V 0.9V VMGTYAVCC CG - EG - EV Series
VCCINT_IO 0.85/0.9V 1.8V VMGTYAVCCAUX With SERDES
1.2V VMGTYAVTT Always On
PS 1.2V VCC_PSPLL IRPS5401
Ch A TDA21240/2 1 Core Voltage
VCC_PSINTLP 0.85/0.9V VCCO_PSIO (0:3)
1.8- 3.3V 3 Ch B 2 DDR (VCCO_PSDDR4)
VCC_PSINTFP 0.85/0.9V
Ch C 3 PS I/O supply
VCC_PSINTFPDDR 0.85/0.9V 1.1 - 1.5V VCCODDR 2 Ch D 4 Auxiliary supply
VCC_PSAUX 1.8V LDO
0.85/0.9V VPS_MGTRAVCC 8
5 PS PLL supply
VCCO_PSADC 1.8V
1.8V VPS_VMGTAVTT IR3883
VCC_PSDDR_PLL 1.8V IRPS5401
Ch A System Voltage 3.3V
Ch B 6 SERDES 1.8V

Recommend Consolidation Ch C 7 SERDES 0.9V

Suggested User Consolidation Ch D 5 SERDES 1.2V
LDO 8 SERDES 0.85V

TDA21240 (<25A-35A) - Zu07, Zu09

TDA21242 (<16A) - Zu02, Zu03, Zu04, Zu05
 Solution Brief: Power for FPGAs 5

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DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC
Power Solution - High Level - Zynq UltraScale+ - Zu02 to Zu09 - CG / EG / EV Series
Power Always On

Use Case 1: Always On Zu02 to Zu09

Zu02_04_05-CG-EG-EV No SERDES
Rocky# Vin Channel Rails Vout Pwr Specs Power Stage Iout (A)
VCC_PSINTFP/VCC_PSINTFPDDR,
0.85/0.9 +/-1% (AC 2%),
Ch A VCCINT_IO / VCCBRAM, VCC_PSINTLP, 0.85V TDA2124x 16A
1/3 Imax step
VCCINT

Ch B VCCO_PSDDR4_504 1.2V 1.2V 1% DC; 3%AC Integrated 1.5A

Ch C VCCO_PSIO (0:3) 1.8V 1.8V 2% DC; 3%AC Integrated 1A

IRPS5401
5V/15V VCCAUX, VCCADC, VCCAUX_IO,
U1 1.8 +/-1% (AC 2%),
Ch D VCC_PSDDR_PLL, VCCO_PSADC, 1.8V Integrated 4A
1/3 Imax step
VCC_PSAUX, VCCIO (0.5A)

LDO out VCC_PSPLL 1.2V Integrated 0.5A

LDO in 3.3V / IR3883 system voltage

Use Case 1: Always On Zu02 to Zu09

Zu07CG-EG-EV No SERDES
Rocky# Vin Channel Rails Vout Pwr Specs Power Stage Iout
VCC_PSINTFP/VCC_PSINTFPDDR,
0.85/0.9 +/-1% (AC 2%),
Ch A VCCINT_IO / VCCBRAM, VCC_PSINTLP, 0.85V TDA2124x 25A
1/3 Imax step
VCCINT

Ch B VCCO_PSDDR4_504 1.2V 1.2V 1% DC; 3%AC Integrated 1.5A

Ch C VCCO_PSIO (0:3) 1.8V 1.8V 2% DC; 3%AC Integrated 1A

IRPS5401
5V/15V
U1 VCCAUX, VCCADC, VCCAUX_IO, VCC_PSDDR_PLL, 1.8 +/-1% (AC 2%),
Ch D VCCO_PSADC, VCC_PSAUX, VCCIO (0.5A)
1.8V Integrated 4A
1/3 Imax step

LDO out VCC_PSPLL 1.2V Integrated 0.5A

LDO in 3.3V / IR3883 system voltage

Use Case 1: Always On Zu02 to Zu09

Zu09CG-EG-EV No SERDES
Rocky# Vin Channel Rails Vout Pwr Specs Power Stage Iout (A)
VCC_PSINTFP/VCC_PSINTFPDDR,
0.85/0.9 +/-1% (AC 2%),
Ch A VCCINT_IO / VCCBRAM, 0.85V TDA2124x 25A
1/3 Imax step
VCC_PSINTLP, VCCINT

Ch B VCCO_PSDDR4_504 1.2V 1.2V 1% DC; 3%AC Integrated 1.5A

Ch C VCCO_PSIO (0:3) 1.8V 1.8V 2% DC; 3%AC Integrated 1A

IRPS5401
5V/15V VCCAUX, VCCADC, VCCAUX_IO,
U1 1.8 +/-1% (AC 2%),
Ch D VCC_PSDDR_PLL, VCCO_PSADC, 1.8V Integrated 4A
VCC_PSAUX, VCCIO (0.5A) 1/3 Imax step

LDO out VCC_PSPLL 1.2V Integrated 0.5A

LDO in 3.3V / IR3883

 Solution Brief: Power for FPGAs 6

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DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Power Solution - High Level - Zynq UltraScale+ - Zu02 to Zu09 - CG / EG / EV Series

Power Always On

Use Case 2: Always On, Power Efficiency, Zu04 to Zu07 with Video Codec
Zu04_05EV No SERDES, Video codec Zu07EV No SERDES, Video Codec
Rocky# Vin Channel Rail Vout Pwr Specs Power Stage Iout (A) Rails Vout Pwr Specs Power Stage Iout (A)
0.72V +/-1% (AC 2%), 0.72V +/-1% (AC 2%),
Ch A VCCINT 0.72V TDA2124x 9A VCCINT 0.72V TDA2124x 15A
1/3 Imax step 1/3 Imax step
Ch B system voltage 3.3V 3.3V 5% Integrated 1.1A (2A) system voltage 3.3V 3.3V 5% Integrated 1.1A (2A)

Ch C Integrated Integrated
VCC_PSINTFP/ VCC_PSINTFPDDR,
0.85/0.9 +/-1% (AC 2%), VCC_PSINTFP/ VCC_PSINTFPDDR, 0.85/0.9 +/-1% (AC 2%),
IRPS5401 VCCINT_IO / VCCBRAM, 0.85V 7A 0.85V 7A
5V/15V 1/3 Imax step VCCINT_IO / VCCBRAM, VCC_PSINTLP 1/3 Imax step
U1 VCC_PSINTLP
Ch D Integrated Integrated

LDO out VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A

LDO in 3.3V / Ch B 3.3V / Ch B

Ch A VCCO_PSIO (0:3) 1.8 1.2V 1% DC; 3%AC Integrated 1A VCCO_PSIO (0:3) 1.8 1.2V 1% DC; 3%AC Integrated 1A

Ch B VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.5A VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.5A

VCCAUX, VCCADC, VCCAUX_IO, VCCAUX, VCCADC, VCCAUX_IO,

1.8 +/-1% (AC 2%), 1.8 +/-1% (AC 2%),
IRPS5401 Ch C VCC_PSDDR_PLL, VCCO_PSADC, 1.8 Integrated 2A VCC_PSDDR_PLL, VCCO_PSADC, 1.8 Integrated 2A
5V/15V 1/3 Imax step 1/3 Imax step
U2 VCC_PSAUX, VCCIO (0.5A) VCC_PSAUX, VCCIO (0.5A)

Ch D system voltage 2.5V 2.5 5% Integrated 1A system voltage 2.5V 2.5 5% Integrated 1A

LDO out User I/O: 1.5V 1.5V 0.5A User I/O: 1.5V 1.5V 0.5A
LDO in 2.5V / Ch D 2.5V / Ch D

Use Case 2: Always On, Power Efficiency, Zu04 to Zu07 with Video Codec
Zu04_05EV With SERDES, Video codec Zu07EV With SERDES, Video Codec
Rocky# Vin Channel Rails Vout Pwr Specs Power Stage Iout (A) Rails Vout Pwr Specs Power Stage Iout (A)
0.72V +/-1% (AC 2%), 0.72V +/-1% (AC 2%),
Ch A VCCINT 0.72V TDA2124x 9A VCCINT 0.72V TDA21240 15A
1/3 Imax step 1/3 Imax step
Ch B System Voltage 3.3V 3.3V 5% Integrated 2A System Voltage 3.3V 3.3V 5% Integrated 2A

Ch C Integrated Integrated
VCC_PSINTFP/ VCC_PSINTFPDDR,
VCC_PSINTFP/ VCC_PSINTFPDDR, 0.85/0.9 +/-1% (AC 2%), 0.85/0.9 +/-1% (AC 2%),
IRPS5401 0.85V 7A VCCINT_IO / VCCBRAM, 0.85V 7A
5V/15V VCCINT_IO / VCCBRAM, VCC_PSINTLP 1/3 Imax step 1/3 Imax step
U1 VCC_PSINTLP
Ch D Integrated Integrated

LDO out VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A

LDO in 3.3V / Ch B, PS I/O Supply: VCCO_PSIO (0:3) use LDO or IR3883 (<200mA) 3.3V / Ch B, PS I/O Supply: VCCO_PSIO (0:3) use LDO or IR3883 (<200mA)
0.9 +/-1% (AC 2%), 0.9 +/-1% (AC 2%),
VMGATAVCC, VMGATAVCC,
Ch A 0.9V <10mVpp ripple Integrated 2A 0.9V <10mVpp ripple Integrated 2A
VMGTYAVCC VMGTYAVCC
1/2 Imax step 1/2 Imax step
Ch B VCCO_PSDDR4_504 1.2V 1.2V 1% DC; 3%AC Integrated 1.5A VCCO_PSDDR4_504 1.2V 1.2V 1% DC; 3%AC Integrated 1.5A

VCCAUX, VCCADC, VCCAUX_IO, VCCAUX, VCCADC, VCCAUX_IO,

1.8 +/-1% (AC 2%), 1.8 +/-1% (AC 2%),
IRPS5401 Ch C VCC_PSDDR_PLL, VCCO_PSADC, 1.8V Integrated 2A VCC_PSDDR_PLL, VCCO_PSADC, 1.8V Integrated 2A
5V/15V 1/3 Imax step 1/3 Imax step
U2 VCC_PSAUX, VCCIO (0.5A) VCC_PSAUX, VCCIO (0.5A)

1.2 +/-1% (AC 2%), 1.2 +/-1% (AC 2%),

VMGTAVTT, VMGTYAVTT, VMGTAVTT, VMGTYAVTT,
Ch D 1.2V <10mVpp ripple Integrated 2A 1.2V <10mVpp ripple Integrated 2A
VCC_PSPLL, VCC_VCU_PLL VCC_PSPLL, VCC_VCU_PLL
1/2 Imax step 1/2 Imax step
LDO out VPS_MGTRAVCC 0.85V 0.5A VPS_MGTRAVCC 0.85V 0.5A
LDO in use 3.3V input; use LDO for SERDES 1.8V (100mA) - VPS_MGTRAVTT, VMGTAVCCAUX VMGTYAVCCAUX use 3.3V input; use LDO for SERDES 1.8V (100mA) - VPS_MGTRAVTT, VMGTAVCCAUX VMGTYAVCCAUX
 Solution Brief: Power for FPGAs 7

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DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Power Solution - High Level - Zynq UltraScale+ - Zu02 to Zu09 - CG / EG Series

Power Always On - Power Efficiency - Separate Vcore voltage, 0.72V & 0.85V

Zu04/05/06/07/09
CG - EG Series
No SERDES
Always On - Power Efficiency
ZYNQ UltraScale+ IRPS5401
Always On - Power Efficiency Ch A TDA21240/2 1a Core Voltage, 0.72V
Separate Core Voltage @ 0.72V Ch B 2 DDR (VCCO_PSDDR4)
Rail Consolidation Ch C 1b Core Voltage, 0.85V
Ch D 4 Auxiliary supply
LDO 5 PS PLL supply
ZYNQ US+ MPSoC
VCCINT 0.72/0.85/0.9V IR3883 System Voltage 3.3V
1a 1.1-3.3V VCCO (HDIO)
VCCAUX 1.8V 1-1.8V VCCO (HPIO) IR3883 3 PS I/O supply
4 VCCO_PSIO (0:3) / 500mA - 1.5A
VCCAUX_IO 1.8V
PL 0.9V VMGATAVCC 7 TDA21240 (<25A-35A) - Zu07, Zu09
VCCADC 1.8V Domain 1.8V VMGTAVCCAUX
6 TDA21242 (<16A) - Zu02, Zu03, Zu04, Zu05
*VCCINT_VCU 0.85/0.9V 1.2V VMGTAVTT
5
VCCBRAM 0.85/0.9V 0.9V VMGTYAVCC
VCCINT_IO 0.85/0.9V 1.8V VMGTYAVCCAUX
Zu02/03/04/05/06/07/09
1.2V VMGTYAVTT CG - EG Series
With SERDES
PS 1.2V VCC_PSPLL Always On - Power Efficiency
Low Power Domain VCCO_PSIO (0:3)
VCC_PSINTLP 0.85/0.9V IRPS5401
1.8- 3.3V 3
VCC_PSAUX 1.8V Ch A TDA21240/2 1a Core Voltage, 0.72V
VCCO_PSADC 1.8V Ch B 2 DDR (VCCO_PSDDR4)

VCC_PSINTFP 0.85/0.9V 1.1 - 1.5V VCCODDR

Ch C 1b Core Voltage, 0.85V
1b 2
VCC_PSINTFPDDR 0.85/0.9V 0.85/0.9V VPS_MGTRAVCC
Ch D 4 Auxiliary supply
8
VCC_PSDDR_PLL 1.8V 1.8V VPS_VMGTAVTT
LDO 5 PS PLL supply
Full Power Domain
IR3883 3 PS I/O supply
VCCO_PSIO (0:3) / 500mA - 1.5A
Recommend Consolidation IR3883
Suggested User Consolidation IRPS5401
Ch A System Voltage 3.3V
*EV Series Only use Video Codec Ch B 6 SERDES 1.8V
Ch C 7 SERDES 0.9V
Ch D 5 SERDES / PLL 1.2V
LDO 8 SERDES 0.85V

TDA21240 (<25A-35A) - Zu07, Zu09

TDA21242 (<16A) - Zu02, Zu03, Zu04, Zu05
 Solution Brief: Power for FPGAs 8

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DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Power Solution - High Level - Zynq UltraScale+ - Zu02 to Zu09 - CG / EG Series

Power Always On - Power Efficiency - Separate Vcore voltage, 0.72V & 0.85V

Use Case 2: Always On, Power Efficiency, Zu04 to Zu09

Zu04_05 CG EG No SERDES Zu07 (15A)_Zu09 (20A) CG EG No SERDES
Rocky# Vin Channel Rails Vout Pwr Specs Power Stage Iout (A) Rails Vout Pwr Specs Power Stage Iout (A)
0.72V +/-1% (AC 2%), 0.72V +/-1% (AC 2%),
Ch A VCCINT 0.72V TDA2124x 9A VCCINT 0.72V TDA2124x 20A
1/3 Imax step 1/3 Imax step
Ch B VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.5A VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.5A

VCC_PSINTFP/ VCC_PSINTFPDDR,
0.85/0.9 +/-1% (AC 2%), VCC_PSINTFP/ VCC_PSINTFPDDR, 0.85/0.9 +/-1% (AC 2%),
Ch C VCCINT_IO / VCCBRAM, 0.85V Integrated 4A 0.85V Integrated 4A
1/3 Imax step VCCINT_IO / VCCBRAM, VCC_PSINTLP 1/3 Imax step
VCC_PSINTLP

IRPS5401
5V/15V
U1 VCCAUX, VCCADC, VCCAUX_IO, VCCAUX, VCCADC, VCCAUX_IO,
1.8 +/-1% (AC 2%),
Ch D VCC_PSDDR_PLL, VCCO_PSADC, 1.8 Integrated 2A VCC_PSDDR_PLL, VCCO_PSADC, 1.8 Integrated 2A
1/3 Imax step
VCC_PSAUX, VCCIO (0.5A) VCC_PSAUX, VCCIO (0.5A)

LDO out VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A

LDO in 3.3V system voltage / IR3883 also additional 1.8V/IR3883 (for VCCO_PSIO) 3.3V system voltage / IR3883 also additional 1.8V/IR3883 (for VCCO_PSIO)

Use Case 2: Always On, Power Efficiency, Zu04 to Zu09

Zu04_05 CG EG with SERDES Zu06_07 (15A)_Zu09 (20A) CG EG with SERDES
Rocky# Vin Channel Rails Vout Pwr Specs Power Stage Iout (A) Rails Vout Pwr Specs Power Stage Iout (A)
0.72V +/-1% (AC 2%), 0.72V +/-1% (AC 2%),
Ch A VCCINT 0.72V TDA2124x 9A VCCINT 0.72V TDA21240 20A
1/3 Imax step 1/3 Imax step
Ch B VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.2A VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.2A

VCC_PSINTFP/ VCC_PSINTFPDDR,
VCC_PSINTFP/ VCC_PSINTFPDDR, 0.85/0.9 +/-1% (AC 2%), 0.85/0.9 +/-1% (AC 2%),
Ch C 0.85V Integrated 4A VCCINT_IO / VCCBRAM, 0.85V Integrated 4A
VCCINT_IO / VCCBRAM, VCC_PSINTLP 1/3 Imax step 1/3 Imax step
VCC_PSINTLP

IRPS5401
5V/15V
U1 VCCAUX, VCCADC, VCCAUX_IO, VCCAUX, VCCADC, VCCAUX_IO,
1.8 +/-1% (AC 2%),
Ch D VCC_PSDDR_PLL, VCCO_PSADC, 1.8 Integrated 2A VCC_PSDDR_PLL, VCCO_PSADC, Integrated 2A
1/3 Imax step
VCC_PSAUX, VCCIO (0.5A) VCC_PSAUX, VCCIO (0.5A)

LDO out VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A

LDO in 1.8V/IR3883 (for VCCO_PSIO) 1.8V/IR3883 (for VCCO_PSIO)

Ch A system voltage 3.3V 3.3V 5% Integrated 1A system voltage 3.3V 3.3V 5% Integrated 1A
1.8+/-1% (AC 2%), 1.8+/-1% (AC 2%),
VPS_MGTRAVTT, VMGTAVCCAUX VPS_MGTRAVTT, VMGTAVCCAUX
Ch B 1.8V <10mVpp ripple Integrated 1A 1.8V <10mVpp ripple Integrated 1A
VMGTYAVCCAUX VMGTYAVCCAUX
1/2 Imax step 1/2 Imax step
0.9 +/-1% (AC 2%), 0.9 +/-1% (AC 2%),
VMGATAVCC, VMGATAVCC,
Ch C 0.9V <10mVpp ripple Integrated 2A 0.9V <10mVpp ripple Integrated 2A
VMGTYAVCC VMGTYAVCC
IRPS5401 1/2 Imax step 1/2 Imax step
5V/15V
U2 1.2 +/-1% (AC 2%), 1.2 +/-1% (AC 2%),
VMGTAVTT, VMGTYAVTT, VMGTAVTT, VMGTYAVTT,
Ch D 1.2V <10mVpp ripple Integrated 2A 1.2V <10mVpp ripple Integrated 2A
VCC_VCU_PLL VCC_VCU_PLL
1/2 Imax step 1/2 Imax step
0.85 +/-1% (AC 2%), 0.85 +/-1% (AC 2%),
LDO out VPS_MGTRAVCC 0.85V <10mVpp ripple Integrated 0.5A VPS_MGTRAVCC 0.85V <10mVpp ripple Integrated 0.5A
1/2 Imax step 1/2 Imax step

LDO in 3.3V / Ch A 3.3V / Ch A

 Solution Brief: Power for FPGAs 9

www.infineon.com/xilinx
DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Power Solution - High Level - Zynq UltraScale+ - Zu04, Zu05, Zu07 EV Series - Video Codec
Power Always On - Power Efficiency - Separate Vcore voltage, 0.72V & 0.85V

Zu04EV / Zu05EV / Zu07EV

EV Series
No SERDES
Always On - Power Efficiency
IRPS5401
ZYNQ UltraScale+ TDA21242 1a Core Voltage, 0.72V
Ch A
Always On - Power Efficiency
Ch B System Voltage 3.3V
Separate Core Voltage @ 0.72V
Ch C 1b Core Voltage, 0.85V
Rail Consolidation
Ch D
LDO 5 PS PLL supply

ZYNQ US+ MPSoC

IRPS5401
VCCINT 0.72/0.85/0.9V 1.1-3.3V VCCO (HDIO) 3 PS I/O supply
1a Ch A
9
VCCAUX 1.8V 1-1.8V VCCO (HPIO) Ch B 2 DDR (VCCO_PSDDR4)
4
VCCAUX_IO 1.8V Ch C 4 Auxiliary supply
PL 0.9V VMGATAVCC 7
VCCADC 1.8V Domain 1.8V VMGTAVCCAUX Ch D System Voltage 2.5V
6
LDO 9 User I/O: 1.5V, 500mA
*VCCINT_VCU 0.85/0.9V 1.2V VMGTAVTT
5
VCCBRAM 0.85/0.9V 0.9V VMGTYAVCC
VCCINT_IO 0.85/0.9V 1.8V VMGTYAVCCAUX
1.2V VMGTYAVTT Zu04EV / Zu05EV / Zu07EV
EV Series
PS 1.2V VCC_PSPLL With SERDES
Low Power Domain VCCO_PSIO (0:3)
VCC_PSINTLP 0.85/0.9V
1.8- 3.3V 3 Always On - Power Efficiency
VCC_PSAUX 1.8V
IRPS5401
VCCO_PSADC 1.8V TDA21242 1a Core Voltage, 0.72V
Ch A
VCC_PSINTFP 0.85/0.9V 1.1 - 1.5V VCCODDR Ch B System Voltage 3.3V
1b 2
VCC_PSINTFPDDR 0.85/0.9V 0.85/0.9V VPS_MGTRAVCC Ch C 1b Core Voltage, 0.85V
8
VCC_PSDDR_PLL 1.8V 1.8V VPS_VMGTAVTT Ch D
Full Power Domain LDO 5 PS PLL supply

Recommend Consolidation
IR3883 3 PS I/O supply
Suggested User Consolidation

*EV Series Only use Video Codec IRPS5401

Ch A 7 SERDES 0.9V
Ch B 2 DDR (VCCO_PSDDR4)
Ch C 4 Auxiliary supply
Ch D 5 SERDES / PLL 1.2V
LDO 8 SERDES 0.85V

LDO 6 SERDES 1.8V

 Solution Brief: Power for FPGAs 10

www.infineon.com/xilinx
DC-DC Power Solutions for FPGAs
Infineon Power for Xilinx Zynq UltraScale+ MPSoC

Power Solution - High Level - Zynq UltraScale+ - Zu04, Zu05, Zu07 EV Series - Video Codec
Power Always On - Power Efficiency - Separate Vcore voltage, 0.72V & 0.85V

Use Case 2: Always On, Power Efficiency, Zu04 to Zu07 with Video Codec
Zu04_05EV No SERDES, Video codec Zu07EV No SERDES, Video Codec
Rocky# Vin Channel Rail Vout Pwr Specs Power Stage Iout (A) Rails Vout Pwr Specs Power Stage Iout (A)
0.72V +/-1% (AC 2%), 0.72V +/-1% (AC 2%),
Ch A VCCINT 0.72V TDA2124x 9A VCCINT 0.72V TDA2124x 15A
1/3 Imax step 1/3 Imax step
Ch B system voltage 3.3V 3.3V 5% Integrated 1.1A (2A) system voltage 3.3V 3.3V 5% Integrated 1.1A (2A)

Ch C Integrated Integrated
VCC_PSINTFP/ VCC_PSINTFPDDR,
0.85/0.9 +/-1% (AC 2%), VCC_PSINTFP/ VCC_PSINTFPDDR, 0.85/0.9 +/-1% (AC 2%),
IRPS5401 VCCINT_IO / VCCBRAM, 0.85V 7A 0.85V 7A
5V/15V 1/3 Imax step VCCINT_IO / VCCBRAM, VCC_PSINTLP 1/3 Imax step
U1 VCC_PSINTLP
Ch D Integrated Integrated

LDO out VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A

LDO in 3.3V / Ch B 3.3V / Ch B

Ch A VCCO_PSIO (0:3) 1.8 1.2V 1% DC; 3%AC Integrated 1A VCCO_PSIO (0:3) 1.8 1.2V 1% DC; 3%AC Integrated 1A

Ch B VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.5A VCCO_PSDDR4_504 1.2 1.2V 1% DC; 3%AC Integrated 1.5A

VCCAUX, VCCADC, VCCAUX_IO, VCCAUX, VCCADC, VCCAUX_IO,

1.8 +/-1% (AC 2%), 1.8 +/-1% (AC 2%),
IRPS5401 Ch C VCC_PSDDR_PLL, VCCO_PSADC, 1.8 Integrated 2A VCC_PSDDR_PLL, VCCO_PSADC, 1.8 Integrated 2A
5V/15V 1/3 Imax step 1/3 Imax step
U2 VCC_PSAUX, VCCIO (0.5A) VCC_PSAUX, VCCIO (0.5A)

Ch D system voltage 2.5V 2.5 5% Integrated 1A system voltage 2.5V 2.5 5% Integrated 1A

LDO out User I/O: 1.5V 1.5V 0.5A User I/O: 1.5V 1.5V 0.5A
LDO in 2.5V / Ch D 2.5V / Ch D

Use Case 2: Always On, Power Efficiency, Zu04 to Zu07 with Video Codec
Zu04_05EV With SERDES, Video codec Zu07EV With SERDES, Video Codec
Rocky# Vin Channel Rails Vout Pwr Specs Power Stage Iout (A) Rails Vout Pwr Specs Power Stage Iout (A)
0.72V +/-1% (AC 2%), 0.72V +/-1% (AC 2%),
Ch A VCCINT 0.72V TDA2124x 9A VCCINT 0.72V TDA21240 15A
1/3 Imax step 1/3 Imax step
Ch B System Voltage 3.3V 3.3V 5% Integrated 2A System Voltage 3.3V 3.3V 5% Integrated 2A

Ch C Integrated Integrated
VCC_PSINTFP/ VCC_PSINTFPDDR,
VCC_PSINTFP/ VCC_PSINTFPDDR, 0.85/0.9 +/-1% (AC 2%), 0.85/0.9 +/-1% (AC 2%),
IRPS5401 0.85V 7A VCCINT_IO / VCCBRAM, 0.85V 7A
5V/15V VCCINT_IO / VCCBRAM, VCC_PSINTLP 1/3 Imax step 1/3 Imax step
U1 VCC_PSINTLP
Ch D Integrated Integrated

LDO out VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A VCC_PSPLL 1.2V 1.2V 1% DC; 3%AC Integrated 0.5A

LDO in 3.3V / Ch B, PS I/O Supply: VCCO_PSIO (0:3) use LDO or IR3883 (<200mA) 3.3V / Ch B, PS I/O Supply: VCCO_PSIO (0:3) use LDO or IR3883 (<200mA)
0.9 +/-1% (AC 2%), 0.9 +/-1% (AC 2%),
VMGATAVCC, VMGATAVCC,
Ch A 0.9V <10mVpp ripple Integrated 2A 0.9V <10mVpp ripple Integrated 2A
VMGTYAVCC VMGTYAVCC
1/2 Imax step 1/2 Imax step
Ch B VCCO_PSDDR4_504 1.2V 1.2V 1% DC; 3%AC Integrated 1.5A VCCO_PSDDR4_504 1.2V 1.2V 1% DC; 3%AC Integrated 1.5A

VCCAUX, VCCADC, VCCAUX_IO, VCCAUX, VCCADC, VCCAUX_IO,

1.8 +/-1% (AC 2%), 1.8 +/-1% (AC 2%),
IRPS5401 Ch C VCC_PSDDR_PLL, VCCO_PSADC, 1.8V Integrated 2A VCC_PSDDR_PLL, VCCO_PSADC, 1.8V Integrated 2A
5V/15V 1/3 Imax step 1/3 Imax step
U2 VCC_PSAUX, VCCIO (0.5A) VCC_PSAUX, VCCIO (0.5A)

1.2 +/-1% (AC 2%), 1.2 +/-1% (AC 2%),

VMGTAVTT, VMGTYAVTT, VMGTAVTT, VMGTYAVTT,
Ch D 1.2V <10mVpp ripple Integrated 2A 1.2V <10mVpp ripple Integrated 2A
VCC_PSPLL, VCC_VCU_PLL VCC_PSPLL, VCC_VCU_PLL
1/2 Imax step 1/2 Imax step
LDO out VPS_MGTRAVCC 0.85V 0.5A VPS_MGTRAVCC 0.85V 0.5A
LDO in use 3.3V input; use LDO for SERDES 1.8V (100mA) - VPS_MGTRAVTT, VMGTAVCCAUX VMGTYAVCCAUX use 3.3V input; use LDO for SERDES 1.8V (100mA) - VPS_MGTRAVTT, VMGTAVCCAUX VMGTYAVCCAUX
 Solution Brief: Power for FPGAs 11

DC-DC Power Solutions for FPGAs Go to IRPS5401

IRPS5401 Multi-output PMIC

Vin IRPS5401 PMBus Command Set

PMBus 1.2 Compliant - Advanced Digital Power
Multi-CORE PROCESSOR
DSP /ASIC / FPGA / SoC
Vin <A:D>

IRPS5401
4A VD
Power Sequencing φ_D*
Switcher D

& Ramp CORE VOLTAGE

Good PWM
Control
PGood <A:D> FB µP µP
EN <A:D> VC
4A
Switcher A Switcher B Switcher C

φ_C*
EN FB
Timing & MEMORY
Phase
φ_B 2A VB
FB
Fault
Management
φ_A
2A VA PLATFORM
FB
Telemetry VOLTAGES
RS+
Differential
RS-
Configuration sense
Memory
LDO 500mA VO_LDO PERIPHERAL
VOLTAGES
SAlert
SDA
SCL

PGnd

* Switchers C & D can be

combined for 8A

Example: Designing for Power Sequencing via PMBus

using PowIRCenter GUI

FEATURES
• 5 integrated outputs
4A, 4A, 2A and 2A Switching Regulators
500mA Source/Sink Linear regulator
• Single rail operation 5V to 12
• Output Range 0.25V to 5.5V for outputs A-D 3.6V for LDO
• Digital Compensation: No externals required
• Differential voltage sensing on Switcher A for accuracy
• I2C / PMBus 1.2 Full Digital Power Command Set DESIGN TOOLS
• I2C level shift allows i/f to any I/O voltage from the SoC
• Integrated Sequencing, Telemetry, Fault Management, • PowIRCenter GUI DESIGN TOOL
Inventory Management • IRPS5401 EVALUATION BOARDS
• Switching Frequency from 200 kHz to 2MHz Eval Board - DB296 Eval Board - DB295
• Regulators operated at different phases IRPS5401 only IRPS5401 + external
• Flexible I2C and PMBus address schemes with base and 4 regulators PowIRstage
offset addressing allowing for 15 offsets per base. 1 LDO 4 regulators
• Optional: Allows use of an external PowIRstage to 50A 1 LDO
• Optional: Switchers C & D can be combined for 8A
• Rated for -40°C to +125°C TJ operation
• Pb-Free, RoHS6, 7x7mm, 56-pin, 0.4mm pitch QFN

APPLICATIONS
• Server / Microserver
• Storage
• Network Infrastructure
• Video / Image Processing
• FPGA accelerators
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 Solution Brief: Power for FPGAs 12

DC-DC Power Solutions for FPGAs Go to IRPS5401

IRPS5401 Multi-output PMIC

Scalable Design Options
20W to +60W
TDA21242 - 20A
TDA21240 - 40A
IR3555 - 50A
IRPS5401 IR3550 - 60A
Sequencing φ_A
PowIRStage VA

Switcher A
& Ramp PWM
Control FB
PGood <A:D> RS+
EN <A:D> RS-

4A VC
Switcher B Switcher D Switcher C
Timing &
Phase φ_C*

Need more power... Fault

Management 4A VD
φ_D*

Telemetry
2A VB
φ_B
Configuration
Memory

IRPS5401
Sequencing 2A VA
Switcher A

φ_A
& Ramp
Control
PGood <A:D>
VB
Switcher B

EN <A:D>
φ_B
2A
Timing &
Phase
Need more power... 8A VC+D
Switcher C

Fault
Management φ_C*

Telemetry
Switcher D

φ_D*
Configuration
Memory Combining Output Options
LDOout
LDO 4A + 4A = 8A

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