2015 International Conference on Information Processing (ICIP)
Vishwakarma Institute of Technology. Dec 16-19, 2015
Realization of Cordic Algorithm in DDS
Novel Approch towards Digital Modulators in MATLAB and VHDL
Miss. Prajakta J. Katkar
Department of Electronics and Telecommunication
JSPM’s BSIOTR COE, Wagholi.
Pune, India
Prajaktakatkar1@gmail.com
Abstract— CORDIC (CO-ordinate Rotation Digital
Computer) algorithm is the most important solution for realizing
the different digital modulation schemes. Modulation is the method
of varying the carrier signal according to the amplitude of the
modulating signal. The CORDIC algorithm is used in the rotation
mode. This mode is used for converting polar coordinates to
rectangular. This paper shows that how to use CORDIC algorithm
in implementing the different digital modulation techniques in
MATLAB realization and VHDL implementation. In that MATLAB
realization of ASK, FSK and PSK with VHDL realization of BPSK,
QPSK and-QAM modulation. Here we use the software defined
radio concept i.e. we can use a single kit for different modulation
techniques by changing only software part without replacing the
hardware. The main concept used here is the direct digital synthesis
(DDS) is the method of generating waveforms in digital domain.
Keywords—CORDIC Algorithm, DDS, Communication
Systems, PSK, ASK, FSK, QPSK, BPSK,-QAM.
I. INTRODUCTION
The Coordinate Rotation Digital Computer
(CORDIC) was introduced in 1959 by Volder. The rotation of
a two-dimensional vector using only add and shift operations
are computes iteratively . CORDIC has been used for
hardware implementations. CORDIC-based architectures are a
very good alternative to conventional add and multiply
hardware. CORDIC algorithm is used for implementing
different digital modulation schemes as phase shift keying,
amplitude shift keying, 4-qam shift keying, frequency shift
keying, binary phase shift keying, 16-qam shift keying,
quadrature shift keying etc. These all modulation schemes are
realized in MATLAB as well as in VHDL. Here in this paper
amplitude shift keying, phase shift keying, frequency shift
keying use MATLAB realization and , binary phase shift
keying, 4-qam shift keying quadrature shift keying use the
VHDL realization. By using this algorithm we can able to
minimize the hardware requirement i.e. we can change the
functionality of a single hardware with varying the only
software part.
978-1-4673-7758-4/15/$31.00 ©2015 IEEE
Dr.Yogesh S. Angal
Department of Electronics and Telecommunication
JSPM’s BSIOTR COE, Wagholi
Pune, India
yogeshangal@yahoo.co.in
In this paper Section II, covers the basic concepts of CORDIC
Algorithm, Section III presents the Communication system
using CORDIC Algorithm. In Section IV the results are
discussed and conclusion is given in Section V.
Acknowledgment is given in section VI.
II. BASIC CONCEPTS OF CORDIC ALGORITHM
Easy way to understand the use the CORDIC
algorithm in the implementation of digital intermediate
frequency (IF) communications systems, CORDIC is
presented with three inputs X0, Y0, and Z0 and three outputs
XN, YN, and ZN .
To implement different digital communication a
generic scheme which shows how to use rotational mode
CORDIC. The scheme is composed of an RM CORDIC where
signals I and Q are connected into X0 and Y0inputs, and the
phase term q connected into Z0 input is ș= (™(Fc + Fm) + ࢥm) *
ɉ
The process of generating sine waveforms directly in
the digital domain is direct digital synthesis. It consists of a
phase accumulator and a phase-to-waveform converter. By an
RM-CORDIC the phase-to-waveform converter could be
realized. The sine and cosine waveforms are obtained
respectively by the CORDIC outputs YN and XN .
Instead of perfect rotation CORDIC computes a
pseudo-rotation of a two-dimensional vector. i.e. The original
vector is rotated by an angle q, and its magnitude is increased
by a constant factor K.
III. COMMUNICATION SYSTEM USING CORDIC
ALGORITHM
A. DIRECT DIGITAL SYNTHESIS
DDS is a method to generate waveforms directly in
the digital domain. The target waveforms in communication
systems are the sine and cosine ones. A DDS is the
combination of a phase accumulator and a phase-to amplitude
converter, as shown in Fig. 2. In a conventional DDS based on
lookup tables (LUTs) the phase accumulator is an integer N-
bit accumulator, whose output directly addresses the LUT
where the amplitude values of sine or cosine waves are stored.
The maximum value of the accumulator (2N–1) represents the
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phase 2 of the sine or cosine wave. When it is incremented
by a fixed value, the accumulator generates a ramp signal.
The CORDIC algorithm in RM can behave as a
phase-to-amplitude converter that directly generates sine and
cosine waveforms. With respect to LUT based methods the
main advantage of using CORDIC-based DDS is that it can
achieve both high precision with lower hardware cost AND
high phase resolution. The difference between CORDIC-
based DDS and LUT methods is that the phase accumulator
generates an integer value that addresses an LUT in the LUT-
based method, while it generates an angle in CORDIC-based
DDS.
To generate sine and cosine waveforms of a digital
frequency fc with the scheme based on CORDIC of Fig. 3, the
parameters fm, ࢥm, and Q must be zero and I = 1/K. The
oscillation frequency is controlled by giving a fixed value to
fc. In such a case CORDIC generates directly the cosine and
sine waveforms (si (n) = cos (fc. ʌ n) and sq (n) = sin (fc. ʌ .n))
through XN and YN outputs, respectively. The maximum
synthesized frequency is obtained by taking the value fc = 1
(which is equivalent to analog frequency of fs/2); and the
minimum frequency is achieved with fc = 2–(N–1), where N is
the word-length of the accumulator [6-7].
frequency fc, through the XN output. An FSK signal can be
generated with the scheme of Fig. 3 if the frequency
modulator signals is fm = m(n), the carrier frequency is a fixed
value fc, the terms Øm, and Q are zero and the X0 input is I =
1/K. The FSK signal (s (n) = cos (fc × ʌ × n + (™m (n)) × ʌ)) is
also obtained by the output XN. In an ASK, PSK, or FSK
modulator, it is required to up-sample the base-band
modulator signal m(n) up to the sampling rate (fs) of the
CORDIC processor and DAC. As this signal usually is a
narrow band one, a Cascade-Integrator- Comb filter (CIC) is a
very low hardware cost solution to perform this task [9].
IV. RESULTS AND DISCUSION
A. SIMULATION IN MATLAB
The results into waveform are obtained in matlab
simulation. The modulating signal is 1001010101

Fig. 3 ASK modulated output

Fig. 1 Generic scheme to use CORDIC in Rotation Mode. Select the mode ASK =1we get the ASK output

Phase Phase to
Accumulator Amplitude

Fig. 2 Block Diagram of DDS

B. FREQUENCY, PHASE AND AMPLITUDE

MODULATORS
The CORDIC scheme of Fig. 3 can be used to
directly generate in the digital domain at IF the binary
modulations ASK, PSK, and FSK.
The CORDIC scheme of Fig. 3 can be used to
directly generate in the digital domain at IF the binary
modulations ASK, PSK, and FSK [8]. Considering m (n) as
Fig. 4 FSK modulated output
the modulator signal, ASK can be implemented by choosing in
Fig. 3 carrier IF fc, using the input Xo as modulator signal I =
Select the mode FSK =1we get the FSK output.
m (n)/K, and leaving to zero fm, Øm, and Q. In such a case the
ASK signal (s (n) = m (n) × cos (fc × ʌ × n)) is generated
through XN CORDIC output. If PM is desired, the terms fm and
Q of Fig. 3 are zeroed, the input Xo is fixed to I = 1/K, and the
phase modulator signal is Øm = m (n). Then the PM signal (s
(n) = cos (fc × ʌ × n + m (n) × ʌ)) is obtained with a carrier

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 Fig. 5 PSK modulated output

Select the mode PSK =1we get the PSK output

B. SIMULATION IN VHDL
The Digital modulation schemes such as frequency
shift keying (FSK), amplitude-shift keying (ASK), and phase-
shift keying (PSK), Quadrature amplitude modulation( QAM),
Quadrature phase shift keying(QPSK), binary phase-shift
keying (PSK), was designed separately using Xilinx ISE 13.2
and its simulated results are shown below.
Following figure shows the VHDL simulation of
ASK modulated signal. System is multimode system because
depending on different 3 bit modes selected any one of the
seven modulation technique is selects.
Mode input is 4 bit input, for binary 1 “0001” and for
binary 0 “0000” is selected. Input is 16 bit. We can select any
input from 216=256 combinations. According to that we got
the 32 bit output. Phase accumulator adds the inputs at every
clock cycle. Phase output is delayed version of phase
accumulator.
Fig. 6 ASK modulated output in VHDL simulation
For FSK, the input and outputs are given bellow and are
clearly shown in figure 8.
Mode=001
Mode input= 0000 to 0001
Input= 0000000000001111
Output= whenever binary 0000 to 0001 transition occurs the
phase output gets changed.
Phase accumulator output= for input 15 its adds 15 in each
clock cycle i.e. 15, 30, 45, 60 etc.
This output given as an input to the Phase to amplitude
converter as Phase Output with delay of one clock cycle.

For ASK, the input and outputs are given bellow

If we select,
Mode=000
Mode input= 0000 to 0001
Input= 0000000000001111 then obtained output is given as
follows
For binary 1 and 0 for binary 0.
Output= 16384
For input 15 its adds 15 in each clock cycle
Phase accumulator output= 15, 30, 45, 60 etc. Fig. 7 FSK modulated output in VHDL simulation

This output given as an input to the Phase to For BPSK, the input and outputs are given bellow and are
amplitude converter as Phase Output with delay of one clock clearly shown in figure 8.
cycle. Output of phase to amplitude converter is multiplied Mode=011
with amplitude modulation control and final output is Mode input= 0000 to 0001
obtained. Input= 0000000000001111
Output= whenever binary 0000 to 0001 transition occurs the
phase output gets changed.
When 0001 comes then 180º phase shift occurs.
Phase Output= (180º*216)/360º=32738. This is added with 30,
32738+30=32768 which is as shown in following figure.

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When output changes from 0001 to 0000 phase output is same
as output of phase accumulator with delay of one clock cycle.
For input 15 its adds 15 in each clock cycle i.e. 15, 30, 45, 60
etc. This output given as an input to the Phase to amplitude
converter as Phase Output with delay of one clock cycle.
For 4-QAM, the input and outputs are given below and are
clearly shown in figure 8.
Mode=101
Mode input= 0000 to 0001
Input= 0000000000001111
Whenever output changes from 0000 to 0001 there is 45°
phase shift occurs.
Phase Output= (45º*216)/360º=8192. This is added with 15,
8192+15=8207 which is as shown in following figure.
Whenever output changes from 0001 to 0000 there is 135°
phase shift occurs.
Phase Output= (135º*216)/360º=24576. This is added with 30,
24576+30=24606 which is as shown in following figure. Then
24606 are added with 15, 24606+15=24621 and so on up to
Mode input is 0001.
Phase accumulator output= for input 15 its adds 15 in each
clock cycle i.e. 15, 30, 45, 60 etc.
This output given as an input to the Phase to amplitude
converter as Phase Output with delay of one clock cycle.

Fig. 8 BPSK modulated output in VHDL simulation

For QPSK, the input and outputs are given below and are
clearly shown in figure 8.
Mode=100
Mode input= 0000 to 0001
Input= 0000000000001111
Output= whenever binary 0000 to 0001 transition occurs the
phase output gets changed.
When 0001 comes then 45º phase shift occurs.
Phase Output= (45º*216)/360º=8192. This is added with 30,
8192+30=8222 which is as shown in following figure. Then
8222 is added with 15, 8222+15=8237 and so on up to Mode
input is 0001. Whenever it changes from 0001 to 0000 phase
output is same as output of phase accumulator with delay of
one clock cycle. Again when mode input changes from 0000 Fig. 9 4-QAM modulated output in VHDL simulation
to 0001, 45° phase shift occurs, due to that 8192 is added with
previous phase accumulator output. In following figure 8192 The design is interfaced with onboard LED display. The
is added with 150 to get 8342 as an output. This output given code was then successfully implemented on Spartan3E board
as an input to the Phase to amplitude converter as Phase after successful completion of translate, map, place and
Output with delay of one clock cycle. route processes. And the outputs can be viewed on LED
display.

Parameter ASK FSK BPSK QPSK 4-

s QAM
Mode 000 001 011 100 101
Amplitude 16384 NA NA NA 11585
Change
Frequency NA Doubles NA NA NA
Change
Phase NA NA 180 45 45
Change
Phase NA NA 32738 8192 24576
Output

Fig. 10 QPSK modulated output in VHDL simulation Table 1. Tabulated Form of Simulation waveforms

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 [8] J. Vankka, "Digital Modulator for Continuous Modulations with Slow
Frequency Hopping," IEEE Transactions on Vehicular Technology, vol.
46, pp. 933-940, Nov. 1997.
V. CONCLUSION [9] M. Kosunen, J. Vankka, M. Waltari, L. Sumanen, K. Koli, and K.
Halonen, "A CMOS Quadrature Baseband Frequency
Synthesizer/Modulator", Analog Integrated Circuits and Signal
Processing, Vol. 18, No. 1, pp. 55-67, Jan. 1999.
This paper gives the use of CORDIC algorithm for
[10] R.Andraka, “A survey of CORDIC algorithms for FPGA based
direct digital synthesis. This algorithm is a useful for computers, Proceedings of ACM/SIGDA sixth International Symposium
conversion of phase to sine amplitude. Through repeated shift- on field Programmable Gate Arrays”, 1998,pp.191-200
add operations CORDIC is implemented by a simple
hardware. This paper is highlighted on the Direct Digital
Synthesizer using CORDIC, with minimum area requirement
in FPGA to increase the speed. This paper reveals that how to
use the CORDIC algorithm to implement different
communications systems like ASK, PSK, FSK in MATLAB
and ASK, FSK, BPSK, QPSK, 4-QAM in VHDL etc digital
modulators using MATLAB and VHDL. Here by using only
variable software parameter settings the same hardware used
as different functional component.
VI. AUTHOR’S BIOGRAPHY

I.Prajakta J. Katkar
Qualification: M.E (VLSI & EMBEDDED SYSTEMS)
Address: Shivnagar,Baramati,Tal- Baramati, Dist- Pune
Mail ID: prajaktakatkar1@gmail.com

II. Yogesh S. Angal

Designation: Head of Department
Qualification: M.E (Instrumentation), D.B.M, PhD
(Instrumentation)
Experience: 19 yrs
Mail ID: hodetcbsiotr@gmail.com
Area of Interest: Speech Processing, Control Systems,
Digital Signal Processing, Industrial Automation,
Mechatronics.

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