Hybrid phase comparator applied to distance

protection
P.G. McLaren, B.Sc, M.A., Ph.D., C.Eng., M.I.E.E. and M.A. Redfern, B.Sc.

Indexing terms: Phase comparators, Power system protection, Power transmission lines, Relay protection

Abstract
The paper describes the operation of a 1 bit processor which can be used to measure phase difference, and hence
can be applied to distance protection. The processor averages over one cycle the sign coincidence between its two
input signals and gives an analogue output proportional to their phase difference. Examples are given of its
application to mho and quadrilateral impedance characteristics. Where appropriate its performance is compared
with a block-average comparator.

List of symbols comparator is faster throughout, but it is considerably faster close to

the boundary. As will be seen later, this speed of operation close to
V = voltage at the relaying point the boundary is achieved at the expense of stability with regard to
/ = current at the relaying point boundary faults. An improvement in boundary accuracy can be
ZR = replica impendance
ZL = line impedance
Zs = source impedance
ZF = ZFL<t> = impedance to fault from the relaying point
Wlf W2, W3 = relay inputs
output to
1 Introduction trip-level
detectors
The block-average phase comparator has been widely applied
in distance-protection schemes.1 The block-average principle, how-
ever, can give rise to unacceptably long operating times for fault
impedances not lying on the characteristic impedance of the com-
parator. On the other hand, its boundary accuracy is very high.
The phase comparator described in this paper retains the aver-
aging function of the block-average comparator but reduces the aver- (i) output of the one-bit comparator
aging period to one cycle of the power frequency. The amplitude of the V —<•'•>
the output signal from the device is linearly proportional to phase dif- (n)W,=V-IZR
ference between its input signals. Trip signals are derived from level trip
detectors which monitor the appropriate output level and by incor- level
porating suitable delays in the level detector circuits, the timing charac-
teristic of the comparator can be given any desired shape. The hardware (MI) output of the block-average
necessary to realise the comparator consists of readily available and well comparator.
established small-scale integrated circuits.
Results are given for online tests on a model transmission line and
the performance of a block-average comparator is included for com-
parison. An offline computer simulation is used to give a more varied 8 x 8 bit shift registers
testing facility, and results are given for the comparator used in mho-
and quadrilateral-characteristic applications.
Schmitt trigger
zero-crossing register[ //• 1 register |—
2 Basic comparator detectors
The block diagram of the comparator is shown in Fig. la.
The input signals Wy and W2 are derived from the relaying point trans- input
ducer outputs by suitable mixing circuits. The input amplifiers, which amplifiers summing-amplifier
input resistors
include accurate zero-crossing detectors, convert the input signals
into square waveforms and a polarity comparison is then performed.
The comparison waveform is then sampled at a rate determined by
the master-clock frequency and a '1' or a '0' is loaded into the shift
summing trip-level
register according to whether the sampled signal is positive or zero. amplifier detector
The register length is chosen such that it can hold the number of
samples taken in one cycle (20 ms for 50 Hz). The bit values, either
T or '0', in the register are summed using an analogue summing
amplifier, details of which are given in Fig. \c and in the Appendix
(Section 7), and the output of this amplifier is monitored by level Fig. 1
detectors. The output amplitude is proportional to the phase differ- 1 bit comparator
ence, in the steady state, between Wx and W2 and the level detectors a Block diagram
can be set to correspond to any desired phase-angle trip level. Fig. \b b Typical input and output waveforms, including block-average output for
shows how the summing-amplifier output varies when the phase angle comparison
c Circuit diagram
between Wt = V — IZR and W2 = V changes from 180° prefault to
60° postfault. The block-average output included in Fig. 16 has a
basic minimum operating time of 10 ms. Fig. 2a shows the timing achieved by using trip-time delays and thereby producing any desired
contour of the 1 bit comparator when the trip level is set for ± 90°. shape of timing characteristic.
Fig. 2b shows the corresponding contours for a ±90° block-average
comparator with a basic minimum operating time of 10 ms. The 1 bit 3 Mho characteristic
A hardware unit was built with a register length of 64
Paper 7549 P, first received 21st April and in final form 15th August 1975
locations and the clock frequency was thus set to 3200 Hz. The level
detector trip circuit was set at the level corresponding to 6 = ±90°.
Dr. MacLaren and Mr. Redfern are with the University Engineering Department,
Trumpington Street, Cambridge CB2 1P2, England Voltage and current signals were derived from a single-phase test

PROC. IEE, Vol. 122, No. 11, NOVEMBER 1975 1295

circuit having a source impedance Za of 0-25 p.u. Z_70°, and a line
impedance Z2 of 1 -0 p.u. Z.7O0. A variable fault resistance RF was
connected in series with a point-on-wave switch which controlled the
the thyristor in the point-on-wave switch close to current zero.
Fig. \b is for a fault impedance giving 6 equal to 60° and Fig. 3 is for
a fault impedance giving 0 = 90°. Both Fig. \b and Fig. 3 show that
the 1 bit comparator approaches its steady-state level faster than the
block-average comparator for fault impedances not lying on the
characteristic impedance of the mho circle. They also demonstrate
that the one-bit comparator output may temporarily overshoot its
steady state output.

3O-
time, ms

2O-

-90 -6O -3O 3O 6O 9O

0. deg
time, ms

Fig. 3
Comparator responses to a typical boundary fault condition
a Fault incidence at maximum voltage
b Fault incidence at zero voltage
Zp = 0-96 p.u. Z.56°
(i) 1 bit comparator output
(ii) V-IZR input waveform
(Hi) Block-average comparator output

The operating times for a number of fault impedances are shown

in Fig. 4.; Fig. 4a for faults at zero voltage and Fig. 46 for faults at
maximum voltage. The latter gives maximum overshoot which in
Fig. 4b is of the order of 10%. To minimise this overshoot the level
detector circuit was altered to give the dual trip mechanism shown in
Fig. 5fl. This circuit tripped without delay if the 75° level was reached,
reached, but imposed an 8 ms delay on levels between 90° and 75°.
6O 90
Fig. Sb shows the steady-state timing contour for this trip mechanism.
9. deg
Fig. 6 shows the operating times for the 1 bit-comparator mho relay
with the new trip mechanism. The overshoot has now been reduced
to 3%, without increasing operating times in the heart of the charac-
teristic by more than 2 ms. This overshoot is now of the same order
Fig. 2 as the angular resolution of the device, i.e. 3° in 90°.
Response times for a mho characteristic To investigate the performance of the 1 bit comparator over a
a 1 bit comparator
wider range of fault conditions than could be achieved on the limited
b Block-average comparator online test facilities available, an offline computer simulation of a 128
0 = postfault phase angle bit comparator was set up. The offline simulation used a source
c = minimum timing
d = maximum timing impedance of 0-5 p.u. Z_89°, a line impedance of 1 -0 p.u. Z.85° and a
prefault phase angle = 180° ZR equal to 1 0 p.u. Z_75°. A prefault load impedance of 10 p.u. Z.0 was
connected at the end of the line. The angular resolution of a 128 bit
instant of fault incidence. comparator is 1 -5°. Fig. la shows the comparator responses for an
The voltage V and the current / measured at the junction of the impedance to fault of 0-625 Z.470. This is similar to the fault im-
source and line impedance were transformed and mixed to produce pedance in Fig. \b, and it can be seen that the two outputs are
signals Wx and W2, where Wt = Fand W2 = V~IZR.ZR was set at basically similar. Fig. 1b, c and d show comparator outputs for faults
1 p.u. L15°. A block-average comparator was supplied with the same on Z L . Trip times are shown for the 1 bit comparator with and with-
input signals Wx and W2 in order that the block-average ramp voltage out the dual trip mechanism. By interpolating between Fig. 1c and d
could be compared with the 1 bit comparator output. A storage it would appear that for faults on ZL an overshoot of 3% might be
oscilloscope was used to display expected without the dual trip mechanism and no overshoot with the
dual trip mechanism. Fig. 8a and b show trip times for the basic mho
(a) the 1 bit comparator output comparator for a selection of fault impedances. These same points
(b)W2 = V-IZR will be used in assessing a quadrilateral characteristic in Section 4.
(c) the block-average ramp voltage.
Signals (a) and (c) were arranged to ramp in opposite directions so 4 Quadrilateral characteristic
that the centre line corresponds to the trip level for both comparators. Rushton and Humpage2 have shown that for long lines the
Fig. \b and Fig. 3 show a number of traces for various fault con- mho characteristic has too great a reach in the resistive direction and
ditions. The nonlinearities in W2 were produced by the behaviour of that for short lines it does not include a substantial proportion of the

1296 PROC. IEE, Vol. 122, No. 11, NOVEMBER 1975

anticipated fault area. The same authors conclude that a quadrilateral equivalent delay of 8 x 360/128 = 225°. The effect of this delay is
characteristic is the optimum shape. to rotate the angular data from IZR to positions OA and PB in Fig.
9a. The block diagram for the quadrilateral characteristic relay is

75° trip
trip
comparator output
output
9O°trip —Cj

8ms delay

75 trip ! 90 trip
3O-- I 8ms delay

2O-

10-

3O 60 75 90
O- 9. deg

Fig. 5
Dual-trip comparator
a Block diagram
b Response times

,,+ 18%. 19-5 +

16+ i e \
"+J6 « *

Fig. 4
Trip times for the 1 bit comparator
a Fault incidence at voltage zero
b Fault incidence at voltage maximum,
n.t. = no trip; trip times in milliseconds

Two 1 bit comparators can be used to produce the characteristic

shape shown in Fig. 9a. Comparator one measures the phase angle
between Fand IZR, where ZR = 1 -1 p.u.7.65°, and has trip levels of
—33-25° and +79-25°. Comparator two measures the phase angle
between V—IZR andIZR and has trip levels of—22-5°.and +67-5°.
characteristic includes 1-02 p.u. of the line impedance at 85°.
This characteristic includes 1 -02 p.u. of the line impedance at 85°.
and negative angles. To reduce the angular limits to ± 56-75° for
comparator one and ± 45° for comparator two, the IZR squared
waveform is routed via an 8 location 1 bit shift register to produce an
Fig. 6
Trip times for the dual-trip comparator
a Fault incidence at voltage zero
n.t. = no trip; trip times in milliseconds
shown in Fig. 9b. Fig. 10 shows trip times for the relay for the same
grid of fault impedances as were used to test the mho characteristic.
The prefault impedance was 1 -0 p.u. £85° + 10 p.u. L0°. Faults

PROC. IEE, Vol. 122No. 11, NOVEMBER 1975 1297

within the characteristic were found in times varying from 12 to mechanism would add 1 -7 ms to operating times for fault angles up to
20 ms. For faults in the area between ZL and ZR the overshoot was 30°.
comparator output, deg

n.t.

H 1—I

I8O-1-

comparator output, deg

O-r

20 4O 6O 80

180 - *

comparator output, deg

0-r

Fig. 6 (continued)
Trip times for the dual-trip comparator 9O-

b Fault incidence at voltage maximum

n.t. = no trip; trip times in milliseconds

input waveforms from system 180^

Wi=V
W 3 =I
Fig. 7
Input and output waveforms for the lbit comparator
b Zp — 0"5 p.u. ^85°, fault incidence at voltage zero, trip time = 9-53 ms
c Zp — 1-Op.u. L&5°, fault incidence at voltage zero, trip time = 18-91 ms
d Zp = 1-05 p.u. LSS°, fault incidence at voltage zero, no trip

derived waveform
24-84

9O
time, ms

comparator output, deg

OT

n.t.
9O- H 1-

I8O"1-

Fig. 7
Input and output waveforms for the 1 bit comparator Fig. 8
Trip times for the 1 bit comparator mho characteristic
a Zp = 0-63 p.u. Z_47°, fault incidence at 120° after voltage zero, trip time :
lS-31ms a Fault incidence at voltage zero

less than 10%. A dual trip mechanism of direct trip at 30° and a An interesting case is where there is no prefault current, i.e. line
5 ms delay between 45° and 30° would reduce this overshoot to open circuit. Here both comparators indicate a 90° phase shift
within the angular resolution of the comparator (1 -5°). Such a

1298 PROC. IEE, Vol. 122, No. 11, NOVEMBER 1975

prefault and both have to ramp into the trip area when the fault is 5 Conclusions
applied. The directional comparator quickly indicates the direction of
The performance of the 1 bit comparator has been examined
in both mho and quadrilateral-characteristic applications. It has been

n.t. ji.t.

n.t.
n.t.
B (I6-7-I8-9)

B (16-3-19-5)

B (I5-8-2O-O)

B (I5-5-2O-O)

BII5-5-I9-8)

BII5-3-I9-5)
Fig. 8 (continued)
Trip times for the 1 bit comparator mho characteristic
b Fault incidence at voltage maximum

X
comparator two
P
Fig. 10
Trip times for the quadrilateral characteristic
a Fault incidence at voltage zero
1 blocked in 1-4 ms
B2 tripped from 17-0-22-8 ms and 36-3-43-8 ms
B3 tripped from 1 31-22-7 ms and 36-7-63-8 ms
B tripped for times shown in brackets
All times in milliseconds, prefault impedance Zj^ + 10-0 p.u. L0°

comparator one

v
f squaring comparator one trip-
V circuit level
128 bit detector
reference
impedence v
z squaring 8 bit delay trip
and circuit register output
mixing
circuits
i comparator two trip-
v
f"vz squaring level
circuit 128 bit detector

Fig. 9
Quadrilaterla characteristic using two 1 bit comparators
a Characteristic
b Block diagram
shown how the steady-state and transient timing contours can be
altered to suit a given compromise between speed of operation and
the fault and causes little delay in the operation of the protection boundary accuracy.
circuit. A typical result is shown in Fig. 11 for a 95% reach fault. Since the comparator measures rather than monitors phase

PROC. IEE, Vol. 122, No. 11, NOVEMBER 1975 1299

difference the output of the suniming amplifier can be checked during
nonfault conditions by observing that the indicated phase difference
B (19-7 -21-4)
B (I9-4-2H)
B (19-7-22-7)
B (19-5-22-7)
Fig. 10 (continued)
Trip times for the quadrilateral characteristic
b Fault incidence at voltage maximum
1 boundary case, 45 in 19-8 ms but no trip
2 blocked in 0-78 ms
B tripped for time shown in brackets
All times in milliseconds, prefault impedance Z/, + 10-0 p.u. L0°
is consistent with system operating conditions. The level detector
circuit could also incorporate an alarm signal which is triggered when
the measured phase angle approaches the trip level by less than a
prescribed amount.
The use of 1 bit comparators to produce a 3-zone distance element
incorporating a distance-to-fault measurement will be considered in
another paper.
6 References
1 JACKSON, L., PATRICKSON, J.B., and WEDEPOHL, L.M.: 'Distance
protection: optimum dynamic design of static relay comparators',
Proc. IEE, 1968, 115, (2), pp. 280-287
2 HUMPAGE, W.D., and RUSHTON, J.: 'Power-system studies for the
determination of distance-protection performance', ibid. 1972, 119, (6),
pp.677-688
7 Appendix: Circuitry for the prototype 1 bit
comparator
The prototype circuits were designed to use readily available
components and to demonstrate the design operations. The principal
integrated circuits used were the '741' series t.t.l. logic circuits.
The comparators input signals were first 'squared' using high-gain
1300
input amplifiers and t.t.l. Schmitt triggers. The resultant waveforms
therefore contained only the polarity information of the input
input waveforms for comparator one
W| =V
W 3 =IZ R
input waveforms for comparator two
W2 = I Z R
W3=IZR
i i time, ms
comparator output, degs
O-r
9O- •V- 1 h ^ 1 1 1 1
Fig. 11
Input and output waveforms for the quadrilateral characteristic
comparator
Zp = 0-95 p.u. L8S°, fault incidence at voltage zero
Output wave forms comparator one • comparator two
signals. These polarity waveforms were then compared using an
Exclusive 'OR' gate. This produced a signal whose value was T if the
input waveforms were of unlike polarity and '0' if they were of the
same polarity. This polarity coincidence waveform was then sampled
and the samples were loaded into the shift register.
The shift register was 64 bits long, comprising 8 x 8 bit shift
registers in series. At each sampling instant the register's contents
were moved along the register by one location and the new sample
was loaded into the first element. The information in the final
location was discarded. Using a sampling rate of 3-2 kHz, i.e. 64
samples per cycle, the register therefore contained one power
frequency period of coincidence data. The summation of the bit
values of each element of the shift register provided the measure of
duration of polarity noncoincidence for the previous power frequency
period, and hence a measure of the phase angle between the input
waveforms. This summation was achieved using an analogue sum-
mation amplifier. Input resistors were connected between the outputs
of each element of the shift register and the summing junction input
of the output amplifier as shown in Fig. \c and the feedback resistor
was chosen to give an output voltage range equivalent to phase angles
between 0 and 180°. The zero output voltage was equivalent to 90°,
which when using the mho-circle relay characteristic was the trip
level. The 64 input resistors for the summing amplifier were all
and the output voltage varied between ± 10 V.
PROC. IEE, Vol. 122, No. 11, NOVEMBER 1975