Nano-CMOS Circuit and

Physical Design
Chapter 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN

5.1 Introduction
5.2 ESD Standard and Models
5.3 ESD Protection Design
5.3.1 ESD Protection Scheme
5.3.2 Turn-on Uniformity of ESD Protection Devices
5.3.3 ESD Implantation and Silicide Blocking
5.3.4 ESD Protection Guidelines
5.4 Low-C ESD Protection Design for High-Speed I/O
5.4.1 ESD Protection for High-Speed I/o or Analog Pins
5.4.2 Low-C ESD Protection Design
5.4.3 Input Capacitance Calculations
5.4.4 ESD Robustness
5.4.5 Turn-on Verification
5.5 ESD Protection Design for Mixed-Voltage I/O
5.5.1 Mixed-Voltage I/O Interfaces
5.5.2 ESD Concerns for Mixed-Voltage I/O Interface
5.5.3 ESD Protection Device for a Mixed-Voltage I/O Interface
5.5.4 ESD Protection Circuit Design for a Mixed-Voltage I/O Interface
5.5.5 ESD Robustness
5.5.6 Turn-on Verification
5.6 SCR Devices for ESD Protection
5.6.1 Turn-on Mechanism of SCR Devices
5.6.2 SCR-Based Devices for CMOS On-Chip ESD Protection
5.6.3 SCR Latch-up Engineering
5.7 Summary
References