®
TOPSwitch -FX Flyback
Design Methodology
Application Note AN-25
This application note introduces a simple methodology for the
design of off-line flyback power supplies using the
TOPSwitch-FX family. It is fundamentally the same as AN-16,
“TOPSwitch Flyback Design Methodology”, which was
intended for TOPSwitch and TOPSwitch-II families. Several
modifications reflect the features of TOPSwitch-FX. In addition
to addressing basic design issues specific to TOPSwitch-FX,
many other general enhancements over AN-16 were also
implemented. A brief summary of the major differences between
this document and AN-16 is provided in Appendix B as a quick
reference for readers already familiar with AN-16.
Introduction
The design of a switching power supply, by nature, is an
iterative process with many variables that have to be adjusted to
optimize the design. The design method described in this
document consists of two major sections: The design flow chart
and the step-by-step design procedure. The flow chart shows
design sequence at conceptual level for TOPSwitch-FX flyback
power supply design. The step-by-step procedure gives details
within each step of the design flow chart including rules of
thumb and look up tables. All key equations and guidelines are
provided wherever possible to assist the readers in better
understanding and/or further optimization.
Blocking Diode
External ILIMIT Resistor
(optional)
VAC
CIN
D M
CONTROL
TOPSwitch-FX
S F
fS = 130 kHz if connected as shown.
For fS = 65 kHz, connect "F" Pin to "C" Pin
(fS option available with TO-220 only)
Figure 1. Typical TOPSwitch-FX Flyback Power Supply.
Basic Circuit Configuration
Because of the high level integration of TOPSwitch-FX, many
power supply design issues are resolved in the chip. Far fewer
issues are left to be addressed externally, resulting in one
common circuit configuration for all applications. Different
output power levels may require different values of some circuit
components, but the circuit configuration stays unchanged.
TOPSwitch-FX is a feature rich product family. Advanced
features like Under-Voltage, Over-Voltage, External ILIMIT,
Line Feed Forward, Remote ON/OFF are easily implemented
with a minimal number of external components, but do require
additional design considerations. Please refer to the
TOPSwitch-FX data sheet for details. Other application specific
issues such as constant current, constant power outputs, etc. are
beyond the scope of this application note. However, such
requirements may be satisfied by adding additional circuitry to
the basic converter configuration. The only part of the circuit
configuration that may change from application to application
is the feedback circuitry. Depending on the power supply output
requirement, one of the two feedback circuits, shown in Figures
3 and 4, will be chosen for the application.
The basic circuit configuration used in TOPSwitch-FX flyback
power supplies is shown in Figure 1, which also serves as the
Output Post Filter L, C
Clamp Zener Output Capacitor
+VD-
+
VO
-
+
+VDB- VB
-
Bias Capacitor
C
Feedback Circuit
CONTROL Pin Capacitor
and Series Resistor
PI-2581-012400
February 2000
 AN-25

1. System Requirements
VACMIN, VACMAX, fL, VO, PO, η, Z
Step 1-2
Determine System Level Requirements
and Choose Feedback Circuit
2. Choose Feedback Circuit & VB

3. Determine CIN, VMIN, VMAX

4. Determine VOR, VCLO

5. Set KP

6. Determine DMAX
Step 3-11
Choose The Smallest TOPSwitch-FX
7. Calculate Primary Peak Current IP For The Required Power

8. Calculate Primary RMS Current IRMS

9. Choose TOPSwitch-FX & fS Using AN-26

10. Set ILIMIT Reduction Factor KI

From Step 23
Calculate ILIMIT (min) & ILIMIT (max)

N
11. IP ≤ ILIMIT (min)

To Step 12

PI-2582-011400

Figure 2A. TOPSwitch-FX Design Flow Chart. Step 1 to 11.

reference circuit for component identifications used in the 3. Design the smallest transformer for the TOPSwitch-FX
description through out this application note. chosen.
4. Select all other components in Figure 1 to complete the
Design Flow design.

Figures 2A, 2B and 2C present a design flow chart showing the
complete design procedure in 37 steps. With the basic circuit
configuration shown in Figure 1 as its foundation, the logic
behind this design approach can be summarized as following:
1. Determine system requirements and decide on feedback
circuit accordingly.
2. Choose the smallest TOPSwitch-FX capable for the
required output power.
The overriding objective of this procedure is “design for cost
effectiveness”. Using smaller components usually leads to a
less expensive power supply. However, for applications with
stringent size or weight limitations, the designer may need to
strike a compromise between cost and specific design
requirements in order to achieve the optimum cost effectiveness
for the end product.

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 AN-25

From Step 11

12. Determine LP

13. Choose Core & Bobbin

Y Determine Ae, Le, AL, BW

N 14. Set NS, L

22. NS, L Iterated

15. Calculate NP, NB

16. Calculate OD, DIA, AWG

17. Calculate BM

N
18. BM ≤ 3000

19. Calculate Lg, CMA

Step 12-28
Design The Smallest Transformer
To Work with The TOPSwitch-FX Chosen

N
20. Lg ≥ 0.10 mm

N 21. 200 ≤ CMA ≤ 500

N
To Step 10 23. BP ≤ 4200

24. Calculate ISP

25. Calculate ISRMS

26. Calculate ODS, DIAS, AWGS

27. Calculate IRIPPLE

To StepPIV
28. Calculate 28 , PIV
S B

To Step 29

PI-2583-011700

Figure 2B. TOPSwitch-FX Design Flow Chart. Step 12 to 28.

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 AN-25

From Step 28

29. Select Clamp Zener & Blocking Diode

30. Select Output Rectifier

31. Select Output Capacitor

32. Select Output Post Filter L, C

33. Select Bias Rectifier

34. Select Bias Capacitor

Step 29-37
Select Other Components
35. Select CONTROL Pin Capacitor
& Series Resistor

36. Select Feedback Circuit Compenents

According to Reference Circuits
Figures 3 and 4

37. Select Bridge Rectifier

Design
Complete

PI-2584-012500

Figure 2C. TOPSwitch-FX Design Flow Chart. Step 29 to 37.

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 AN-25

Step by Step Design Procedure • Line frequency, fL: 50 Hz or 60 Hz.

• Output voltage, VO: in Volts.
This design procedure uses the TOPSwitch-FX continuous/ • Output power: PO: in Watts.
discontinuous flyback design spreadsheet (available from Power • Power supply efficiency, η: 0.8 if no better reference data
Integrations) which contains all the important equations required available. (Refer to AN-26)
for a TOPSwitch-FX flyback power supply design, and automates • Loss allocation factor, Z: If Z = 1, all losses are on the
most calculations. Designers are, therefore, relieved from the secondary side. If Z = 0, all losses are on the primary side.
tedious calculations involved in the complicated and highly Set Z = 0.5 if no better reference data available.
iterative design process. Note that all user provided inputs are in
column B and all spreadsheet calculated results are in column D. Step 2. Choose feedback circuit and bias voltage VB based
Column C is reserved for intermediate variables needed in some on output requirements
complicated calculations. Look up tables and rules of thumb are
provided where appropriate to facilitate the design task. Feedback VB Output Load* Line Ref.
Circuit (V) Accuracy Reg. Reg. Circuit
Step 1. Determine system requirements: VACMAX, VACMIN,
fL, VO, PO, η, Z Opto/Zener 15 ± 5% ± 1% ± 0.5% Figure 3
Opto/TL431 15 ± 1% ± 0.2% ± 0.2% Figure 4
• Minimum AC input voltage, VACMIN: in Volts.
• Maximum AC input voltage, VACMAX: in Volts. *Over 10% to 100% Load Range.
• Recommended AC input ranges: Table 2

Input (VAC) VACMIN (VAC) VACMAX (VAC) • Use Opto/Zener for lower cost.
• Use Opto/TL431 for better performance.
Universal 85 265 • Although not included in Table 2, primary feedback may
also be used with TOPSwitch-FX design.
230 or 115 with doubler 195 265 • Bias voltage VB: 15 V recommended. May be set to
different value if needed.
Table 1

CY1
2.2 nF
C14 R15
1 nF 150 Ω
L3 12 V
3.3 µH @ 1.7A

VR1 D8 C10 C11 C12

P6KE200 BYW29-100 560 µF 560 µF 220 µF
35 V 35 V 35 V
BR1
600 V RTN
2A
D1
UF4005 D2
L1 1N4148 R6
20 mH 22 Ω R8
T1 C6 150 Ω
100 nF
C1 U2
CX1 68 µF LTV817A
100 nF 400V D M TOPSwitch-FX
250 VAC U1 CONTROL
TOP234Y C

R5
F1 S F 6.8 Ω VR2
J1 3.15 A 1N524IC
11 V, 2%
L C5
47 µF
10 V
N
PI-2579-012400

Figure 3. Opto/Zener Feedback Reference Circuit.

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 AN-25

CY1
2.2 nF
C14 R15
1 nF 150 Ω
L3 12 V
3.3 µH @ 1.7A

VR1 D8 C10 C11 C12

P6KE200 BYW29-100 560 µF 560 µF 220 µF
35 V 35 V 35 V RTN
BR1
600 V
2A
D1
UF4005 D2
L1 1N4148 R6
20 mH C1 470 Ω R8
68 µF C6 680 Ω
400V T1
100 nF
R1
CX1 39.2 KΩ
100 nF D M TOPSwitch-FX U2
U1 LTV817A
250 VAC CONTROL
TOP234Y C
3.3 KΩ
R5
F1 S F 6.8 Ω R3 C3
J1 3.15 A 100 nF

L C5 U3 R2
47 µF TL431 10 KΩ
10 V
N

PI-2580-012400

Figure 4. Opto/TL431 Feedback Reference Circuit.

Step 3. Determine minimum and maximum DC input • Calculate maximum DC input voltage VMAX:
voltages VMIN, VMAX and input storage capacitance CIN based
on AC input voltage and PO (Figure 5) V MAX = 2 ×V ACMAX

• Choose input storage capacitor, CIN per Table 3. Step 4. Determine reflected output voltage VOR and clamp
Zener voltage VCLO based on input voltage (Figure 6)
Input (VAC) CIN (µF/Watt of PO) VMIN (V)
• Set reflected output voltage, VOR = 135 V.
Universal 2~3 ≥ 90 • Use 200 V clamp Zener, VCLO = 200 V.
• RCD (Resistor/Capacitor/Diode) clamp may be used with
230 or 115 with doubler 1 ≥ 240 TOPSwitch-FX for increased VOR and wider DMAX when
and only when current limit is set externally with current
Table 3 limit reduction as a function of line voltage. Compared to
Zener clamp, designs using RCD clamp usually have
• Set bridge rectifier conduction time, tC = 3 ms. slightly lower efficiency at light load. In addition, great
• Derive minimum DC input voltage VMIN care must be taken in RCD clamp design. Because of its
inherent variation in clamp voltage over load range, if not
designed properly, RCD clamp may fail to protect
 1 
2 × P O × −t C  TOPSwitch-FX, especially under startup or output overload
2×fL  conditions.
V MIN = (2 ×V ACMIN 2) −
η ×C IN
where units are volts, watts, Hz, seconds and farads

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 AN-25

VACMIN × 2
V+
VMIN
tC

PO = Output Power

fL = Line Frequency
(50 or 60 Hz)

tC = Conduction Angle
 1 
2 × P O × −t C  Use 3 ms if unknown
2×fL 
V MIN = (2 ×V ACMIN 2) − η = Efficiency
η ×C IN

PI-2585-012500

Figure 5. Input Voltage Waveform.

BVDSS 700 V
MARGIN = 25 V
675 V
BLOCKING DIODE FORWARD RECOVERY = 20 V
655 V

575 V

VCLM
510 V
VCLO
VOR = 135 V
VMAX 375 V

VCLO = 1.5 x VOR = 200 V

VCLM = 1.4 x VCLO = 280 V

0V 0V

Universal/230 VAC Input

Use VOR = 135 V and 200 V Zener Clamp

PI-2586-011400

Figure 6. Reflected Voltage VOR and Clamp Zener Voltage VCLO.

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 AN-25

Step 5. Set primary current waveform parameter KP for

IR desired mode of operation and current waveform: KP ≡ KRP
KP ≡ KRP = for KP ≤ 1.0 and KP ≡ KDP for KP ≥ 1.0 (Figures 7 & 8)
IP

• For KP ≤ 1.0, KP ≡ KRP, continuous mode (see Figure 7)

IR
Primary IP IR
K P ≡ K RP= where IR is primary ripple current and IP
IP
(a) Continuous, KP < 1 is primary peak current.
• For KP ≥ 1.0, KP ≡ KDP, discontinuous mode (see Figure 8)

V OR×(1 − D MAX )
IP K P ≡ K DP=
Primary IR
(V MIN −V DS) × D MAX
• For continuous mode design, set
(b) Borderline Continuous/Discontinuous, KP = 1
KP = 0.4 for universal input
PI-2587-011400
0.6 for 230 VAC or 115 VAC with doubler.
• For discontinuous mode design, set KP = 1.0.
Figure 7. Continuous Mode Current Waveform, KP ≤1. • KP must be kept within the range specified in Table 4.

KP ≡ KDP = (1-D) x T
t

T = 1/fS

Primary
DxT (1-D) x T

Secondary

(a) Discontinuous, KP > 1

T = 1/fS

Primary

DxT (1-D) x T = t

Secondary

(b) Boarderline Discontinuous/Continuous, KP = 1

PI-2578-011800

Figure 8. Discontinuous Mode Current Waveform, KP ≥1.

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 AN-25
Step 9. Choose TOPSwitch-FX based on AC input voltage,
KP
PO and η using AN-26 selection curves
Input (VAC)
Continuous Discontinuous
Mode Mode • Choose the smallest TOPSwitch-FX using TOPSwitch-FX
Universal 0.4~1.0 ≥1.0 Selection Curves in AN-26.
• Identify appropriate selection curves according to AC
230 0.6~1.0 ≥1.0 input voltage.
• Continuous mode: Use selection curves as is.
Table 4 • Discontinuous mode: Use selection curves with the output
power derated by 33%. This effectively makes a 10 W
Step 6. Determine DMAX based on VMIN and VOR discontinuous design equivalent to a 15 W continuous
design in TOPSwitch-FX selection.
• Continuous mode • Switching Frequency fS: For DIP and SMP packages, set
fS = 130 kHz. For TO-220 package, choose between
V OR
D MAX = 65 kHz and 130 kHz.
(V MIN −V DS) +V OR
Step 10. Set ILIMIT reduction factor KI for External ILIMIT
• Discontinuous mode external ⋅I LIMIT
• K I= where 0.4 ≤ KI ≤ 1.0
V OR default ⋅I LIMIT
D MAX =
K P ×(V MIN −V DS) +V OR • KI is set by the value of the resistor connected between M
pin and SOURCE pin (Refer to TOPSwitch-FX data sheet).
• Set TOPSwitch-FX Drain to Source voltage, VDS = 10 V. • For applications demanding very high efficiency, a
TOPSwitch-FX bigger than necessary may be used by
Step 7. Calculate primary peak current IP lowering ILIMIT externally to take advantage of the lower
RDS(ON).
• Continuous mode (KP ≤ 1.0) • If no special requirement, set KI = 1.0.
• Calculate ILIMIT(min) and ILIMIT(max)
I AVG
I P= I LIMIT (min) = default ⋅I LIMIT (min) × K I
1 − P  × D
K
 2 
MAX
I LIMIT (max) = default ⋅I LIMIT (max) × K I
• Discontinuous mode (KP ≥ 1.0)
Step 11. Validate TOPSwitch-FX selection by checking IP
2 × I AVG against ILIMIT(min)
I P=
D MAX • For KI = 1.0, check IP ≤ 0.96 x ILIMIT(min).
PO • For KI < 1.0, check IP ≤ 0.94 x ILIMIT(min).
• Input average current I AVG =
η ×V MIN • Choose larger TOPSwitch-FX if necessary.

Step 8. Calculate primary RMS current IRMS Step 12. Calculate primary inductance LP

• Continuous mode • Continuous mode

10 6 × PO Z × (1 − η) + η
K 2  LP= ×
I RMS = I P × D MAX × P − K P +1 η
I P 2 × K P ×1 − P  × f S(min)
K
 3   2 
• Discontinuous mode where units are µH, watts, amps and Hz

IP 2
I RMS = D MAX ×
3

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 AN-25
• Discontinuous mode. Step 14. Set value for number of primary layers L and
10 × PO
6
Z × (1 − η) + η number of secondary turns NS (may need iteration)
LP= ×
1
I P 2 × × f S(min) η • Starting with L = 2 (Keep 1.0 ≤ L ≤ 2.0 through out
2 iteration).
where units are µH, watts, amps and Hz • Starting with NS = 0.6 turn/volt.
• Both L and NS may need iteration.
• Z is loss allocation factor and η is efficiency from Step 1.
Step 15. Calculate number of primary turns NP and number
Step 13. Choose core and bobbin based on fS and PO using of bias turns NB
Table 5 and determine Ae, Le, AL and BW from core and
bobbin catalog • Diode forward voltages: 1.0 V for fast P/N diode, 0.7 V for
ultra fast P/N diode and 0.5 V for Schottky diode.
• Core effective cross sectional area, Ae: in cm2. • Set output rectifier forward voltage, VD.
• Core effective path length, Le: in cm. • Set bias rectifier forward voltage, VDB.
• Core ungapped effective inductance, AL: in nH/turn2. • Calculate number of primary turns.
• Bobbin width, BW: in mm.
V OR
• Choose core and bobbin based on fS, PO and construction N P= N S×
type. V O+ V D

65 kHz 130 kHz • Calculate number of bias turns NB.

Output
Triple Margin Triple V B+V DB
Power Margin N B= N S ×
Insulated Wound Insulated
Wound V O+ V D
Wire Wire
EFD15 EEL16 EFD15 EEL16 Step 16. Determine primary winding wire parameters OD,
EF16 EF20 EF16 DIA, AWG
EE16 EEL19 EE16
0-10 W • Primary wire outside diameter in mm.
EE22
EFD20
L × ( BW − 2 × M )
EE19 OD =
NP
EF20 EFD25 EE22 EF20
10-20 W EI25 EF25 EFD20 EEL19 where L is number of primary layers,
E24/25 EFD30 EE19 BW is bobbin width in mm,
EI30 EF20 M is safety margin in mm.
EF25 EER28 EI25 EFD25
20-30 W • Determine primary wire bare conductor diameter DIA and
EI28 EF30 E24/25 EF25
primary wire gauge AWG.
EI30 ETD29 EF25 EFD30
EF30 EER28L EI28 EI30 Step 17 to Step 22. Check BM, CMA and Lg. Iterate if
30-50 W EER28 ETD34 EER28 necessary by changing L, NS or core/bobbin until within
ETD29 EF30 specified range
EER28L
EI35 EI40 EI30 ETD29 • Set safety margin, M. Use 3 mm (118 mils) for margin
50-70 W ETD34 EER35 EF30 EER28L wound and zero for triple insulated secondary.
EER28 • Maximum flux density: 3000 ≥ BM ≥ 2000; in gauss.
EI40 ETD39 ETD29 ETD34 100 × I P × L P
EER35 EER40 EER28L EI40 BM =
EI35 EER35 N P × Ae
70-100 W
ETD34 ETD39
where units are gauss, amps, µH and cm2
EI40 EER40
EER35

Table 5.

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 AN-25

• Gap length in mm: Lg ≥ 0.1 Step 26. Determine secondary winding wire parameters
ODS, DIAS, AWGS
 NP2 1 
L g = 40 × π × Ae × −  • Secondary wire outside diameter in mm
 1000 × L P A L 
BW − (2 × M )
where Lg in mm, Ae in cm2, AL in nH/turn2 and ODS =
LP in µH
NS
• Secondary wire bare conductor diameter in mm
• Primary winding current capacity in circular mils per amp:
500 ≥ CMA ≥ 200 4 × CMAS × I SRMS 25.4
π DIAS = ×
1.27 × DIA × 2
2 1.27 × π 1000
CMA = 4 × 1000 
I RMS  25.4  where CMAS is secondary winding current capacity
in circular mils per amp. Minimum wire diameter is
where DIA is the bare conductor diameter in mm calculated by using a CMAS of 200.

• Iterate by changing L, NS, core/bobbin according to Table 6. • Determine secondary winding wire gauge AWGS based on
DIAS. If the bare conductor diameter of the wire is larger
BM Lg CMA than that of the 27 AWG for 130 kHz or 25 AWG for
65 kHz, a parallel winding using multiple strands of thinner
L ↑ - - ↑ wire should be used to minimize skin effect.
↑ ↑
NS ↑ ↑ Step 27. Determine output capacitor ripple current IRIPPLE
core ↑
size ↑ ↑ ↑ • Output capacitor ripple current

Table 6 I RIPPLE = I SRMS 2 − I O 2

Step 23. Check BP ≤ 4200 . If necessary, reduce current where IO is the output DC current
limit by lowering ILIMIT reduction factor KI
Step 28. Determine maximum peak inverse voltages PIVS,
PIVB for secondary and bias windings
I LIMIT (max)
• BP = × BM
IP • Secondary winding maximum peak inverse voltage.
• Check BP ≤ 4200 gauss to avoid transformer saturation at NS
startup and output over load. PIV S=V O+(V MAX × )
• Decrease KI if necessary until BP ≤ 4200. NP
• Bias winding maximum peak inverse voltage.
Step 24. Calculate secondary peak current ISP
NB
N PIV B=V B+(V MAX × )
• I SP = I P × P NP
NS
Step 29. Select clamp Zener and blocking diode for primary
Step 25. Calculate secondary RMS current ISRMS clamping based on input voltage and VCLO

• Continuous mode • Use 200 V Zener such as Motorola P6KE200 for the clamp.
• Use ultra fast diode such as General Instruments UF4005
KP2  for the blocking diode.
I SRMS = I SP × (1 − D MAX ) ×  − K P +1
 3  Step 30. Select output rectifier
• Discontinuous mode
• VR ≥ 1.25 x PIVS; where PIVS is from Step 28 and VR is the
1 − D MAX rated reverse voltage of the rectifier diode.
I SRMS = I SP × • ID ≥ 3 x IO; where ID is the diode rated DC current and
3 ×K P
IO = PO/VO.

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 AN-25
Step 31. Select output capacitor
• Ripple current specification at 105 °C, 100 kHz: Must be
equal to or larger than IRIPPLE, where IRIPPLE is from Step 27.
• ESR specification: Use low ESR, electrolytic capacitor.
Output switching ripple voltage is ISP x ESR , where ISP is
from Step 24.
Step 32. Select output post filter L, C
• Inductor L: 2.2 to 4.7 uH. Use bead for low current (≤ 1A)
output and standard off-the-shelf choke for higher current
output. Increase choke current rating or wire size if necessary
to avoid significant DC voltage drop.
• Capacitor C: 120 uF, 35 V, low ESR, electrolytic capacitor.
Step 33. Select bias rectifier
• VR ≥ 1.25 x PIVB; where PIVB is from Step 28 and VR is the
rated reverse voltage of the rectifier diode.
Step 34. Select bias capacitor
• Use 0.1 uF, 50 V, ceramic.
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Step 35. Select CONTROL pin capacitor and series resistor
• CONTROL pin capacitor: 47 uF, 10 V, low cost electrolytic
(Do not use low ESR capacitor).
• Series resistor: 6.2 ohm, 1/4 W (Not needed if KP ≥ 1, i.e.
discontinuous mode).
Step 36. Select feedback circuit components according to
applicable reference circuits shown in Figures 3 and 4
• Applicable reference circuit: Identified in Step 2.
Step 37. Select input bridge rectifier
• VR ≥ 1.25 x 2 x VACMAX; where VACMAX is from Step 1.
• IACRMS ≥ 2 x ID; where ID is the bridge rectifier rated RMS
current and IACRMS is the input RMS current.
PO
Note: I ACRMS = ;where VACMIN is from
η ×V ACMIN × PF
Step 1 and PF is the power factor of the power supply which
is typically between 0.5 and 0.7. If no better reference
information available, use PF = 0.5.
 AN-25

Appendix A
Multiple Output Flyback Power
Supply Design
The only difference between a multiple output flyback power Customization of secondary designs for each output
supply and a single output flyback power supply of the same The turns for each secondary winding are calculated based on
total output power is in the secondary side design. Instead of the respective output voltage VO(n):
delivering all power to one output as in single output case, a
multiple output flyback distributes its output power among V O ( n ) + V D( n )
N S ( n) = N S ×
several outputs. Therefore, the design procedure for the primary V O+ V D
side stays the same while that for the secondary side demands
further considerations. Output rectifier maximum inverse voltage is

Design with lumped output power N S ( n)

One simple way of doing multiple output flyback design is
PIV S(n) =V MAX × + V O( n )
NP
described in detail in AN-22, “Designing Multiple Output
Flyback Power Supplies with TOPSwitch”. The design method With output RMS current ISRMS(n), secondary number of turns
starts with a single output equivalent by lumping output power NS(n) and output rectifier maximum inverse voltage PIVS(n)
of all outputs to one main output. Secondary peak current ISP and known, the secondary side design for each output can now be
RMS current ISRMS are derived. Output average current IO carried out exactly the same way as for the single output design.
corresponding to the lumped power is also calculated.
Secondary winding wire size
Assumption for simplification TOPSwitch-FX design spreadsheet assumes a CMA of 200
The current waveforms in the individual output windings are when calculating secondary winding wire diameters. This gives
determined by the impedance in each circuit, which is a function the minimum wire sizes required for the RMS currents of each
of leakage inductance, rectifier characteristics and capacitor output using seperate windings. Designers may wish to use
value. Although this current waveform may not be exactly the larger size wire for better thermal performance. Other
same from output to output, it is reasonable to assume that, to considerations such as skin effect and bobbin coverage may
the first order, all output currents have the same shape as for the suggest the use of a smaller wire by using multiple strands
single output equivalent of lumped power. wound in parallel. In addition, practical considerations in
transformer manufacturing may also dictate the wire size.
Output RMS current vs. average current
The output average current is always equal to the DC load
current, while the RMS value is determined by current wave
shape. Since the current wave shapes are assumed to be the
same for all outputs, their ratio of RMS to average currents must
also be identical. Therefore, with the output average current
known, the RMS current for each output winding can be
calculated as
I SRMS
I SRMS (n) = I O(n) ×
IO
where ISRMS(n) and IO(n) are the secondary RMS current and
output average current of the nth output and ISRMS and IO are the
secondary RMS current and output average current for the
lumped single output equivalent design.

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Appendix B
AN-25 and AN-16 Comparison Table

Design Methodologies AN-16 AN-25

Applicable products TOPSwitch TOPSwitch-FX
TOPSwitch-II
Product selection basis ILIMIT(min) ≥ IP AN-26 selection curves
Product selection validation power dissipation ILIMIT(min) ≥ IP
Mode of operation continuous continuous and discontinuous
Switching frequency fS 100 kHz 130 kHz or 65 kHz
Maximum duty cycle DMAX 64% 75%
ILIMIT reduction factor KI N/A 1.0 ≥ KI ≥ 0.4
Core selection table 100 kHz 130 kHz & 65 kHz
Flux density limitation design for BM ≤ 3000 & BP ≤ 4200 design for BM ≤ 3000 & adjust ILIMIT to
meet BP ≤ 4200
Minimum gap size Lg ≥ 0.05 mm Lg ≥ 0.1 mm
Secondary winding wire size calculated based on primary CMA calculated based on CMA of 200 for
minimum wire size
Secondary side design for multiple N/A yes
outputs

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Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.

PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc.

©Copyright 2000, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086

WORLD HEADQUARTERS NORTH AMERICA - EAST EUROPE & AFRICA TAIWAN

NORTH AMERICA - WEST
Power Integrations, Inc.
477 N. Mathilda Avenue
Sunnyvale, CA 94086 USA
Main: +1•408•523•9200
Customer Service:
Phone: +1•408•523•9265
Fax: +1•408•523•9365
& SOUTH AMERICA Power Integrations (Europe) Ltd. Power Integrations International
Power Integrations, Inc. Centennial Court Holdings, Inc.
Eastern Area Sales Office Easthampstead Road 2F, #508, Chung Hsiao E. Rd., Sec. 5,
1343 Canton Road, Suite C1 Bracknell Taipei 105, Taiwan
Marietta, GA 30066 USA Berkshire RG12 1YQ, Phone: +886•2•2727•1221
Phone: +1•770•424•5152 United Kingdom Fax: +886•2•2727•1223
Fax: +1•770•424•6567 Phone: +44•1344•462•300
Fax: +44•1344•311•732

CHINA KOREA JAPAN INDIA (Technical Support)

Power Integrations, China
Rm# 1705, Bao Hua Bldg.
1016 Hua Qiang Bei Lu
Shenzhen Guangdong, 518031
Phone: +86•755•377•9485
Fax: +86•755•377•9610
Power Integrations International Power Integrations, K.K. Innovatech
Holdings, Inc. Keihin-Tatemono 1st Bldg. #1, 8th Main Road
Rm# 402, Handuk Building, 12-20 Shin-Yokohama 2-Chome, Vasanthnagar
649-4 Yeoksam-Dong, Kangnam-Gu, Kohoku-ku, Yokohama-shi, Bangalore 560052, India
Seoul, Korea Kanagawa 222, Japan Phone: +91•80•226•6023
Phone: +82•2•568•7520 Phone: +81•45•471•1021 Fax: +91•80•228•9727
Fax: +82•2•568•7474 Fax: +81•45•471•3717

APPLICATIONS HOTLINE APPLICATIONS FAX

World Wide +1•408•523•9260 World Wide +1•408•523•9361

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