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VTOP
FALL SEMESTER 2020-21 - COURSE
REGISTRATION

19BEC0202 - KASIREDDY VAMSHIDHAR REDDY - BEC - Electronics and Communication

Engineering - BTECH 09-Jul-2020 11:17:16

Note : Credits Courses

 Home Maximum 27 -
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REGISTERED COURSE(S)

Registered Course(s)

Group Course Code Course Title Course Type L T P J Credit Course Category Course Option Cla

General ECE1003 Electromagnetic Theory Only 3000 3 Programme Core Regular VL2020
(Semester) Field Theory

General ECE1004 Signals and Embedded 2000 2 Programme Core Regular VL2020
(Semester) Systems Theory

General ECE1004 Signals and Embedded 0004 1 Programme Core Regular VL2020
(Semester) Systems Project

General ECE2002 Analog Embedded 2000 2 Programme Core Regular VL2020

(Semester) Electronic Theory
Circuits

General ECE2002 Analog Embedded 0020 1 Programme Core Regular VL2020

(Semester) Electronic Lab
Circuits

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Group Course Code Course Title Course Type L T P J Credit Course Category Course Option Cla

General ECE2002 Analog Embedded 0004 1 Programme Core Regular VL2020

(Semester) Electronic Project
Circuits

General ECE2003 Digital Logic Embedded 2000 2 Programme Core Regular VL2020
(Semester) Design Theory

General ECE2003 Digital Logic Embedded 0020 1 Programme Core Regular VL2020
(Semester) Design Lab

General ENG1901 Technical Lab Only 0040 2 University Core Regular VL2020
(Semester) English - I

General MAT2002 Applications of Embedded 3000 3 Programme Core Regular VL2020

(Semester) Differential and Theory
Difference
Equations

General MAT2002 Applications of Embedded 0020 1 Programme Core Regular VL2020

(Semester) Differential and Lab
Difference
Equations

General MEE2065 Energy in Built Embedded 3000 3 University Regular VL2020

(Semester) Environment Theory Elective

General MEE2065 Energy in Built Embedded 0004 1 University Regular VL2020

(Semester) Environment Project Elective

General STS2101 Getting Started Soft Skill 0000 1 University Core Regular VL2020
(Semester) to Skill (GENERAL
Enhancement Basket)

Time Table
Registered Slots / Hours are highlighted with green color.

If there is no green highlight it indicates that there are no Registered List Slots / Hours.

Start 08:00 09:00 10:00 11:00 12:00 - Lunch 14:00

Theory
End 08:45 09:45 10:45 11:45 12:45 - Lunch 14:45
Start 08:00 08:46 10:00 10:46 11:31 12:16 Lunch 14:00
Lab
End 08:45 09:30 10:45 11:30 12:15 13:00 Lunch 14:45
MON
TB1-
Theory A1 F1 D1 MAT2002- TG1 - Lunch A2 E
ETH-TT523 T

Lab L1- L2- L3 L4 L5 L6 Lunch L31

ECE2003- Copyright
ECE2003- © 2020 Software Development Cell (VIT)
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7/9/2020 VIT - VTOP REGISTRATION
ELA-TT422 ELA-TT422

B1- G1- B2-

Theory MAT2002- ECE1004- E1 TC1 TAA1 - Lunch ECE2003-
ETH-TT523 ETH-TT313 ETH-TT313
TUE
L11- L12-
Lab L7 L8 L9 L10 ENG1901- ENG1901- Lunch L37
LO-MB229 LO-MB229
C2-
MEE2065-
Theory C1 A1 F1 V1 V2 - Lunch
ETH-
MB218
WED

Lab L13 L14 L15 L16 L17 L18 Lunch L43

G1- D2-
B1-
ECE1004- ECE2002-
Theory D1 MAT2002- TE1 TCC1 - Lunch E
ETH- ETH-
ETH-TT523 ET
TT313 TT531A
THU
L23-
L24-
ECE2002-
Lab L19 L20 L21 L22 ECE2002- Lunch L49
ELA-
ELA-TT246
TT246
E2-
STS2101- M
Theory E1 C1 TA1 TF1 TD1 - Lunch
SS-
FRI SMV102
L27- L28-
Lab L25 L26 ENG1901- ENG1901- L29 L30 Lunch L55
LO-MB229 LO-MB229
Theory V8 X11 X12 Y11 Y12 - Lunch X21
SAT
Lab L71 L72 L73 L74 L75 L76 Lunch L77
Theory V10 Y11 Y12 X11 X12 - Lunch Y21
SUN
Lab L83 L84 L85 L86 L87 L88 Lunch L89

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