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Test: Assessment: Oracle SPARC M5-32

Server Overview (WBT)


Review your answers, feedback, and question scores below. An asterisk (*) indicates a correct
answer.

This 20-question assessment test is the one of the final components of the SPARC M5-32
Servers guided learning path. This assessment will allow you to test your knowledge level
of the information learned from the SPARC M5-32 Servers courseware. Passing is
considered a score of >80%.

Assessment: Oracle SPARC M5-32 Server Overview (WBT)


(Answer all questions in this section)

1Select the three components of the SPARC M5 processor that


Mark for
. contribute to its high throughput design.
Review 
(1) Points

(Choose all correct answers)

EMS modules
L3 48MB shared cache (*)
8 SSDs per DCU
6 S3 cores per CMP (*)
Up to 8 threads per core (*)

Correct!

2Select the two statements the apply to fans in the SPARC M5-32
Mark for
. server.
Review 
(1) Points

(Choose all correct answers)

If the fans are not working for a CMU, the CMU will
continue to operate but the fans needs to be replaced within
12 hours.
If the fans are not working for a CMU, the CMU will
continue to operate but the fans needs to be replaced within
24 hours.
If there is an issue with a fan, the SPP informs the SP of any
cooling issues and the SP adjusts the fans if needed. (*)
If the fans are not working for a CMU, there will be no
airflow so the CMU will be shutdown. (*)
If there is an issue with a fan, the SPP adjusts the fans if
needed.

Sorry, that is not correct. Please review the course content


and try again.

3The SPARC M5-32 server comes configured with _________


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. PDOM(s). Select the number that is true.
Review 
(1) Points

1 (*)
2
4
0

Correct!

4How many SP Proxies are supported by a Service Processor


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. (SP)? Select the correct number.
Review 
(1) Points

2
8
4 (*)

Correct!

5Select the three options that are true for Clock Boards in the
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. SPARC M5-32 server.
Review 
(1) Points

(Choose all correct answers)


One clock board is redundant for failover (*)
Two Clock Boards are active
One clock board is active (*)
Two Clock Boards (*)
Only one Clock Board

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11Select the
Mark for
. statement
Review 
that is true
(1) Points
for an
IOU’s
components
.

One I/O board, four EMS and sixteen PCI slots and
eight HDDs/SSDs.
Two I/O boards, four EMS and sixteen PCI slots and
eight HDDs/SSDs. (*)
Two I/O boards, two EMS and sixteen PCI slots and
eight HDDs/SSDs.

Correct!

12. There can be _______Dynamic Domains (Physical


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Domains or PDoms) in the M5-32 Server. Select the
Review 
statement that fills in the blank.
(1) Points

1
up to 2
up to 4 (*)
up to 8
up to 32

Correct!

13. What size DIMMs are supported in the SPARC M5-32


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server? Select all the sizes that apply.
Review 
(1) Points

(Choose all correct answers)

16 GB (*)
48 GB
32 GB (*)
8 GB

Correct!

14. Select the statement that is true regarding the SPARC


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M5-32 server Bixby ASICs.
Review 
(1) Points

Each group of six Bixby ASICs can have a loss of


one SSB and the SPARC M5-32 server can run in a
degraded mode of five but the Coherency Directory
is not available.
Each group of six Bixby ASICs can have a loss of
one SSB and the SPARC M5-32 server can run in a
degraded mode of five and the Coherency Directory
is still available. (*)
Each group of six Bixby ASICs can have a loss of up
to three SSBs and the SPARC M5-32 server can run
in a degraded mode of five and the Coherency
Directory is still available.

Correct!

15. What is the maximum number of Logical Domains that


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can be supported in a SPARC M5-32 server? Select the
Review 
correct number.
(1) Points

32
512 (*)
128
1024
64

Correct!
16There are
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. two types
Review 
of
(1) Points
Dynamic
Domains.
Select the
three
statement
s that are
true.
(Choose all correct answers)

The Application Programmer can set the attribute of


the Dynamic Domain.
A regular Dynamic Domain (or PDom) can be
expanded beyond eight SPARC M5 processors. (*)
A Bounded Dynamic Domain (or Bounded PDom) is
limited to eight SPARC M5 processors in a single
Domain Configuration Unit (DCU). (*)
A Bounded Dynamic Domain (or Bounded PDom) is
limited to thirty two SPARC M5 processors in a single
Domain Configuration Unit (DCU).
The System Administrator sets the attribute of the
Dynamic Domain by setting the variable expandable to
either true or false. (*)

Sorry, that is not correct. Please


review the course content and try
again.

17. The SPARC M5-32 server using its maximum CPU


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capacity has a total of ____ cores. Select the valid
Review 
configuration.
(1) Points

32
192 (*)
8
4
6

Correct!

18. Select the three statements that apply to each SPP in the
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SPARC M5-32 server.
Review 
(1) Points

(Choose all correct answers)

Manages a maximum of 8 CPUs (or 4 CMUs) (*)


Monitors 8 fans (*)
Manages only 4 CPUs (or 2 CMUs)
Monitors 4 fans
Manages rKVMS activity (*)

Correct!
19. Select three statements that apply to the SPARC M5-32
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server.
Review 
(1) Points

(Choose all correct answers)

All DCUs are treated like one DCU.


It uses four SPPs. (*)
1 SPP is chosen as the "Golden SPP". (*)
Audit logs are forwarded from the SPP to Main-SP. (*)
It uses one SPP.

Correct!

20. The SPARC M5-32 server is designed specifically for


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virtualization. Select the statement that is true.
Review 
(1) Points

The SPARC M5-32 server provides three SPARC


virtualization technologies: Dynamic Domains, Logical
Domains, and Solaris Zones. (*)
The SPARC M5-32 server provides the Dynamic
Domain SPARC virtualization technology.
The SPARC M5-32 server provides two SPARC
virtualization technologies: Dynamic Domains and
Logical Domains.

Correct!

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